Event-driven logic circuit

Abstract

A logic circuit comprises: an event generator (10) for detecting a variation in data outputted from a signal source (100) to generate an event which indicates the variation of the data; a plurality of propagation elements (20) for propagating the event in a chained fashion; and a plurality of evaluation elements (30) for evaluating data received at a first stage from the signal source (100) to propagate a result of the evaluation in a chained fashion. When receiving the event, each of the plurality of evaluation elements (30) evaluates the data inputted to the evaluation element. A logic circuit is realized wherein both an input load and an activation yield are reduced, and a high speed operation is realized with low power consumption.

Description

technical field [0001] The present invention relates to a logic circuit, in particular to a circuit structure technique for reducing delay and power consumption of sequential circuits. Background technique [0002] In current semiconductor integrated circuits, static circuits centered on CMOS (Complementary Metal Oxide Semiconductor) circuits are widely used. CMOS circuits have the following advantages: If the input does not change, the output does not change, and the current consumption is only a small leakage component and the activation component generated when the value shifts, and the current consumption is small. The disadvantages of the CMOS circuit can be cited as follows: the power delay product is relatively large when realizing high-speed operation. [0003] Figure 62 It is a diagram showing a CMOS circuit based on a concept. In general, a CMOS circuit has a circuit for realizing a logic operation of an evaluation function f and a complementary function f* whic...

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Problems solved by technology

[0005] However, the following problem has been pointed out: in the dynamic circuit, since the initialization phase and the evaluation phase are alternately operated continuously, the activation rate is higher than that of the static circuit

Due to the principle of detecting changes in input signals, the application of clock control corresponding to changes in input signals is limited to sequential elements such as flip-flops and memories.

[0010] In this way, the increase of the input load in the static circuit, the increase of the activation rate in the dynamic circuit and the difficulty of the design, the occurrence of the overhead of the handshake circuit in the asynchronous circuit and the difficulty of the design, and the difficulty of the design according to the input signal Applicable restrictions in changing clock control, etc., make it difficult for logic circuits to achieve high speed and low power consumption at the same time

As in static circuits, the results of evaluating signals input to functions are propagated successively, or as in dynamic circuits, the results of evaluating signals are input to functions at intervals are propagated. As long as the circuit operation is based on one of these methods, it is difficult to solve it at the same time. Issues such as signal loading, activation rate, and circuit size

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