Semiconductor memory device using only single-channel transistor to apply voltage to selected word line

Abstract

A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first conductivity type. A source or drain of the first transistor is connected to each of word lines. A drain of the second transistor is connected to a gate of the first transistor. A source of the third transistor is connected to the gate of the first transistor. The gates of the second transistor and the third transistor are not connected, a source of the second transistor is not connected to a drain of the third transistor, and the gate of the second transistor and the drain of the third transistor have different voltage levels corresponding to opposite logic levels each other.

Description

[0001] This application is a divisional application of the invention patent application with the application number 01120869.4, the application date is June 8, 2001, and the invention title is "semiconductor storage device that only uses single-channel transistors to transmit voltage to selected word lines". technical field [0002] The present invention relates to a semiconductor storage device, and more specifically to a nonvolatile semiconductor storage device such as a NAND cell, a NOR cell, a DINOR cell, and an AND cell type EEPROM. Background technique [0003] Conventionally, an electrically rewritable EEPROM is known as a semiconductor memory device. What is striking is that the NAND cell type EEPROM, in which a plurality of memory cells are connected in series to form a NAND cell block, can be highly integrated. [0004] A memory cell, one of the NAND cell types EEPEOM, has a FET-MOS structure in which a floating gate (charge storage layer) and a control gate are la...

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Problems solved by technology

Therefore, there is a problem that the pattern area of ​​the row decoder circuit increases

[0025] In addition, in order to solve this problem, if the transistors connected to the word lines are provided as one per word line in the row decoder circuit, a pump circuit is required in the row decoder circuit, and since the pattern area of ​​the pump circuit increase, there is still the problem of increasing the graphic area of ​​the row decoder circuit

[0026] Furthermore, when the row decoder circuit is provided with one transistor connected to the word line per word line, and no pump circuit is provided in the row decoder circuit, it cannot be achieved without a voltage drop. Sending high voltage for writing to the word line increases the risk of insufficient data writing operation

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