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Regenerative clock repeater

A repeater and clock technology, applied in the field of clock signal distribution, can solve the problems of large k_opt value and large minimum propagation delay, etc.

Inactive Publication Date: 2006-07-26
ATMEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If the RC value of the allocated line is very high, the k_opt value will be large and the minimum propagation delay at this optimal value may still be large

Method used

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  • Regenerative clock repeater
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  • Regenerative clock repeater

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0027] Referring to FIG. 5, a low logic level (V L ) and a high logic level (V H ) of the regenerative clock generator 700 includes: an edge detection circuit 500 and an output driver circuit 706 . Edge detection circuit 500 receives clock signal CK from a segment of clock distribution line 702 characterized by inherent RC impedance 704 IN , and generates a pull-up control signal (PULL-UP#) or a pull-down control signal (PULL-DOWN) based on the logic level of the clock signal 702 . The pull-up control signal (PULL-UP#) is generated by detecting that the rising edge of the clock signal exceeds the low threshold voltage level, and the pull-down control signal (PULL-DOWN) is generated by detecting the falling edge of the clock signal. generated at high threshold voltage levels. The output driver 706 has a high logic level (V H ) connected to the power supply pull-up transistor 706A (usually P-type) and at a low logic level (V L ) (typically ground) is connected to a power su...

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PUM

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Abstract

A regenerative clock repeater comprises an edge detector and an output driver means to produce the clock signal by recovering its high logical level and low logical level. The output driver means further comprises a pull-up and a pull-down circuitry adapted to receive a pair of control signals. These control signals are generated by the edge detector to sense the rising edge and falling edge of the clock signal. Inside the edge detector, a pair of threshold level detectors detect a high and a low logical level of the clock signal and inputs the results to a combination of logic gates and a latch to keep the locations of the signal markers fixed. These fixed-location of control signals trigger the output driver means to recover the high logical level and the low logical level of said clock signal.

Description

technical field [0001] The present invention relates to a clock signal distribution in a memory integrated circuit, and more particularly to a clock repeater arranged along a clock line to recover the logic level of the clock signal. Background technique [0002] In a digital synchronous system, efficient clock distribution is necessary for the system to function properly. Inappropriately slow propagation of the clock signal can limit the ability of system elements to remain sufficiently synchronized with each other. In addition, a degraded clock signal can completely fail the system, even if the other parts are flawless design and components. see figure 1 , the representative clock distribution line 100 includes a low logic level V L and high logic level V H The reference clock signal 102 , the clock input buffer or driver 104 . Distribution line 100 has inherent resistance (R) and capacitance (C) 106 and load capacitance 108 at the receiving end. The clock signal 102...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K5/01G06F1/10H01LH03K19/017
CPCG06F1/10H03K19/01721
Inventor S·西韦罗M·弗卢里欧
Owner ATMEL CORP