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Semiconductor memory module

A memory module and semiconductor technology, applied in semiconductor devices, static memory, memory systems, etc., can solve the problems of high number of pins, difficult to implement, high cost, etc., and achieve the effect of improving heat distribution and reducing operating temperature.

Inactive Publication Date: 2006-08-09
INFINEON TECH AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, for differential signaling, the required pin count is significantly higher, which is very difficult to implement (or leads to high cost) from a technical point of view

Method used

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  • Semiconductor memory module
  • Semiconductor memory module
  • Semiconductor memory module

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0025] exist figure 1 In the first embodiment of the present invention schematically shown in , the chip package 11 ( figure 2 shown in detail in ) is arranged at an approximately central position on the semiconductor memory module 10, which in this example is an RDIMM module mounted with DDR-DRAM chips 4 each storing eight data items D and Another DDR-DRAM chip 4a for error correction (DE-CC). Outside the semiconductor memory module 10, the 8-bit wide data line portion supplies write and read data to the DDR-DRAM chips 4 and 4a. The differential clock signal input line 61 supplies the clock signal C1 to the common chip package 11 from the pin contact 8, and the line portion 71 with a specific bit width also supplies the command and address input signal CA to the common chip package from the pin contact 8. Body 11. From figure 2 As can be seen in , in this example, clock signal regeneration circuit 12 and register circuit 13 multiply clock signal 61 and CA signal 71 by ...

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PUM

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Abstract

A semiconductor memory module includes a plurality of semiconductor memory chips and bus signal lines that supply an incoming clock signal and incoming command and address signals to the semiconductor memory chips. A clock signal regeneration circuit and a register circuit are arranged on the semiconductor memory module in a common chip packing connected to the bus signal lines. The clock signal regeneration circuit and the register circuit respectively condition the incoming clock signal and temporarily store the incoming command and address signals, respectively multiply the conditioned clock signal and the temporarily stored command and address signals by a factor of 1:X, and respectively supply to the semiconductor memory chips the conditioned clock signal and the temporarily stored command and address signals.

Description

technical field [0001] The present invention relates to a semiconductor memory module, wherein, on the semiconductor memory module are arranged: several semiconductor memory chips; bus signal lines each supplying at least an input clock signal and an input command and address signal to the semiconductor memory chip; and a semiconductor memory chip The circuit includes a buffer register circuit and a clock signal regeneration circuit. Background technique [0002] Current memory systems (DDR1; DDR2; DDR3) offer the possibility to provide only one CA bus version (copy) to the DIMM command / address bus carrying command and address signals (CA), e.g. (fly-by) bus. With a further increase in processing speed and taking into account the high parallelism of the CA bus (eg up to 36 memory chips per CA bus), it is no longer possible to facilitate the transmission of command and address signals. [0003] One possible solution to the above problem is to use two copies of the CA bus. ...

Claims

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Application Information

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IPC IPC(8): H01L25/00G11C7/00G06F12/00
CPCG11C5/04G11C5/063G11C7/222G11C11/4093G11C11/4096G11C2207/2254
Inventor H·鲁克鲍尔A·巴哈C·西歇尔特D·萨维纳克P·格雷戈里乌斯P·瓦尔纳
Owner INFINEON TECH AG