Method for increasing RAM utilizing efficiency
A technology of efficiency and clock frequency, applied in the field of digital circuit design, can solve the problem of low utilization rate of RAM, achieve the effect of improving utilization efficiency and saving resources
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Embodiment 1
[0023] Embodiment one, as attached figure 2 As shown, for a FIFO whose bit width is wider than that of dual-port RAM, the way to read and write data can be modified. First, the RAM clock is separated from the FIFO clock, and the write clock and read clock of RAM are set. The frequency is FIFO n times the clock frequency, the data written externally to the FIFO is divided into n parts, which are represented by "write data 1", "write data 2" ... "write data n-1", "write data n", and will be read from the FIFO The read data is also divided into n parts, respectively represented by "read data 1", "read data 2" ... "read data n-1", "read data n", since the write clock frequency of RAM is the FIFO write clock frequency n times of that, the RAM read clock frequency is n times of the FIFO read clock frequency, and the RAM bandwidth is correspondingly n times of the FIFO bandwidth. When external data is written into the FIFO, each RAM clock cycle writes 1\n copies of the data written...
Embodiment 2
[0026] Embodiment 2, if the FIFO width is the same as that of the dual-port RAM, the RAM space can also be divided into multiple parts by the method of the present invention, and a plurality of FIFOs are used to generate a plurality of FIFOs, so as to overcome the aforementioned block of RAM blocks only Defects that can be assigned to a module for use. as attached image 3 As shown, first separate the RAM clock from the FIFO clock, set the RAM write clock and read clock, and its frequency is n times the FIFO clock frequency. After modifying the clock, the RAM bandwidth is n times the FIFO bandwidth. In addition, it is necessary to modify each logic module inside the FIFO, divide the dual-port RAM into n parts (each part can be different in size), respectively "RAM1", "RAM2" ... "RAMn", and expand the external FIFO interface to n They are "FIFO1", "FIFO2", ... "FIFOn", and each FIFO uses its corresponding RAM. During the write operation, n FIFOs write data in one external FIF...
Embodiment 3
[0027]Embodiment three, in the above-mentioned two kinds of methods, the first method is that a FIFO takes up all time slices (n RAM clock cycles) of RAM, and the second method is that a FIFO takes up a time slice of RAM (1 RAM clock cycles). In fact, the two methods can also be used in combination. The internal RAM clock frequency can be increased to n times the external FIFO clock frequency, and then the RAM is divided into m parts corresponding to the external m FIFOs (m is less than or equal to n), and the RAM time slice (Clock cycle) is reasonably allocated to each FIFO, which can meet the needs of FIFOs with different widths and depths. For example: m=3, n=4, then 3 FIFOs can be generated, one of which occupies 2 time slices, and the data width is twice that of RAM. The other two each occupy a time slice, and the data width is the same as that of RAM. Similarly, if m=2 and n=4, two FIFOs can be generated, and each FIFO occupies two time slices, and the data width is tw...
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