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Method for preapring nano size pit on gallium arsenide substrate

A nano-scale, GaAs technology, used in final product manufacturing, sustainable manufacturing/processing, semiconductor/solid-state device manufacturing, etc., can solve problems such as high manufacturing efficiency, dislocation defects, and low efficiency

Inactive Publication Date: 2007-01-24
INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] So far, the method of preparing nanometer-sized pits on GaAs substrates is mainly the method of direct photolithography, which is inefficient, easy to introduce dislocation defects, and high cost
The method for preparing nanometer-sized pits on the gallium arsenide substrate proposed by the present invention utilizes the self-organization method. Compared with the method of direct photolithography, the production efficiency is high, the defect is few, and the cost is low. At present, there is no report at home and abroad.

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  • Method for preapring nano size pit on gallium arsenide substrate
  • Method for preapring nano size pit on gallium arsenide substrate

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Experimental program
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Effect test

Embodiment

[0035] (1) Main equipment for realizing the invention

[0036] Molecular Beam Epitaxy System

[0037] Mechanical vacuum pump + diffusion vacuum pump (or other vacuum equipment)

[0038] temperature control system

[0039] (2) According to the specific conditions of the growth equipment, make appropriate adjustments to the growth technology route.

example

[0041] (1) Main equipment for realizing the invention

[0042] Riber32 Molecular Beam Epitaxy System

[0043] Mechanical vacuum pump + diffusion vacuum pump (or other vacuum equipment)

[0044] temperature control system

[0045] (2) Using semi-insulating gallium arsenide (001) single crystal as the substrate;

[0046] (3) Epitaxial growth of 200nm gallium arsenide buffer layer on gallium arsenide substrate by molecular beam epitaxy system;

[0047] (4) At, 500°C, 4.0×10 -6 Torr's As 2 Heteroepitaxial growth of 2.7 molecular monolayer (ML) indium arsenide in the atmosphere, and the formation of self-assembled nano-dots was observed by the high-energy electron diffraction system;

[0048] (5) epitaxy a GaAs thin layer with a thickness of 2nm, so that it partially covers the above-mentioned InAs nanodots;

[0049] (6) Annealing at 500°C for 40 seconds;

[0050] (7) The substrate temperature is lowered to 400°C;

[0051] (8) The temperature of the substrate is raised to 5...

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Abstract

This invention relates to a method for preparing nm pits on a GaAs substrate including the following steps: 1, taking a semi-insulating GaAs single wafer as the substrate, 2, heterogeneously and epitaxially growing InAs strain self-assembled nm points, 3, extending the GaAs thin layer to cover part of said InAs nm points, 4, annealing for the first time, 5, reducing the temperature of the substrate to below 400deg.C, 6, rising the temperature of the substrate to 500-530deg.C, 7, annealing the second time to form nm pits on the substrate.

Description

Technical field [0001] The invention provides a method for preparing nano-sized pits on a gallium arsenide substrate, particularly a method of partially covering indium arsenide nanodots with gallium arsenide, annealing at high temperature, then cooling, then raising the temperature, and then annealing. method. Background technique [0002] Semiconductor materials and nanomaterials are the two key and hot areas of current materials science. Combining the quantum properties of nanomaterials with the energy band properties of semiconductor materials is a very important branch of semiconductor physics and an important way to create new functional devices. The performance of optoelectronic devices, such as lasers and detectors, made from low-dimensional semiconductor heterojunction materials has been rapidly improved, and they have quickly entered the market and are widely used. Therefore, the preparation of nano-semiconductor materials is of great significance for both materi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/18H01L33/00H01L31/18
CPCY02P70/50
Inventor 李凯叶小玲王占国
Owner INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI