Semiconductor memory device and driving method thereof

Abstract

The present invention provides a semiconductor memory device and a driving method for initializing an internal logic circuit in the semiconductor memory device in a stable state of a source voltage without additional reset pins. The semiconductor memory device includes: a power supply signal generating unit for generating a power supply signal; and an internal reset signal generating unit for generating an internal reset signal in response to a pad signal input from any external pin during a test mode. a reset signal; an internal logic initialization signal generating unit configured to generate an internal logic initialization signal based on the power supply signal and the internal reset signal; and an internal logic unit initialized in response to the internal logic initialization signal.

Description

technical field [0001] The present invention relates to a semiconductor memory device, and more particularly to a technique for initializing an internal logic circuit of the semiconductor memory device. Background technique [0002] Generally speaking, a semiconductor storage device includes a plurality of internal logic circuits and internal supply voltage generating blocks. The internal supply voltage generation block generates a plurality of internal supply voltages such as a core voltage VCORE, a peripheral voltage VPERI and a bit line precharge voltage VBLP from a source voltage VDD input from an external source to further ensure stable operation. Herein, the core voltage VCORE is used to read data from or write data to the memory cells, and the peripheral voltage VPERI is used to operate internal logic circuits included in the semiconductor memory device. [0003] The internal logic circuits should be powered by the internal supply voltage to allow them to initialize ...

AI Technical Summary

Problems solved by technology

[0011]However, most semiconductor memory devices do not include additional initialization facilities such as dedicated external reset pins

As a result, it is difficult to deal with errors occurring in the steady state of the source voltage VDD

Images