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Decoupled complementary mask patterning transfer method

A patterning and patterning technology, which is applied in the direction of semiconductor devices, electrical components, circuits, etc., can solve the problems that cannot be realized, and aggravate the difference in vertical etching depth

Active Publication Date: 2007-05-02
NXP USA INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

These advantages include individually adjusted exposure conditions for each mask, elimination of flare effects that cause unwanted interactions between exposures, photoresist trimming on anchored features (trimming) (before cutting the mask), and the inclusion of assist features, however, these advantages may not be realized due to image coupling effects
Unfortunately, existing solutions exacerbate the vertical etch depth difference between the two mask transfers, resulting in excessive active pitting at the gate, for example

Method used

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  • Decoupled complementary mask patterning transfer method
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  • Decoupled complementary mask patterning transfer method

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Embodiment Construction

[0023] 1 shows a cross-sectional view of a stack 100 used in a split complementary mask patterning method (eg, in a gate patterning process flow) according to one embodiment of the present invention. Stack 100 includes substrate 102 , gate dielectric 104 over substrate 102 , target layer 106 over gate dielectric 104 , and first hard mask 110 over target layer 106 . Substrate 102 may comprise, for example, a bulk substrate, a bonded wafer substrate (e.g., semiconductor-on-insulator, silicon-on-insulator, germanium-on-insulator, or the like), or other substrates suitable for a particular semiconductor Substrates for device fabrication. Gate dielectric 104 may include, for example, gate oxide, SiON, metal oxide, or other dielectric suitable for a particular semiconductor device fabrication. Target layer 106 may include, for example, a polysilicon layer, a metal layer, a metal oxide layer, a dielectric layer, or other layers suitable for a particular semiconductor device fabricat...

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Abstract

A patterning method allows for separate transfer of a complementary reticle set. In one embodiment, for example, the method includes etching a phase shift mask (PSM) [112], then etching a cut mask for a cPSM mask (110). Moreover, a decoupled complementary mask patterning transfer method includes two separate and decoupled mask patterning steps which form combined patterns through the use of partial image transfers into an intermediate hard mask (112) prior to final wafer patterning. The intermediate (112) and final hard mask (110) materials are chosen to prevent image transfer into an underlying substrate (102) or wafer prior to the final etch process.

Description

technical field [0001] The present invention relates to semiconductor device processing, and more particularly, to a decoupled complementary mask patterning transfer method. Background technique [0002] A standard dual-mask patterning scheme, such as a complementary phase shift mask (cPSM, cPSM), needs to expose the phase shift mask and the dicing mask before etching. However, there is the advantage of transferring each mask pattern to the substrate separately. These advantages include individually adjusted exposure conditions for each mask, elimination of flare effects that cause unwanted interactions between exposures, photoresist trimming on anchored features (trimming) (before cutting the mask), and include assist features, however, these advantages may not be realized due to image coupling effects. Unfortunately, existing solutions exacerbate the vertical etch depth difference between the two mask transfers, resulting in excessive active pitting, for example, at the ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/302H01L21/461H01L21/4763H01L21/3205H01L21/8242H01L21/28H01L21/3213H01L21/331H01L21/8222H10B12/00
CPCH01L21/32139H01L21/28123
Inventor 塔伯·A·斯蒂芬忠-诚·付查尔斯·F·金
Owner NXP USA INC