Split gate field effect transistor with esd discharge path

Abstract

This invention discloses a split-gate field-effect transistor with an ESD discharge path, comprising a low-resistivity N+ substrate, with a drain metal and an epitaxial layer at both ends of the low-resistivity N+ substrate, respectively. The top of the epitaxial layer has several trenches, the sidewalls of which are covered by a first dielectric layer. A split gate and a control gate are disposed within the trenches. The control gate and the split gate are isolated by a second dielectric layer within the active region, and short-circuited within the transition region. The short-circuited portion of the control gate has several P-type regions, which are connected by N-type regions. This invention introduces multiple PN junctions between the control gate and the split gate in the transition region of a conventional split-gate field-effect transistor, forming back-to-back Zener diodes. When an ESD event occurs, static charge is discharged through the Zener diodes, thereby ensuring that the voltage between the gate and source does not exceed the rated gate-source voltage, preventing gate-source breakdown and device damage.

Description

Technical Field

[0001] This invention relates to a split-gate field-effect transistor with an ESD discharge path. Background Technology

[0002] Split-gate MOSFETs (SGT-MOS) are advanced power semiconductor devices that utilize a vertically grounded field plate inserted into the semiconductor epitaxial material. This modulates the electric field of the epitaxial material and provides shielding between the gate and drain, reducing the specific on-resistance and improving switching efficiency. This results in lower device losses in both steady-state and dynamic states, making them a highly competitive product category in low- and medium-voltage power semiconductor devices. Related products are mainly used in emerging fields such as power management, motor control, inverters, and energy storage systems. However, due to their unique structure, split-gate MOSFETs are susceptible to electrostatic discharge (ESD). Specifically: 1. The split gate and trench structure disperses the ESD current path, making it difficult for punch-through protection methods to cover all sensitive nodes. 2. The bottom of the deep trench easily forms a high electric field region during ESD events, triggering localized avalanche breakdown. 3. The high cell density of the split gate prevents the high heat generated by ESD events from dissipating quickly, causing localized metal melting or semiconductor material melting. 4. Split-gate devices utilize the charge balance principle to improve device performance, but are sensitive to process precision. ESD protection structures must be implemented without significantly increasing processing costs or affecting process precision. Summary of the Invention

[0003] The purpose of this invention is to address the problem that when an ESD event occurs, a transient high voltage is generated between the ports of a split-gate field-effect transistor. If no protection is provided, this voltage can lead to electrical failure or even thermal failure, resulting in device burnout. This invention proposes a split-gate field-effect transistor with an ESD discharge path. In addition, to adapt to different split-gate field-effect transistor process routes, specific implementation process solutions are provided.

[0004] The technical solution of this utility model: A split-gate field-effect transistor with an ESD discharge path includes a low-resistivity N+ substrate. Drain metal and an epitaxial layer are respectively disposed at both ends of the low-resistivity N+ substrate. Several trenches are formed on the top of the epitaxial layer, and the sidewalls of the trenches are covered by a first dielectric layer. A split gate and a control gate are disposed within the trenches. The control gate and the split gate are isolated by a second dielectric layer within the active region and short-circuited within the transition region. Several P-type regions are provided in the short-circuited portion of the control gate, and these P-type regions are connected by N-type regions. The top of the epitaxial layer is covered by an intermetallic isolation dielectric. A gate metal and a source metal are disposed on the top of the intermetallic isolation dielectric. A protrusion extending through the intermetallic isolation dielectric and into the control gate is provided in the middle of the gate metal, and a protrusion extending through the intermetallic isolation dielectric and into the split gate is provided in the middle of the source metal.

[0005] The control gate and the split gate are distributed vertically or horizontally within the trench; When distributed vertically, the control gate is placed above the split gate; When distributed left and right, the control gate is placed on both sides of the top of the split gate.

[0006] Field limiting loops can be installed on both sides of several P-type regions.

[0007] The P-type region is a doped region with the opposite doping type to the control gate, and the N-type region is a doped region with the same doping type as the control gate.

[0008] The beneficial effects of this utility model are: This invention incorporates a lateral back-to-back Zener diode in the transition region between the active and terminal regions of a split-gate field-effect transistor (FET) to connect the gate and source, creating an ESD discharge channel. When an ESD event occurs, static charge flows out of the device through this channel, thus mitigating ESD. Regarding cost, since the added structure is located in the transition region, and the split gate of a split-gate FET needs to be grounded, there is a natural gap of approximately 20 μm between the split gate and the control gate. This is sufficient to create multiple independent P-type regions forming a back-to-back Zener diode. Therefore, the added structure does not increase chip area or thus cost. In terms of process complexity and compatibility, this invention only requires one additional ion implantation step in the traditional split-gate FET process and does not alter the trench morphology or the oxide layer structure of the trench walls that affect the voltage withstand capability and reliability of the split gate structure. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of the principle of the split-gate field-effect transistor with ESD discharge path of this utility model.

[0010] Figure 2 This is a schematic diagram of the structure of the control gate and the split gate of this utility model when they are distributed vertically and connected to the metal layer.

[0011] Figure 3 This is a schematic diagram of the three-dimensional structure of a traditional device.

[0012] Figure 4 This is a schematic diagram of the structure when the control grid and the split grid of this utility model are distributed vertically.

[0013] Figure 5 This is a schematic diagram of the structure of the control gate and the split gate of this utility model when they are distributed left and right.

[0014] Figure 6 This is a schematic diagram of the three-dimensional structure of a traditional device using a left-right split manufacturing process.

[0015] Figure 7 This is a schematic diagram of the structure of a field-limited loop that is synchronously fabricated using the transition region of this utility model.

[0016] Figure 8 This is a comparison chart of the port voltage and current curves of this utility model and traditional devices under ESD events.

[0017] Figure 9 This is a process flow diagram of the transistor fabrication method with the split-top and split-bottom structure in Examples 1 and 2.

[0018] Figure 10 This is a process flow diagram of the transistor fabrication method with a split structure in Example 3.

[0019] Figures 11 to 22 This is a process flow diagram of the manufacturing method of Example 1 and Example 2.

[0020] Reference numerals: 1-Drain metal, 2-Low-resistivity N+ substrate, 3-High-resistivity N-epitaxial layer, 4-First dielectric layer, 5-Second dielectric layer, 6-Control gate, 7-Split gate, 8-First P-type region, 9-First N-type region, 10-Second P-type region, 11-Second N-type region, 12-Third P-type region, 13-Gate metal, 14-Source metal, 15-Intermetallic isolation dielectric, 16-Cell P-type region, 17-First field-limiting ring P-region, 18-Second field-limiting ring P-region, 19-Third field-limiting ring region. Detailed Implementation

[0021] Example 1: like Figure 1A split-gate field-effect transistor with ESD protection includes a drain metal 1, a low-resistivity N+ substrate 2 above the drain metal electrode, a high-resistivity N- epitaxial layer 3 above the low-resistivity N+ substrate, a deep trench region above the high-resistivity N- epitaxial layer, wherein, from bottom to top, there are dielectric layers 4, a split gate 7 extending vertically into the trench above the dielectric layers, a dielectric layer 5 on the upper left side of the split gate, and, from left to right, a control gate 6, a first P-type region 8, a first N-type region 9, a second P-type region 10, a second N-type region 11, and a third P-type region 12 on the upper part of the dielectric layer 5, with the right side of the P-type region 12 connected to the split gate 7; a gate metal 13 above the control gate, a source metal 14 above the split gate, and a dielectric 15 between the gate metal and the source metal. The number of P-type and N-type regions on the upper part of the dielectric layer 5 can be adjusted.

[0022] This invention incorporates a lateral back-to-back Zener diode in the transition region between the active and terminal regions of a split-gate field-effect transistor to connect the gate and source. The two ends of the diode are connected to the gate of the active region and the source field plate at the edge of the transition region, respectively. Figure 1 As shown, when an ESD event occurs, the electrostatic potential between the gate and source is greater than the Zener diode's startup voltage. The static charge will be discharged through the Zener diode, which clamps the potential difference between the gate and source at its sustaining voltage, thus ensuring that the voltage between the gate and source does not exceed the rated gate-source voltage, preventing gate-source breakdown and device damage. The static charge will flow out of the device through the discharge path formed by the back-to-back Zener diodes, thereby providing ESD protection. Regarding the finished product cost, since the added structure of this invention is located in the transition region, and the split gate of a split-gate field-effect transistor needs to be grounded, there is a natural gap of approximately 20 μm between the split gate and the control gate, which is sufficient to set up multiple independent P-type regions to form back-to-back Zener diodes. (For ease of explanation, the number of P-type regions in the accompanying drawings is shown as 3. However, in practical applications, the number of P-type regions can be increased or decreased according to requirements.) Therefore, the added structure of this invention will not increase the chip area and thus increase the cost of the finished product. In terms of process complexity and compatibility, this invention only requires one ion implantation in the traditional split-gate field-effect transistor process, and does not change the trench morphology and trench wall oxide layer structure that affect the voltage withstand capability and reliability of the split gate structure.

[0023] To illustrate the gain effect of this invention, a conventional split-gate field-effect transistor will be used as a comparison, and its device structure is as follows: Figure 3 As shown, simulation verification was performed using the TCAD Sentaurus numerical simulation tool. The IV curves of the split-gate field-effect transistor with ESD discharge path provided by this invention and the traditional split-gate field-effect transistor under ESD events are shown below. Figure 8As shown, under the same ESD voltage level, this invention clamps the port voltage to a lower level. In contrast, the port voltage of a traditional split-gate field-effect transistor increases sharply when discharging the same current. When the voltage reaches the gate oxide withstand voltage limit, the gate oxide breaks down and the device is damaged.

[0024] Example 2: The process flow of this utility model is as follows: Figure 9 As shown in the diagram, the process flow diagram is as follows: Figures 11 to 22 As shown, the final product structure diagram is as follows. Figure 2 As shown, it includes the following steps: Step 1: Cleaning the N+ substrate; Step 2: An N- epitaxial layer is formed on the N+ substrate; Step 3: Etch trenches on the N-epitaxy layer; Step 4: Fabricate a first dielectric layer with a thickness of 3300 Å within the trench; Step 5: Fabricate a split gate within the dielectric layer. The polysilicon type of the split gate is N-type, with a thickness of 8 kÅ and a sheet resistance of [missing information]. ; Step 6: Etch away the top of the dielectric layer and the top of the split gate within the active region, with an etching depth of 1.3 μm; Step 7: Fabricate a second dielectric layer with a thickness of 0.4 μm in the etched area; Step 8: Fabricate a 600 Å thick gate oxide layer on the trench sidewall using dry oxygen; Step 9: Fabricate a control gate on top of the second dielectric layer and between the gate oxide layers. The polysilicon type is N-type, with a thickness of 8 kÅ and a sheet resistance of [missing information]. ; Step 10: Fabricate a P-type region on the silicon wafer surface using ion implantation. Impurity: B / Energy: 110 keV / Dose: 9.5E 12cm -2 ; Step 11: Create independent P-type regions on the control gate located in the chip transition region using ion implantation. Impurity: B / Energy: 40 keV / Dose: 4E15cm -2 .

[0025] Step 12: Annealing activates the P-type impurities on the silicon wafer surface and pushes the P-type region to a certain junction depth. At the same time, it activates the independent P-type impurities on the control gate to form a back-to-back Zener diode with the N-type polysilicon. Step 13: Create N+ regions on the silicon wafer surface using ion implantation. Impurity: As / Energy: 60 keV / Dosage: 8E 15cm -2 ; Step 14: Fabricate a 5kÅ thick dielectric layer to cover the silicon wafer surface; Step 15: Create contact holes in the surface dielectric layer, and simultaneously fabricate source contact holes, split gate contact holes, and control gate contact holes; Step 16: Ion implantation to create a high-concentration, low-resistivity region within the contact hole: Impurities: BF2 / Energy: 40 KeV / Dosage: 2E15cm -2 , Impurities: B / Energy: 40 keV / Dosage: 1E13cm -2 ; Step 17: Surface metal preparation to form an ohmic contact with the low-resistance region inside the contact hole; Step 18: Metal patterning to form source and gate electrodes; Step 19: Create the passivation layer and etch it to form a wire bonding window; Step 20: Thin the back side of the silicon wafer and sputter the back side ohmic contact metal, then anneal to form the drain ohmic contact; Step 21: Thicken the back metal to form the drain electrode.

[0026] Example 3: according to Figure 9 The process flow of this utility model shown can be appropriately modified to achieve the final product structure as follows: Figure 4 As shown.

[0027] The modifications are as follows: Figure 9 Step 11 of the process flow shown is modified as follows: Independent P-type regions are fabricated on the control gate located in the chip transition region using ion implantation, while field-limiting ring regions are fabricated on adjacent silicon wafer surfaces. Impurity: B / Energy: 40keV / Dose: 4E 15cm -2 .

[0028] Example 4: like Figure 10 As shown, the split-gate field-effect transistor with ESD discharge path of this invention can also be fabricated through the following steps: Step 1: Cleaning the N+ substrate; Step 2: An N- epitaxial layer is formed on the N+ substrate; Step 3: Etch trenches on the N-epitaxy layer; Step 4: Fabricate a first dielectric layer with a thickness of 3300 Å within the trench; Step 5: Fabricate a split gate within the dielectric layer. The polysilicon type of the split gate is N-type, with a thickness of 8 kÅ and a sheet resistance of [missing information]. ; Step 6: Etch away the top of the dielectric layer in the active region and transition region of the trench, to a depth of 1.3 μm; Step 7: Dry oxygen is used to fabricate the second dielectric layer and the gate oxide layer on the trench sidewall. The gate oxide layer is 600 Å thick, and the second oxide layer on the split gate sidewall is approximately 1000 Å thick. Step 8: Etch away the second dielectric layer on the sidewall of the split gate within the transition region; Step 9: Fabricate the control gate, using N-type polysilicon with a thickness of 8 kÅ and sheet resistance. It is connected to the top of the split gate within the transition region; Step 10: Fabricate a P-type region on the silicon wafer surface using ion implantation. Impurity: B / Energy: 110 keV / Dose: 9.5E 12cm -2 ; Step 11: Create independent P-type regions on the control gate located in the chip transition region using ion implantation. Impurity: B / Energy: 40 keV / Dose: 4E15cm -2 ; Step 12: Annealing activates the P-type impurities on the silicon wafer surface and pushes the P-type region to a certain junction depth. At the same time, it activates the independent P-type impurities on the control gate to form a back-to-back Zener diode with the N-type polysilicon. Step 13: Create N+ regions on the silicon wafer surface using ion implantation. Impurity: As / Energy: 60 keV / Dosage: 8E 15cm -2 ; Step 14: Fabricate a 5kÅ thick dielectric layer to cover the silicon wafer surface; Step 15: Create contact holes in the surface dielectric layer, and simultaneously fabricate source contact holes, split gate contact holes, and control gate contact holes; Step 16: Ion implantation to create a high-concentration, low-resistivity region within the contact hole: Impurities: BF2 / Energy: 40 KeV / Dosage: 2E15cm -2 , Impurities: B / Energy: 40 keV / Dosage: 1E13cm -2 ; Step 17: Surface metal preparation to form an ohmic contact with the low-resistance region inside the contact hole; Step 18: Metal patterning to form source and gate electrodes; Step 19: Create the passivation layer and etch it to form a wire bonding window; Step 20: Thin the back side of the silicon wafer and sputter the back side ohmic contact metal, then anneal to form the drain ohmic contact; Step 21: Thicken the back metal to form the drain electrode.

[0029] Example 5: according to Figure 10 The transistor of this invention shown in the diagram has another manufacturing process, which can be appropriately modified to achieve the final product structure as follows: Figure 7As shown.

[0030] The modifications are as follows: Figure 10 Step 11 of the process flow shown is modified as follows: Independent P-type regions are fabricated on the control gate located in the chip transition region using ion implantation, while field-limiting ring regions are fabricated on adjacent silicon wafer surfaces. Impurity: B / Energy: 40keV / Dose: 4E 15cm -2 .

Claims

1. A split-gate field-effect transistor with an ESD discharge path, characterized in that: The system includes a low-resistivity N+ substrate (2), with a drain metal (1) and an epitaxial layer (3) at both ends of the substrate (2). The top of the epitaxial layer (3) has several trenches, the sidewalls of which are covered by a first dielectric layer (4). A split gate (7) and a control gate (6) are disposed within the trenches. The control gate (6) and the split gate (7) are isolated within the active region by a second dielectric layer (5), and short-circuited within the transition region. The short-circuited control gate (6)... The junction is provided with several P-type regions, which are connected by N-type regions. The top of the epitaxial layer (3) is covered by an intermetallic isolation medium (15). The top of the intermetallic isolation medium (15) is provided with a gate metal (13) and a source metal (14). The middle part of the gate metal (13) is provided with a protrusion that extends through the intermetallic isolation medium (15) into the control gate (6). The middle part of the source metal (14) is provided with a protrusion that extends through the intermetallic isolation medium (15) into the split gate (7).

2. A split-gate field-effect transistor with an ESD discharge path according to claim 1, characterized in that: The control grid (6) and the split grid (7) are distributed vertically or horizontally within the trench; When distributed vertically, the control gate (6) is placed above the split gate (7); When distributed in a left-right configuration, the control gate (6) is placed on both sides of the top of the split gate (7).

3. A split-gate field-effect transistor with an ESD discharge path according to claim 2, characterized in that: When the control grid (6) is placed on both sides of the top of the split grid (7), field limit loops are provided on both sides of several P-type regions.

4. A split-gate field-effect transistor with an ESD discharge path according to claim 1, characterized in that: The P-type region is a doping region with the opposite doping type to the control gate (6), and the N-type region is a doping region with the same doping type as the control gate (6).

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