Light-emitting semiconductor device and method for manufacturing the same

Abstract

Light-emitting semiconductor device (100) comprising: a first conductive semiconductor layer (102); an active layer (103) which is arranged on a first region of the first conductive semiconductor layer (102); a second conductive semiconductor layer (104) arranged on top of the active layer (103); a first inner electrode (105a) which is arranged on a second region of the first conductive semiconductor layer (102) separate from the first region; a second internal electrode (105b) which is arranged on at least one region of the second conductive semiconductor layer (104) and is connected to the second conductive semiconductor layer (104); an insulating section (106) which is arranged on a region of the second region, the first and second inner electrodes (105a, 105b), and has an open region such that at least one region of each of the first and second inner electrodes (105a, 105b) is exposed; and a first and a second pad electrode (107a, 107b) arranged on the insulating section (106) and each being connected to a respective first and second inner electrode (105a, 105b) exposed through the opening area, and wherein the first inner electrode (105a) has a plurality of first regions (C) that are separated from each other and touch the first conductive semiconductor layer (102), and a plurality of second regions that connect the plurality of first regions (C) together, and wherein the majority of the first regions (C) and the majority of the second regions have the same thickness in a direction perpendicular to the first conductive semiconductor layer (102).

Description

Technical field

[0001] The present disclosure relates to a light-emitting semiconductor device and a light-emitting device. background

[0002] A light-emitting diode (LED) is a light-emitting semiconductor device capable of emitting light of various colors due to the recombination of electrons and holes at a junction between p-type and n-type semiconductor layers when an electric current is applied. Such a light-emitting semiconductor device offers advantages over a filament-based light-emitting device due to a relatively longer lifespan, lower power consumption, superior start-up characteristics, and other factors. These factors have continuously driven demand for light-emitting semiconductor devices. In particular, much attention has recently been paid to group III nitride semiconductors, which can emit light in the blue short-wavelength range.

[0003] Since the development of LEDs using nitride semiconductors, technological advances have expanded their range of applications. Consequently, many studies have been conducted to determine how nitride semiconductor devices can be used in general lighting devices and electric light sources. Light-emitting nitride devices have been used as components in low-current and portable low-power devices. The application range of light-emitting nitride devices has further expanded to include high-current and high-power devices.

[0004] Accordingly, research has been conducted in the area of ​​improving the light emission efficiency and quality of light-emitting semiconductor devices, and in particular, light-emitting devices with different electrode structures have been developed to improve light emission rates and their reliability.

[0005] DE 10 2008 011 848 A1 relates to an optoelectronic semiconductor body comprising a substantially planar sequence of semiconductor layers with a first and a second main surface, the latter having an active layer suitable for generating electromagnetic radiation. Furthermore, the semiconductor body includes at least one trench dividing the active layer of the semiconductor sequence into at least two electrically isolated active sublayers. A first and second connection layer arranged on a second main surface serves to connect the active sublayers. The first and second connection layers are electrically connected to each other in such a way that the active sublayers form a series circuit.

[0006] US 2012 / 0 032 198 A1 relates to an optoelectronic semiconductor device comprising: a substrate; a semiconductor system with an active layer formed on the substrate; and an electrode structure formed on the semiconductor system, wherein the electrode structure comprises: a bond pad of the first conductivity type; a bond pad of the second conductivity type; an extension electrode of the first conductivity type; and an extension electrode of the second conductivity type, wherein the extension electrode of the first conductivity type and the extension electrode of the second conductivity type form a three-dimensional intersection; wherein the extension electrode of the first conductivity type and the extension electrode of the second conductivity type are located on opposite sides of the active layer.

[0007] US Patent 2010 / 0 155 752 A1 relates to a light-emitting semiconductor device comprising a first-type conductivity semiconductor layer, a first electrode, an insulating layer, and an electrode layer. The first electrode has at least one branch on the first-type conductivity semiconductor layer. The insulating layer is arranged on the first electrode. The electrode layer is arranged on the insulating layer.

[0008] DE 10 2008 062 933 A1 relates to an optoelectronic projection device that generates a predetermined image during operation. The projection device comprises a semiconductor body having an active layer suitable for generating electromagnetic radiation and a radiation emission side. The semiconductor body is an image-generating element of the projection device. For electrical contacting of the semiconductor body, a first contact layer and a second contact layer are arranged on a rear side of the semiconductor body opposite the radiation emission side and are electrically isolated from each other by means of a separating layer.

[0009] DE 10 2009 023 849 A1 relates to an optoelectronic semiconductor body with a front side intended for the emission and / or reception of electromagnetic radiation, a back side opposite the front side intended for mounting on a substrate, and an active semiconductor layer sequence comprising, in the direction from back side to front side, a layer of a first conductivity type, an active layer, and a layer of a second conductivity type in that order. DE 10 2009 023 849 A1 further relates to a semiconductor chip with such a semiconductor body. According to one aspect, the semiconductor layer sequence has at least one recess extending from the back side into the semiconductor layer sequence.According to another aspect, the depression has a first section that extends through the layer of the first conductivity type and the active layer into the layer of the second conductivity type and has a bottom surface in the layer of the second conductivity type. According to yet another aspect, the depression has a second section with an opening, the opening being completely enclosed, in plan view from the rear, by an outer contour of the bottom surface of the first section, and the second section extending from the opening towards the front and running at least within the layer of the second conductivity type. SUMMARY

[0010] One aspect of the present invention relates to a light-emitting semiconductor device with improved current distribution efficiency and a significantly less frequent occurrence of layer delamination defects between an electrode and a semiconductor layer.

[0011] One aspect of the present invention also relates to a light-emitting semiconductor device with a reduced operating voltage and improved light output.

[0012] Further aspects of the present invention also relate to a method for manufacturing a light-emitting semiconductor device and a light-emitting device with improved heat dissipation efficiency and reliability.

[0013] The subject matter of the present disclosure is not limited thereto and includes, even if not expressly mentioned, items and effects derived from embodiments and claims of the present application within the scope of this disclosure.

[0014] A light-emitting semiconductor device according to the invention is defined by claim 1 and a method according to the invention for manufacturing a light-emitting semiconductor device by claim 6. Further developments and advantageous embodiments are the subject of the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and further aspects, properties and other advantages of the present disclosure will become clearer through the following detailed description, which is made in conjunction with the accompanying drawings, in which: Fig. 1 is a schematic top view illustrating a light-emitting semiconductor device according to an embodiment of the present disclosure; Fig. 2 a schematic cross-sectional view along a line AA' from Fig. 1 is illustrating a light-emitting semiconductor device according to an embodiment of the present invention; Fig. 3 a schematic cross-sectional view along a line BB' from Fig. 1 is illustrating a light-emitting semiconductor device according to an embodiment of the present disclosure; The Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14 to Fig. 15 schematic process views are shown, illustrating the steps of a method for manufacturing a light-emitting semiconductor device according to an embodiment of the present disclosure; The Fig. 16, Fig. 17 and Fig. 18 schematic cross-sectional views are shown, illustrating a light-emitting device according to an embodiment of the present disclosure; The Fig. 19, Fig. 20, Fig. 21, Fig. 22 to Fig. 23 schematic views are shown illustrating a light-emitting semiconductor device according to a further embodiment of the present disclosure, and process views illustrating the steps of a method for manufacturing the same; and The Fig. 24 and Fig. 25 schematic process cross-sectional views illustrate the steps of a method for manufacturing a light-emitting semiconductor device according to a further embodiment(s) of the present disclosure. DETAILED DESCRIPTION OF THE EXECUTION FORMS

[0016] The following are detailed descriptions of embodiments of the present disclosure with reference to the accompanying drawings. However, the inventive idea can be embodied in many different forms and should not be considered limited to the embodiments presented herein. Rather, these embodiments are intended to ensure that this disclosure is thorough and complete and fully covers the scope of the inventive idea. In the drawings, the shapes and dimensions of elements may be exaggerated for clarity, and the same reference numerals will generally be used throughout to denote the same or similar elements.

[0017] Fig. 1 is a schematic top view illustrating a light-emitting semiconductor device according to one embodiment of the present disclosure; Fig. 2 is a schematic cross-sectional view along a line AA' from Fig. 1; and Fig. Figure 3 is a schematic cross-sectional view along a line BB'. Fig. 1. Regarding the Fig. 1, Fig. 2 and Fig. 3. A light-emitting semiconductor device 100 can comprise a light-emitting structure arranged on a substrate 101, that is, a light-emitting stack with a first conductive semiconductor layer 102, an active layer 103, and a second conductive semiconductor layer 104, and an electrode structure with a first and a second inner electrode 105a and 105b, and a first and a second pad electrode 107a and 107b. The respective components of the light-emitting semiconductor device 100 will be described below.

[0018] The substrate 101 can be a semiconductor growth substrate and be made of a semiconductor material with insulating or conducting properties, such as sapphire, silicon carbide (SiC), MgAl₂O₄, MgO, LiAlO₂, LiGaO₂, GaN, or the like. The substrate 101 can have properties that allow at least a portion of the light emitted by the active layer 103 to be transmitted through it. Accordingly, the light-emitting semiconductor device 100 can have a flip-chip form in which, when the semiconductor devices are mounted in a circuit, the substrate 101 is oriented upwards. In this case, sapphire with electrical insulating properties is most preferably used as the substrate 101. Sapphire is a crystal with a hexa-rhombo-R3C symmetry and has a lattice constant of 13.001 Å along a C-axis and a lattice constant of 4.758 Å along an A-axis.The sapphire exhibits a C-(0001) plane, an A-(1120) plane, an R-(1102) plane, and the like. In this case, the C-plane is primarily used as a nitride growth substrate, since the C-plane relatively simplifies the growth of a nitride layer and is stable at high temperatures. Meanwhile, as in . Fig. 2 and Fig. Figure 3 illustrates how a plurality of uneven structures can be formed on the surface of substrate 101, namely a semiconductor growth layer, such that the structures increase the semiconductor layer crystallinity and light emission efficiency. However, uneven structures are not necessarily required and in some cases they can be omitted.

[0019] The first and second conductive semiconductor layers 102 and 104 of the light-emitting structure can be semiconductors doped with either n-type or p-type impurities; however, the present disclosure is not limited to this. More generally, the first and second conductive semiconductor layers 102 and 104 can each be a p-type and an n-type semiconductor layer, respectively. The first and second conductive semiconductor layers 102 and 104 can consist of a nitride semiconductor, for example, a material with a composition formula of Al x In y Ga 1-x-yN (0≤X≤1, 0≤Y≤1, 0≤X+Y≤1) can be formed. Furthermore, an AlGaInP-based or an AlGaAs-based semiconductor can also be used. Additionally, the active layer 103, which is arranged between the first and the second conductive semiconductor layers 102 and 104, can have a multi-quantum well (MQW) structure in which quantum well layers and quantum barrier layers are stacked alternately, and in this case of a nitride semiconductor, a GaN / InGaN structure can be used here, for example. Meanwhile, the first and second conductive semiconductor layers 102 and 104 and the active layer 103, which forms the light-emitting structure, can be grown by a prior art method such as metal-organic chemical vapor deposition (MOCVD), hydride gas epitaxy (HVPE), molecular beam epitaxy (MBE) or the like.

[0020] The first inner electrode 105a can be formed on a substrate 101 on which the first conductive semiconductor layer 102, the active layer 103, and the second conductive semiconductor layer 104 have been formed sequentially. The first inner electrode 105a can then be formed by removing the first conductive semiconductor layer 102, the active layer 103, and the second conductive semiconductor layer 104 from a region of the substrate, creating a groove that reaches and connects the first conductive semiconductor layer 102. The first inner electrode 105a can then be formed in the groove on the exposed region of the substrate and can have a shape corresponding to the groove.Additionally, the second inner electrode 105b can be formed on at least one region of the second conductive semiconductor layer 104, different from the region with the first inner electrode 105a formed thereon, and the second inner electrode 105b can be formed such that it connects the second conductive semiconductor layer 104. Alternatively, the first conductive semiconductor layer 102 can be removed in such a way that it forms the groove exposing the first conductive semiconductor layer 102. In such a case, the first inner electrode 105a can contact a highest surface of the first conductive semiconductor layer 102. Meanwhile, if the groove is formed by removing a region of the light-emitting structure, a side face of the groove can be inclined, as shown in [reference]. Fig. Figure 3 illustrates this. However, as shown in Fig. 6 or the same is illustrated, the side surface of the groove is not inclined and the degree of inclination (or non-inclination) can be determined according to a removal method of the first conductive semiconductor layer 102, the active layer 103 and the second conductive semiconductor layer 104.

[0021] The first inner electrode 105a and the second inner electrode 105b can be formed from a conductive material exhibiting resistive properties. The first inner electrode 105a and the second inner electrode 105b can each be formed relative to the first and second conductive semiconductor layers 102 and 104, respectively, and can have a single-layer or multilayer structure. For example, the first and second inner electrodes 105a and 105b can be formed from a material such as silver (Ag), aluminum (Al), nickel (Ni), chromium (Cr), palladium (Pd), copper (Cu), or an alloy thereof, using a coating process, a sputtering process, a plating process, or the like.The first and second inner electrodes 105a and 105b can be formed from a high-reflective material, such that the light-emitting semiconductor device 100 is suitable for use in the form of a flip-chip as described above. However, forming the first and second inner electrodes 105a and 105b with a reflective material is not strictly necessary, and a portion of the first and second inner electrodes 105a and 105b can be formed from a transparent conductive oxide (TCO) or the same, if required.

[0022] In one embodiment, the first inner electrode 105a can have a plurality of contact areas C, each of which has a relatively larger width than other areas of the first inner electrode 105a when viewed from above, as well as in Fig. Figure 1 shows that sufficient contact areas with the first pad electrode 107a are ensured. The contact areas C can be formed such that they penetrate the second conductive semiconductor layer 104 and layer 103 in such a way that the first inner electrode 105a is connected to the first conductive semiconductor layer 102 in the contact areas C. In particular, the majority of contact areas C can be arranged in rows and columns as shown in Figure 1. Fig. Figure 1 shows that the contact areas can be arranged such that a current flow can be uniform within them. Additionally, the majority of contact areas C can be connected to each other by further areas of the first inner electrode 105a (such as the areas shown in dashed lines in Figure 1). Fig. Figure 1 shows areas into which a first inner electrode 105a extends, such as the row of four contact areas C that are passed through the first inner electrode 105a as shown in Figure 1. Fig. (2 shown, are connected). The second inner electrode 105b can be formed in a region separated from and spatially separated from a circumferential region of the contact regions C such that a stress in the circumferential region of the contact regions C can be reduced in order to decrease the frequency of a layer detachment phenomenon of the second inner electrode 105b. Furthermore, if a region connecting the contact regions C is not present, the entirety of contact regions C can be surrounded by the second inner electrode 105b, and in this case a large stress can act on the circumferential region of the contact regions C, thereby increasing the probability that the second inner electrode 105b and the second conductive semiconductor layer 104 will detach.Meanwhile, it is not necessarily required in the embodiment, however, the first inner electrode 105a may have a linear or further area connecting contact areas C in different rows under the plurality of contact areas C, as shown in the dashed lines of the . Fig. Figure 1 illustrates the linear or further region can be found in the vicinity of the light-emitting semiconductor device (as further explained in Figure 1). Fig. 1 is illustrated) are arranged.

[0023] The first inner electrode 105a can be surrounded by an insulating region 106 and electrically isolated from the active layer 103 and the second conductive semiconductor layer 104. Additionally, as shown in Fig. Figure 2 illustrates that the insulating area 106 allows selected areas of the majority of contact regions C (and a corresponding area(s) of the first inner electrode 105a) to be exposed and connected to the first pad electrode 107a, while allowing the remainder of the first inner electrode 105a (i.e., areas connecting the majority of contact regions C) to remain exposed and instead be covered by the insulating area 106. In this way, the majority of contact regions C with a greater width can be connected to the first pad electrode 107a, while other areas of the first inner electrode 105a (for example, areas connecting the majority of regions C and areas with a reduced width) cannot be in direct contact with or connected to the first pad electrode 107a.The presence of the additional areas can ensure that the light-emitting semiconductor device provides a sufficient light-emitting area and reduces light loss due to light absorption by the first inner electrode 105a.

[0024] In particular, to connect the first pad electrodes 107a and the first inner electrode 105a, a method for forming an opening region in the insulating region 106 can be used. However, a limitation may exist in reducing the width of the contact regions C, taking into account a method limit. Since the area of ​​regions of the first inner electrode 105a exposed above the opening regions of the insulating region 106 increases, the area of ​​the first electrode 105a can also increase, thereby reducing the light-emitting area and the light-emitting efficiency of the light-emitting semiconductor device. Consequently, in one embodiment, only the contact regions C connected to the first pad electrodes 107a are formed such that they have a relatively large width in order to improve light-emitting efficiency.Meanwhile, with respect to the regions of the first inner electrode 105a formed by the same process, the contact regions C and further regions of the first inner electrode 105a can have the same thickness, and as described later, the contact regions C can denote a region that fills a first region of the groove, and the further regions can denote a region that fills a second region of the groove. However, this is not necessarily limited to this.

[0025] The insulating region 106 can fill a portion of the groove such that the first inner electrode 105a is not connected to the active layer 103 and the second conductive semiconductor layer 104. Additionally, the insulating region 106 can be formed on and between the first and second inner electrodes 105a and 105b to isolate them from each other. In this case, the insulating region 106 can have an opening to expose at least a portion of each of the first and second inner electrodes 105a and 105b, and the first and second pad electrodes 107a and 107b can be formed on / in the opening. The insulating region 106 can be formed from any material that has electrical insulating properties, such as an electrical insulating material like silicon oxide, silicon nitride, or the like.Additionally, light-reflecting fillers are distributed within the electrical insulation material to form a light-reflecting structure.

[0026] The first and second pad electrodes 107a and 107b can each be connected to the first and second inner electrodes 105a and 105b, respectively, and can serve as external terminals of the light-emitting semiconductor device 100. The first and second pad electrodes 107a and 107b can be formed as a single layer or as two or more layers and can be formed from Ag, Al, Ni, Cr, Pd, Cu, and the like, or an alloy thereof, using a deposition process, a sputtering process, a plating process, or the like. Additionally or alternatively, the first and second pad electrodes 107a and 107b can be formed from or comprise a eutectic metal such as AuSn, SnBi, or the like.In such a case, when mounted in a package or the like, the first and second pad electrodes 107a and 107b can be connected by eutectic bonding, eliminating the need for a solder bump, which is usually required in a flip-chip bonding process. Compared to cases using a solder bump, the mounting method using the eutectic metal allows for better heat dissipation. To achieve higher heat dissipation, the first and second pad electrodes 107a and 107b can be configured to cover a relatively large area. Specifically, the area covered by the first and second pad electrodes 107a and 107b can represent 80% to 95% of the total surface area of ​​the light-emitting semiconductor device.

[0027] The structure of the light-emitting semiconductor device can be understood in more detail by describing a manufacturing process for it, which is described below. Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14 to Fig. Figure 15 are schematic process views illustrating the steps of a method for fabricating a light-emitting semiconductor device according to an embodiment of the present disclosure. In the method for fabricating a light-emitting semiconductor device according to the embodiments, a semiconductor stack can first be formed by growing the first conductive semiconductor layer 102, the active layer 103, and the second conductive semiconductor layer 104 on the substrate 101 using a method such as MOCVD, HVPE, or the same, as described in Fig. 4 can be formed. The substrate 101 can have uneven structures formed on one of its surfaces (for example, a surface that touches a first conductive semiconductor layer 102) as well as in the examples of the Fig. 2 and Fig. 3 shown, or the substrate cannot have uneven structures on any surface of it, as in the example of the Fig. 5 is shown.

[0028] After the semiconductor stack was formed, as in Fig. 5 (a top view) and Fig. As illustrated in Figure 6 (a cross-sectional view), a groove G exposing the first conductive semiconductor layer 102 is formed by removing a region of the first conductive semiconductor layer 102, the active layer 103, and the second conductive semiconductor layer 104. The layers can be removed by etching so that the side faces of the groove G are not inclined, as shown in Figure 6. Fig. Figure 6 is shown. Alternatively, other removal methods can be used that provide a groove with inclined edges, such as those shown in the Fig. 2 and Fig. 3 shown. Meanwhile, as in Fig. Figure 5 illustrates that the layers at an edge region of the light-emitting structure are removed simultaneously or separately from the formation of the groove G to expose an edge region of the first conductive semiconductor layer 102. The exposed edge region of the first conductive semiconductor layer 102 can be used as a parting line during the separation of the light-emitting structure in chip units. However, the formation of the parting line is not necessary or required in this embodiment, and if necessary, further regions exposing the first conductive semiconductor layer 102, other than the groove G, can be formed or omitted.

[0029] In one embodiment, the groove G can be provided as a region for forming the inner electrode 105a and can have a plurality of first regions ① with a relatively large width to expose a large area of ​​the first conductive semiconductor layer 102, and second regions ② that connect at least some of the first regions ① and have a relatively small width. The inner electrode 105a can be formed in the groove G to have a shape corresponding to the groove G. In general, the shape of the respective first regions ① is not limited to being circular when viewed from above, and other shapes, such as a polygonal or oval shape, can be used.

[0030] Just like in Fig. As illustrated in Figure 5, the plurality of first regions ① can be arranged in rows and columns, and the second regions ② can connect first regions ① that are positioned in the same row below the plurality of first regions ①. Additionally, the groove G can further have a third region ③ that connects first regions ① that are positioned in different rows below the plurality of first regions ①. Accordingly, a single groove G can be used to connect all of the first regions ①, and the first internal electrode 105a, with a shape corresponding to the groove G, can be connected in a similar manner.

[0031] Next, as it is in Fig. 7 (a top view) and Fig. As illustrated in Figure 8 (a cross-sectional view), the first inner electrode 105a, which touches and is connected to the first conductive semiconductor layer 102, is formed such that it corresponds to the shape of the groove G. Accordingly, the majority of contact regions C of the first inner electrode 105a can be formed in the majority of first regions ① of the groove G, and regions of the first inner electrode 105a formed in the second region ② and the third region ③ can connect the majority of contact regions C. However, in some examples, as in Fig. Figure 9 illustrates that the first inner electrode 105a is formed from a plurality of electrodes that are separated from one another, such that the first inner electrode 105a is formed only in each of the contact regions C and cannot be formed in the second regions ② and the third region ③. In the case where a first inner electrode 105a is formed only in the contact regions C, this may be disadvantageous compared to the previous case where the first inner electrode 105a is formed in the first regions ①, the second regions ②, and the third region ③; however, light loss due to the first inner electrode 105a can be reduced. Additionally, the separation of the second inner electrode 105b due to the groove G can be permitted, thus reducing the layer detachment phenomenon of the second inner electrode 105b.

[0032] Just like in Fig. 10 (a cross-sectional view) and Fig. As illustrated in Figure 11 (a top view), the second inner electrode 105b is formed on the second conductive semiconductor layer 104, and then the insulating region 106 can be formed to cover the groove G and the first and second inner electrodes 105a and 105b (as shown in Figure 11). Fig. (as shown in Figure 12). The insulating region 106 can be formed such that it covers the entire surface of the light-emitting semiconductor device and can be formed from an insulating material such as silicon oxide, silicon nitride, or the like by using a deposition process, a spin-coating process, or the like. Then, as shown in Fig. 13 (a top view) and the Fig. As illustrated in Figure 14 (a cross-sectional view), an opening region O is formed in the insulating region 106 to expose at least one region of the first and second inner electrodes 105a and 105b. In this case, as described above, the first inner electrode 105a can have exposed regions corresponding to the contact regions C. Then, as shown in Fig. As illustrated in Figure 15, the first and second pad electrodes 107a and 107b are formed to connect the first and second inner electrodes 105a and 105b respectively.

[0033] The light-emitting semiconductor device with the structure described above can be applied to a mounting substrate or the like, in order to be used in a light-emitting device, for example in a backlighting unit of a display device, an indoor / outdoor lighting device, a vehicle headlight or the same.

[0034] In particular, the Fig. 16, Fig. 17 and Fig. 18 schematic cross-sectional views illustrating a light-emitting device according to an embodiment of the present disclosure. The light-emitting device according to the embodiments of the present disclosure can comprise a mounting substrate 108 and a light-emitting semiconductor device mounted thereon, and in this case, the light-emitting semiconductor device can have a substrate such as the one described above with respect to the Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14 to Fig. The mounting substrate 108 can have first and second surface electrodes 109a and 109b and first and second bottom electrodes 111a and 111b, as described in Section 15. As illustrated, the first and second surface electrodes 109a and 109b can be connected to the first and second bottom electrodes 111a and 111b via first and second through-holes 110a and 110b. The illustrated structure of the mounting substrate 108 is provided as an example only and can be used in different forms. Additionally, the mounting substrate 108 can be a circuit substrate 100 such as PCB, MCPCB, MPCB, FPCB, or the like, or a ceramic substrate such as AlN, Al2O3, or the like. Alternatively, the mounting substrate 108 can be in the form of a component frame rather than a substrate.

[0035] The light-emitting semiconductor device can be configured as a flip-chip, as described above. In other words, the first and second pad electrodes 107a and 107b can be arranged in one direction towards the mounting substrate 108. The first and second pad electrodes 107a and 107b can have bonding layers, such as eutectic metal layers, on their surfaces, such that the first and second pad electrodes 107a and 107b can be connected to the first and second surface electrodes 109a and 109b. In situations where the first and second pad electrodes 107a and 107b do not have bonding layers, separate bonding layers such as a eutectic metal layer, conductive epoxy layers or the same can be formed between the first and second pad electrodes 107a and 107b and the first and second surface electrodes 109a and 109b.While not strictly necessary in this embodiment, a wavelength conversion region 112 can be formed or arranged on surfaces of the light-emitting semiconductor device to convert one wavelength of light emitted by the light-emitting semiconductor device into another. For this purpose, the wavelength conversion region 112 can comprise a fluorescent substance, a quantum dot, or the like.

[0036] In a modified example of one in Fig. In the light-emitting device shown in Figure 17, a wavelength conversion region 112' can be formed on the surface of the light-emitting semiconductor device. In particular, the wavelength conversion region 112' can be formed only on one surface of a substrate 101', and a reflection region 113 can be formed on side faces of the light-emitting semiconductor device. In this case, an uneven structure can be formed between the wavelength conversion region 112' and the substrate 101', and such an uneven structure can be applied to any of the embodiments described above. The reflection region 113 can have a structure in which reflection fillers, such as ceramics or metals such as TiO2, SiO2, and the like, are distributed in a transparent resin. Additionally, as in the example of a light-emitting device in Figure 17, a reflection region 113 can be formed on the surface of the light-emitting semiconductor device. Fig. 18. The substrate 101' is removed from the light-emitting semiconductor device, and a surface irregularity can be formed on a first conductive semiconductor layer 102' (for example, a surface opposite the surface with the active layer 103 and the first and second internal electrodes 105a and 105b formed thereon). One or both of the wavelength conversion region and the reflection region described in the preceding embodiments can be located in the light-emitting device of Fig. 18 integrated.

[0037] Regarding the Fig. 19, Fig. 20, Fig. 21, Fig. 22 to Fig. 23 A light-emitting semiconductor device according to further embodiments of the present disclosure and a method for manufacturing the same are provided. First, as described in Fig. As shown in Figure 19, the shape of a groove G' that exposes the first conductive semiconductor layer 102 in this embodiment differs from that of the preceding embodiments. In particular, the groove G' can have a shape in which a plurality of strips are arranged parallel to one another when viewed from above. In this case, the groove G' can have a region formed in a direction perpendicular to the plurality of strips and connecting them, similar to the third region ③ of the preceding embodiments. The plurality of strips can have a substantially uniform width, and the first inner electrode 105a can have a corresponding shape.Accordingly, the first inner electrode 105a cannot have contact areas with a relatively large width and consequently the first electrodes 105a have a uniform width in order to reduce the overall size of the first electrodes 105a in order to enable an increase in the light-emitting area and a reduction in light loss.

[0038] Next, as it is in Fig. As illustrated in Figure 20, the insulating region 106 is formed entirely above the groove G' and the light-emitting structure. Unlike the previous embodiments, in this embodiment the insulating region 106 can be formed before the formation of the first inner electrode 105a. Afterwards, as shown in Figure 20, the insulating region 106 is formed. Fig. As illustrated in Figures 21 (a cross-sectional view) and 24 (a top view), a portion of the insulating region 106 is removed to eliminate the opening region O, such that the first conductive semiconductor layer 102 and the second inner electrode 105b are exposed through the opening regions. Then, as shown in Fig. As illustrated in Figure 23, the first inner electrode 105a, the first pad electrode 107a, and the second pad electrode 107b are formed. The first inner electrode 105a, the first pad electrode 107a, and the second pad electrode 107b can be formed using a single process. Alternatively, the electrodes can be formed using separate processes. In this case, since masks for the respective first inner electrode 105a, the first pad electrode 107a, and the second pad electrode 107b are not required in this embodiment, process efficiency can be increased compared to the previous embodiments. Furthermore, the first inner electrode 105a, the first pad electrode 107a, and the second pad electrode 107b can be formed from the same material or from different materials, as required.

[0039] As in the embodiment, the first inner electrode 105a is formed in the insulating region 106 after the opening region has been formed, such that no surface of the first electrode 105a is covered by the insulating region 106. Accordingly, the first inner electrode 105a and the first pad electrode 107a can contact each other over their entire area, thus simplifying uniform current injection and eliminating the need for the relatively wide contact areas described in the preceding embodiments. As described above, in the case where the first inner electrode 105a is formed first and the opening region is then formed in the insulating region 106, there is a limitation on reducing the width of the first inner electrode 105a near the opening region due to a process boundary. In contrast, in the case of Fig. 19, Fig. 20, Fig. 21, Fig. 22 to Fig. 23, since the opening area in the insulating area 106 is formed before the formation of the first inner electrode 105a in the embodiment, the width of the first inner electrode 105a is not affected and accordingly the first inner electrode 105a can have a relatively small width. In addition, the second inner electrode 105b does not have to surround the entire area of ​​the first electrode 105a in order to reduce the layer detachment phenomenon of the second inner electrode 105b.

[0040] The Fig. 24 and Fig. Figure 25 are schematic process cross-sectional views illustrating the steps of a method for manufacturing a light-emitting semiconductor device according to a further embodiment of the present disclosure. In this embodiment, as described in Fig. As illustrated in Figure 24, the first conductive semiconductor layer 102, the active layer 103, the second conductive semiconductor layer 104, and the second inner electrode 105b are formed successively on the substrate 101. Then, as shown in Figure 24, the first conductive semiconductor layer 102, the active layer 103, the second conductive semiconductor layer 104, and the second inner electrode 105b are formed sequentially on the substrate 101. Fig.As illustrated in Figure 25, a region of each of the first conductive semiconductor layer 102, the active layer 103, the second conductive semiconductor layer 104, and the second inner electrode 105b is removed from a groove G, and it is not necessary to prepare a mask for forming the second inner electrode 105b, thereby improving process efficiency. After forming the groove G, the procedures performed in the preceding embodiments can be used. In other words, forming the first inner electrode in the groove G, forming the insulating region, forming the opening region in the insulating region, and forming the first and second pad electrodes are performed sequentially. Alternatively, forming the insulating region, forming the opening region in the insulating region, forming the first inner electrode, and forming the first and second pad electrodes are performed sequentially.

[0041] As previously explained above, a light-emitting semiconductor device according to embodiments of the disclosure can be provided with an improved current distribution efficiency as well as with a significantly reduced layer detachment error between an electrode and a semiconductor layer.

[0042] Additionally, a light-emitting semiconductor device with a reduced operating voltage and improved light output can be provided.

[0043] Additionally, a light-emitting device with improved heat dissipation efficiency and reliability can be provided.

[0044] The advantageous effects resulting from the present disclosure are not limited thereto, and even if they are expressly mentioned or not expressly mentioned, further objects and effects derived from the embodiment of the present disclosure are conceivable.

Claims

[1] Light-emitting semiconductor device (100) comprising: a first conductive semiconductor layer (102); an active layer (103) which is arranged on a first region of the first conductive semiconductor layer (102); a second conductive semiconductor layer (104) arranged on top of the active layer (103); a first inner electrode (105a) which is arranged on a second region of the first conductive semiconductor layer (102) separate from the first region; a second internal electrode (105b) which is arranged on at least one region of the second conductive semiconductor layer (104) and is connected to the second conductive semiconductor layer (104); an insulating section (106) which is arranged on a region of the second region, the first and second inner electrodes (105a, 105b), and has an open region such that at least one region of each of the first and second inner electrodes (105a, 105b) is exposed; and a first and a second pad electrode (107a, 107b) arranged on the insulating section (106) and each being connected to a respective first and second inner electrode (105a, 105b) exposed through the opening area, and wherein the first inner electrode (105a) has a plurality of first regions (C) that are separated from each other and touch the first conductive semiconductor layer (102), and a plurality of second regions that connect the plurality of first regions (C) together, and wherein the majority of the first regions (C) and the majority of the second regions have the same thickness in a direction perpendicular to the first conductive semiconductor layer (102). [2] Light-emitting semiconductor device (100) according to claim 1, wherein the insulating section (106) exposes at least one region of each of the plurality of first regions (C) forming the first inner electrode (105a). [3] Light-emitting semiconductor device (100) according to claim 1, wherein: Each of the first regions (C) has a width that is wider than the width of each of the second regions, the width being perpendicular to the thickness in a direction. [4] Light-emitting semiconductor device (100) according to claim 1 or 3, wherein the plurality of first regions are arranged in a plurality of rows and a plurality of columns and each of the second regions connects first regions that are arranged in the same row. [5] Light-emitting semiconductor device according to claim 1, wherein the insulating section (106) does not cover a surface of the first inner electrode (105a). [6] Method for manufacturing a light-emitting semiconductor device (100) comprising: Forming a groove (G) in a first conductive semiconductor layer (102), an active layer (103) formed on the first conductive semiconductor layer (102), and a second conductive semiconductor layer (104) formed on the active layer (103) by removing at least one region of the second conductive semiconductor layer (104) and the active layer (103) to expose a first region of the first conductive semiconductor layer (102); Forming a first inner electrode (105a) connected to the first region of the first conductive semiconductor layer (102) by filling a region of the slot (G) with an electrode material; Forming a second inner electrode (105b) connected to the second conductive semiconductor layer (104) on at least one region of the second conductive semiconductor layer (104); Forming an insulating section (106) by filling a residual area of ​​the groove (G) with an insulating material, wherein the insulating section (106) is formed on a region of the second area, the first and second inner electrodes (105a, 105b) respectively, and is formed such that it has an opening area which exposes at least one region of each of the first and second inner electrodes (105a, 105b); and Forming a first and a second pad electrode (107a, 107b) on the insulating section (106) and wherein each is connected to a respective first and second inner electrode (105a, 105b) which are exposed through the opening area, and wherein the groove (G) has a plurality of first regions (C) that are separated from each other and touch the first conductive semiconductor layer, and a plurality of second regions that connect the plurality of first regions (C), and wherein the majority of the first regions (C) and the majority of the second regions have the same thickness in a direction perpendicular to the first conductive semiconductor layer (102). [7] Method according to claim 6, wherein the first inner electrode (105a) is formed such that it has a shape corresponding to a shape of the groove (G). [8] Method according to claim 6, wherein each of the first regions has a width which is wider than the width of each of the second regions, the width being in a direction perpendicular to the thickness.

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