Semiconductor device and method for its manufacture

Abstract

Method for manufacturing a semiconductor device, the method comprising: Forming dummy gate structures (40, 41, 42) for field-effect transistors, hereinafter referred to as FETs, with different gate lengths Lg1, Lg2 in a first region (A) and in a second region (B) to produce a short-channel FET and a long-channel FET; Forming a first insulating layer (70) over the dummy gate structures (40, 41, 42); Removing the dummy gate structures (40, 41, 42) so that gate spaces (81 - 83) are created in the first insulating layer (75); Forming a first conductive layer (90) in the gate spaces (81 - 83), so that smaller gate spaces are created; Filling the reduced gate spaces with a second conductive layer (100) made of a different material than the first conductive layer (90); Deepening the filled first conductive layer (90) and the second conductive layer (100) so that a first gate depression (87, 89) is formed in the first region (A); and Forming a third conductive layer (130) over the first conductive layer (90) and the second conductive layer (100) in the first gate recess (87, 89), Deepening of the third conductive layer (130) so that a second gate depression (91, 92) is formed; and Forming a second insulating layer (140) over the recessed third conductive layer (130) in the second gate recess (91, 92).

Description

TECHNICAL AREA

[0001] The disclosure relates to a method for manufacturing a semiconductor device and in particular a structure and a manufacturing process for a metal gate structure. BACKGROUND

[0002] With the development of nanometer-scale semiconductor technology, driven by the pursuit of higher device density, increased performance, and reduced costs, both manufacturing and design challenges have led to the development of three-dimensional designs such as Fin field-effect transistors (FinFETs) and the use of a metal-gate structure with a material exhibiting a high k-value (dielectric constant). The metal-gate structure is often fabricated using gate replacement technologies.

[0003] US Patent 9,209,273 B1 discloses a method for manufacturing a semiconductor device with a conductive layer above a gate volume layer, wherein the conductive layer protrudes above an underlying conductive layer. US Patent 2013 / 0015532 A1 and US Patent 2009 / 0224338 A1 disclose further manufacturing methods for a semiconductor device.

[0004] US patent 2015 / 0061027A1 discloses a method for manufacturing replacement gate structures for NMOS and PMOS transistors.

[0005] The invention is defined in the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure is best understood from the following detailed description, when read in conjunction with the accompanying figures. It is emphasized that, in accordance with standard industry practice, various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various features may be enlarged or reduced as desired for the sake of clarity. Fig. Figures 1A-15 show an exemplary sequence of a manufacturing process of a semiconductor device according to an embodiment of the present disclosure. Fig. Figures 16-20 show an exemplary sequence of a manufacturing process of a semiconductor device according to another embodiment of the present disclosure. Fig. Figures 21-23 show an exemplary sequence of a manufacturing process of a semiconductor device according to another embodiment of the present disclosure. Fig. Figure 24 shows an exemplary cross-sectional view of a semiconductor device according to another embodiment of the present disclosure. Fig. 1B-24 are cross-sectional views corresponding to line X1-X1 of Fig. 1A. DETAILED DESCRIPTION

[0007] It is clear that the following disclosure provides for many different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below for the sake of simplicity. For example, the dimensions of elements are not limited to the disclosed range or values ​​but may depend on process conditions and / or desired properties of the device. Furthermore, the formation of a first feature above or on top of a second feature in the following description may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, so that the first and second features may not be in direct contact.For the sake of simplicity and clarity, various features can be drawn at different scales.

[0008] Furthermore, spatial terms such as "below," "under," "lower," "above," "upper," and the like can be used here for simple description to convey the relationship of one element or feature to one or more other elements or features depicted in the figures. These spatial terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatial descriptors used here can be interpreted accordingly. Additionally, the term "made of" can mean either "comprising" or "consisting of."

[0009] Fig. Figures 1A-15 show an exemplary sequence of a manufacturing process of a semiconductor device according to an embodiment of the present disclosure. Fig. 1B-15 are cross-sectional views corresponding to line X1-X1 of Fig. 1A. It is clear that additional work steps may be planned before, during and after the processes that are carried out by Fig. Figures 1A-15 are shown, and some of the subsequent steps may be replaced or eliminated for additional embodiments of the method. The sequence of the steps / processes may be variable.

[0010] Fig. Figure 1A shows a top view (plan view) of a semiconductor device structure after dummy gate structures have been formed over a substrate. Fig. 1A and Fig. In 1B, dummy gate structures 40, 41, and 42 are formed over a channel layer, for example, part of a fin structure 20. Each of the dummy gate structures 40, 41 corresponds to a short-channel FET with a gate length Lg1, and the dummy gate structure 42 corresponds to a long-channel FET with a gate length Lg2, where Lg1 < Lg2. In some embodiments, Lg1 is less than about 30 nm. The short-channel FETs are arranged in region A, and the long-channel FET is arranged in region B. Although the dummy gate structures 40, 41, and 42 are in Fig. 1A and Fig. The arrangement is not limited to the fact that 1B are arranged side by side. In some embodiments, the dummy gate structures 40, 41 and 42 are separated from each other by a gap.

[0011] The fin structure 20 is formed over a substrate 10 and extends from an insulating layer 30. To clarify, the dummy gate structures 40, 41, and 42 are formed over the same fin structure 20, but in some embodiments, dummy gate structures 40, 41, and 42 are each formed over different fin structures. Although two fin structures 20 in Fig. As shown in Figure 1A, the number of fin structures per gate structure is not limited to two and can be one, three, or more.

[0012] Substrate 10, for example, is a p-type silicon substrate with an impurity concentration in the range of approximately 1 x 10 15 cm -3 up to about 1 x 10 18 cm 3 In other embodiments, the substrate is an n-type silicon substrate with an impurity concentration in the range of approximately 1 x 10 15 cm -3 up to about 1 x 10 18 cm -3Alternatively, the substrate may comprise another elemental semiconductor, such as germanium; a compound semiconductor containing group IV-IV compound semiconductors, such as SiC and SiGe; group III-V compound semiconductors, such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof. In one embodiment, the substrate is a silicon layer made from an SOI (silicon on insulator) substrate.

[0013] The fin structures 20 can be formed by trench etching of the substrate. After the formation of the fin structures 20, the insulating layer 30 is formed over the fin structures 20. The insulating layer 30 contains one or more layers of insulating materials, such as silicon dioxide, silicon oxynitride, or silicon nitride, formed by LPCVD (low-pressure chemical vapor deposition), plasma CVD, or flowable CVD. The insulating layer can be formed by one or more layers of spin-on glass (SOG), SiO₂, SiON₂, SiOCN₂, and / or fluorine-doped silicate glass (FSG).

[0014] After the formation of the insulating layer 30 over the fin structures 20, a planarization process is performed to remove a portion of the insulating layer 30. This planarization process may include chemical-mechanical polishing (CMP) and / or a back-etching process. The insulating layer 30 is then further removed (depressed) to expose the upper regions of the fin structures 20.

[0015] The dummy gate structures 40, 41, and 42 are then formed over the exposed fin structures 20. The dummy gate structure comprises a dummy gate electrode layer 44 made of polysilicon and a dielectric dummy gate layer 43. Sidewall spacers 48, containing one or more layers of insulating material, are also formed on the sidewalls of the dummy gate electrode layer. The sidewall spacers 48 contain one or more layers of insulating material such as silicon nitride-based material containing SiN, SiON, SiCN, and SiOCN. The film thickness of the sidewall spacers 48 at the base of the sidewall spacers is in the range of about 3 nm to about 15 nm in some embodiments and in the range of about 4 nm to about 8 nm in other embodiments.

[0016] The dummy gate structures further include a mask insulating layer 46, which is used to structure a polysilicon layer within the dummy gate electrode layers. The thickness of the mask insulating layer 46 is in the range of approximately 10 nm to approximately 30 nm in some embodiments and in the range of approximately 15 nm to approximately 20 nm in other embodiments.

[0017] As in Fig. As shown in Figure 2, source / drain regions 60 are formed after the formation of the dummy gate structures. In the present disclosure, a source and a drain are used interchangeably, and the term source / drain refers to either a source or a drain. In some embodiments, the fin structure 20, which is not covered by the dummy gate structures, is recessed below the upper surface of the insulating layer 30. The source / drain regions 60 are then formed above the recessed fin structure by an epitaxial growth process. The source / drain regions 60 may contain a strain material to exert a load on the channel region. Additional source / drain regions 60 may be formed on the left side of the dummy gate structure 40 and / or on the right side of the dummy gate structure 42.

[0018] As in Fig. As shown in Figure 3, a first etch stop layer (ESL) 70 and a first insulating intermediate layer (ILD) 75 are formed over the dummy gate structures and the source / drain regions. The first ESL 70 contains one or more layers of insulating material, such as silicon nitride-based materials containing SiN, SiCN, and SiOCN. The thickness of the first ESL 70 ranges from approximately 3 nm to approximately 10 nm in some embodiments. The first ILD layer 75 contains one or more layers of insulating material, such as silicon oxide-based materials like silicon dioxide (SiO2) and SiON.

[0019] After the planarization step on the first ILD layer 75 and the ESL 70, the dummy gate structures are removed, resulting in gate spaces 81, 82, and 83, as shown in Fig. 4 is shown. As in Fig. As shown in Figure 4, the gate sidewall spacers 48 remain in the gate spaces.

[0020] Then, as in Fig. As shown in Figure 5, a dielectric gate layer 85 is formed. The dielectric gate layer 85 contains one or more layers of dielectric material, such as a high k-number metal oxide. Examples of metal oxides used for high k-number dielectrics include oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and / or mixtures thereof. In some other embodiments, an interface layer (not shown), consisting, for example, of silicon oxide, is formed over the fin structure (channel region) prior to the formation of the dielectric gate layer 85. A cover layer of a suitable dielectric material is formed over the gate spaces and the first ILD layer 75 by CVD, PVD, ALD, or other suitable film-forming processes.

[0021] Furthermore, a working function setting (WFA) layer 90 for a p-channel FET is formed in the gate regions 81, 82, and 83. A cover layer of a suitable conductive material is formed over the gate regions and the first ILD layer 75. The WFA layer 90 contains one or more layers of conductive material. Examples of the WFA layer 90 for a p-channel FET include Ti, TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co. In one embodiment, TiN is used for a p-channel FET. Examples of the WFA layer 90 for an n-channel FET include TiN, TaN, TaAlC, TiC, TiAl, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC. In one embodiment, TaAlC, TiAl, or Al is used for an n-channel FET. The thickness of the WFA layer 90 is in some embodiments in a range of about 3 nm to about 10 nm.The WFA layer can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) including sputtering, atomic layer deposition (ALD), or other suitable methods. As shown in . Fig. As shown in Figure 5, the WFA layer is formed conformally in the gate rooms.

[0022] As in Fig. As shown in section 6, a first metal material is then applied 100 above the structure of Fig. 5. The first metal material comprises one or more layers of metal material, such as Al, Co, Cu, W, Ti, Ta, TiN, TiAl, TiAlC, TiAlN, TaN, NiSi, CoSi, or other conductive materials. In one embodiment, W, Co, or Al is used. The first metal material is formed by CVD, PVD, ALD, electroplating, or other suitable processes. The first metal material 100 consists of a different material than the WFA layer 90.

[0023] Then, as in Fig. As shown in Figure 7, a planarization step is performed to remove the top portion of the deposited first metal material 100. Following the planarization step, the first conductive layer 100A for a metal gate electrode of a short-channel FET and the first conductive layer 100B for a metal gate electrode of a long-channel FET are formed in each of the gate regions. The short-channel FETs in region A also contain a dielectric gate layer 85A and a WFA layer 90A, and the long-channel FET in region B also contains a dielectric gate layer 85B and a WFA layer 90B. The planarization step may include a chemical-mechanical polishing (CMP) and / or a re-etching process.

[0024] Subsequently, a protective layer 110 is applied over the structure of Fig. 7 is formed and a mask structure 115 is formed such that it covers area B for the long-channel FET, as shown in Fig. Figure 8 is shown. The protective layer 110 contains one or more layers of insulating material, such as SiN. The mask structure 115 is a photoresist structure in some embodiments.

[0025] By using the mask structure 115 as an etching mask, the protective layer 110 is structured to open an area above area A. Then, using the structured protective layer 110 as an etching mask, the upper part of the first conductive layer 100A, the dielectric gate layer 85A, the WFA layer 90A, the sidewall spacer 48, the first ESL 70, and the first ILD layer 75 are recessed, as shown in Fig. 9A is shown. In some embodiments, the mask structure 115 remains on the protective layer 110. In other embodiments, the upper part of the first conductive layer 100A, the dielectric gate layer 85A, the WFA layer 90A, the sidewall spacer 48, the first ESL 70, and the first ILD layer 75 is not substantially recessed, as shown in Fig. 9B is shown.

[0026] After etching the depression of area A, the first conductive layers 100A and the WFA layers 90A are recessed (back-etched) to form gate depressions 87 and 89, as shown in Fig. Figure 10 illustrates this. Because the materials for the first conductive layers 100A and the WFA layer 90A are different, the extent of etching (depth) of the first conductive layers 100A and the WFA layer 90A differs. For example, if the first conductive layers 100A are made of W and the WFA layer 90A is made of TiN or an aluminum-containing material (TiAl, TaAlC, or Al), the WFA layer 90A will be etched more than the first conductive layer 100A. As a result, the first conductive layer 100A protrudes from the WFA layer 90A, as shown in Figure 10. Fig. Figure 10 is shown. The extent H1 of the projection is in some embodiments in the range of approximately 10 nm to approximately 50 nm. The dielectric gate layers 85A are also etched (deepened) by an additional etching step. In other embodiments, the dielectric gate layers 85A are not etched (deepened).

[0027] As in Fig. As shown in 11, a cover layer made of a second metal material 120 is then conformally applied over the structure of Fig. 10. Subsequently, a third metal material layer 130 is formed over the second metal material layer 120, as shown in Fig. Figure 12 shows the third metal material layer 130, which contains one or more of Al, Co, Cu, W, Ti, Ta, TiN, TiAl, TiAlC, TiAlN, TaN, NiSi, Co, Si, or other conductive materials. In one embodiment, W, Co, or Al is used. In this embodiment, the third metal material layer 130 consists of the same material as the first conductive layer 100. The second conductive layer 120 serves as an adhesive layer for the third conductive layer 130 and contains one or more layers of TiN, Ti, or TaN. The second and third metal materials are formed by CVD, PVD, ALD, electroplating, or other suitable processes.

[0028] Subsequently, a re-etching step is performed on the third conductive layer 130. This re-etching step forms the third conductive layers 130A in the gate recesses 87 and 89, and removes the third conductive layer formed over area B, as shown in Fig. Figure 13 shows that in the etching step the second metal material 120 is also removed, thereby forming second conductive layers 120A.

[0029] As in Fig. As shown in Figure 14, the mask layer 110 is removed, and then another etching step is performed to remove the third conductive layers 130A in the first region A, forming first gate depressions 91, 92 and the first conductive layer 100B in the second region B, thus forming a second gate depression 93. In the etching step, the dielectric gate layer 85B and the WFA layer 90B in the second region B are also depressions. In some embodiments, the dielectric gate layer 85B is not etched (depressions).

[0030] As in Fig. As shown in Figure 14, the first conductive layer 100B protrudes from the WFA layer 90B by an amount of H4, because the materials for the first conductive layer 100B and the WFA layer 90B are different, and the extent of the etching (the depth) of the first conductive layer 100B and the WFA layer 90B is different. In some embodiments, H4 is less than approximately ± 50 nm.

[0031] In some embodiments, the height of the recessed third conductive layer 100A, measured from the substrate, differs from the height of the recessed first conductive layer 100B by an amount H2. In some embodiments, H2 is less than approximately ± 60 nm. In some embodiments, the height of the recessed first conductive layer 100B is greater than the height of the recessed third conductive layer 130A, and in other embodiments, the height of the recessed first conductive layer 100B is less than the height of the recessed third conductive layer 130A.

[0032] Similarly, the height of WFA layer 90A in region A, measured from the substrate, differs from the height of WFA layer 90B in region B by an amount H3. In some embodiments, H3 is less than approximately ± 60 nm. In some embodiments, the height of WFA layer 90A is greater than the height of WFA layer 90B, and in other embodiments, the height of WFA layer 90A is less than the height of WFA layer 90B.

[0033] As in Fig. As shown in Figure 15, the gate recesses 91, 92, and 93 are filled with a second insulating layer 140. A cover layer of a second insulating material is formed, and a planarization step, such as a CMP process, is performed. The second insulating layer 140 contains one or more layers of insulating material, such as a silicon nitride-based material containing SiN, SiCN, or SiOCN.

[0034] As in Fig. As shown in Figure 15, short-channel FETs 101 and 102 comprise a first dielectric gate layer 85A and a first gate electrode. The first gate electrode includes a WFA layer 90A (located beneath the conductive layer) in contact with the first dielectric gate layer 85A and a first conductive layer 100A (conductive bulk layer). The first gate electrode further comprises a third conductive layer 130A (upper conductive layer) and a second conductive layer 120A (conductive intermediate layer) arranged between the first conductive layer 100A and the third conductive layer 130A. The first conductive layer 100A projects from the WFA layer 90A. An insulating layer 140 is provided in contact with the third conductive layer 130A.

[0035] A long-channel FET 103 comprises a second dielectric layer 85B and a second gate electrode. The second gate electrode contains a WFA layer 90B in contact with the second dielectric gate layer 85B and a first conductive layer 100B. An insulating layer 140 is provided in contact with an upper surface of the WFA layer 90B and the first conductive layer 100B.

[0036] Fig. Figures 16-20 show exemplary steps of the manufacturing process of a semiconductor device according to another embodiment of the present disclosure. Fig. 16-20 are cross-sectional views corresponding to line X1-X1 of Fig. 1A. It is clear that additional work steps may be planned before, during and after processes that are caused by Fig. Figures 16-20 illustrate the process, and some of the subsequent steps described may be replaced or eliminated for additional embodiments of the method. The sequence of steps / processes may be modified. Furthermore, the same or similar configuration, structure, materials, steps, or processes of the preceding embodiments may be used in this embodiment, and a detailed explanation may be omitted.

[0037] In this embodiment, a short-channel n-type FET, a long-channel n-type FET and a short-channel p-type FET are formed in region A, region B and region C respectively.

[0038] After the dummy gate structures were similar to those in Fig. Once 4 were removed, a dielectric gate layer 85 is formed in the gate space 81', 82' and 83', as shown in Fig. Figure 16 is shown. Furthermore, a first working function setting (WFA) layer 92 for a p-channel FET is formed in gate space 82' in region C, as shown in Fig. 16 is shown.

[0039] A cover layer of a suitable conductive material is formed over the gate spaces and the first ILD layer 75, and a structuring operation, including lithography and etching, is performed to form the first WFA layer 92 for a p-channel FET in the gate space 82' (and the surrounding area). The first WFA layer 92 contains one or more layers of conductive material. Examples of the first WFA layer 92 for the p-channel FET include Ti, TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co. In one embodiment, Ti is used. The thickness of the first WFA layer 92 is in the range of about 3 nm to about 10 nm in some embodiments. The first WFA layer 92 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) including sputtering, atomic layer deposition (ALD), or other suitable methods. As described in Fig. As shown in Figure 16, the first WFA layer 92 is formed conformally in gate space 82'.

[0040] As in Fig. As shown in Figure 17, a second WFA layer 94 is formed for n-channel FETs in the gate regions 81' and 83'. A cover layer of a suitable conductive material is formed over the gate regions and the first WFA layer 92. The second WFA layer 94 contains one or more layers of conductive material. Examples of the second WFA layer 94 for an n-channel FET include TiN, TaN, TaAlC, TiC, TiAl, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC. In one embodiment, Ti is used. The thickness of the second WFA layer 94 is in the range of about 3 nm to about 10 nm in some embodiments. The second WFA layer 94 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) including sputtering, atomic layer deposition (ALD), or other suitable methods. As shown in Fig. As shown in Figure 17, the second WFA layer 94 is formed conformally in gate spaces 81' and 83'. It is noted that the order in which the first WFA layer 92 and the second WFA layer 94 are formed can be changed. The second WFA layer 94 is made of a different material than the first WFA layer 92.

[0041] Then, similar to what is done in Fig. 6, a first metal material 100 above the structure of Fig. 17 formed, as in Fig. Figure 18 shows that the first metal material 100 consists of a different material than at least one of the first WFA layer 92 and the second WFA layer 94.

[0042] As in Fig. As shown in Figure 19, a planarization step is then performed to remove the upper part of the deposited first metal material 100. After the planarization step, the first conductive layer 100A for a metal gate electrode of a short-channel n-type FET, the first conductive layer 100B for a metal gate electrode of a long-channel n-type FET, and the first conductive layer 100C for a metal gate electrode of a short-channel p-type FET are formed in each of the gate regions. The short-channel n-type FET in area A also contains a dielectric gate layer 85A and a second WFA layer 94A, the long-channel FET in area B also contains a dielectric gate layer 85B and a second WFA layer 94B, and the short-channel p-type FET in area C contains a dielectric gate layer 85C and a second WFA layer 94C.

[0043] Once the structure of Fig. Once 19 is formed, similar work steps are carried out as in Fig. 8-15 carried out and the structure of Fig. 20 will be received.

[0044] As in Fig. Figure 20 shows a short-channel n-type FET 104 comprising a first dielectric gate layer 85A and a first gate electrode. The first gate electrode includes a second WFA layer 94A in contact with the first dielectric gate layer 85A and a first conductive layer 100A. Furthermore, the first gate electrode includes a third conductive layer 130A and a second conductive layer 120A, which is arranged between the first conductive layer 100A and the third conductive layer 130A. The first conductive layer 100A projects from the second conductive layer 120A. An insulating layer 140 is provided in contact with the third conductive layer 130A.

[0045] A long-channel n-type FET 106 comprises a second dielectric gate layer 85B and a second gate electrode. The second gate electrode contains a second WFA layer 94B in contact with the second dielectric gate layer 85B and a first conductive layer 100B. An insulating layer 140 is in contact with an upper surface of the second WFA layer 94B and the first conductive layer 100B.

[0046] A p-type short-channel FET 105 comprises a third dielectric gate layer 85C and a third gate electrode. The third gate electrode includes a first WFA layer 92C in contact with the first dielectric gate layer 85C, a second WFA layer 94C, and a first conductive layer. Furthermore, the third gate electrode includes a third conductive layer and a second conductive layer, arranged between the first and second conductive layers and the third conductive layer, similar to the n-type short-channel FET. The first conductive layer protrudes from the second conductive layer. An insulating layer 140 is provided in contact with the third conductive layer.

[0047] Fig. Figures 21-23 show exemplary processes of a manufacturing process of a semiconductor device according to another embodiment of the present disclosure. Fig. 21-23 are cross-sectional views corresponding to a line X1-X1 of Fig. 1A. It is clear that additional work steps may be planned before, during and after the processes that are carried out by Fig. Figures 21-23 illustrate the process, and some of the subsequent steps may be replaced or eliminated for additional embodiments of the method. The sequence of steps / processes may be variable. Furthermore, the same or similar configuration, structure, materials, steps, or processes of the preceding embodiments may be used in this embodiment, and a detailed explanation may be omitted.

[0048] Once the structure of Fig. 10 is formed, as in Fig. As shown in Figure 21, third conductive layers 130A are formed over the first conductive layers 100A and the WFA layers 90A. In one embodiment, the third conductive layers 130A' contain tungsten (W), formed, for example, by ALD using WCl5 and H2 as source gases. Generally, tungsten is selectively formed over a conductive surface by ALD and is not formed over an insulating surface. Therefore, the third conductive layers 130A', consisting of W, can only be formed over the first conductive layers 100A and the WFA layers 90A. By adjusting the deposition time, the third conductive layers 130' can be formed with a required thickness.

[0049] Once the structure of Fig. Once 21 is formed, similar work steps are carried out as in Fig. 14 carried out and the structure of Fig. 22 will be retained.

[0050] Furthermore, similar work steps are used as in Fig. 15 carried out and the structure of Fig. 23 will be retained.

[0051] As in Fig. As shown in Figure 23, short-channel FETs 101' and 102' contain a first dielectric gate layer 85A and a first gate electrode. The first gate electrode contains a WFA layer 90A in contact with the first dielectric gate layer 85A and a first conductive layer 100A. Furthermore, the first gate electrode contains a third conductive layer 130A'. The first conductive layer 100A projects from the WFA layer 90A. An insulating layer 140 is provided in contact with the third conductive layer 130A'. If the first conductive layer 100A and the third conductive layer 130A' are made of different materials, an interface can be observed between these two layers. If the first conductive layer 100A and the third conductive layer 130A' are made of the same material (e.g.,W) no interface can be observed between these two layers and the combination of the first conductive layer 100A and the third conductive layer 130A' forms a T-shape in cross-section.

[0052] A long-channel FET 103' comprises a second dielectric gate layer 85B and a second gate electrode. The second gate electrode comprises a second WFA layer 90B in contact with the second dielectric gate layer 85B and a first conductive layer 100B. An insulating layer 140 is provided in contact with an upper surface of the WFA layer 90B and the first conductive layer 100B.

[0053] Fig. Figure 24 shows an exemplary cross-sectional view of a semiconductor device according to another embodiment of the present disclosure. The same or similar configuration, structure, materials, work steps or processes of the preceding embodiments may be used in this embodiment, and the detailed explanation may be omitted.

[0054] In this embodiment, the first conductive layer is not positioned above the top surface of the WFA layer 90A'. During the formation of the WFA layer 90A', a gate space is completely filled with material for the WFA layer, and a back-etching step is performed to etch back the material deposited for the WFA layer. Then, a second conductive layer 120A is formed, followed by the formation of a third conductive layer 130A".

[0055] In area B, the thickness of the WFA layer 90B' is greater than in the case of the preceding embodiments, for example Fig. 15.

[0056] In some embodiments, the height of the third conductive layer 130A" from a substrate differs from the height of the first conductive layer 100B. In other embodiments, the height of the third conductive layer 130A" is essentially the same as the height of the first conductive layer 100B, with the height difference being within about 2 nm.

[0057] It is clear that the in Fig. 15, Fig. 20, Fig. 23 and Fig.The devices shown in Figure 24 undergo further CMOS processes to form various features, such as connecting conductive layers, dielectric layers, passivation layers, etc. The preceding embodiment describes the fabrication steps for a FinFET. However, the above fabrication process can also be applied to other types of FETs, such as a planar FET.

[0058] The various embodiments or examples described here offer several advantages over the prior art. For example, since the third conductive layer, which contains a metal material with a lower resistance than the WFA layers, is deposited in the present disclosure, the gate resistance can be reduced. Furthermore, since the metal-gate structure for a short-channel FET and the metal-gate structure for a long-channel FET are formed separately, the extent of WFA etching can be controlled for the short-channel FET and the long-channel FET.

[0059] It is clear that not all advantages have necessarily been discussed here, no particular advantage is required for all embodiments or examples, and other embodiments or examples may offer other advantages.

[0060] According to one aspect of the present disclosure, in a method for fabricating a semiconductor device, a dummy gate structure is formed over a substrate. A first insulating layer is formed over the dummy gate structure. The dummy gate structure is removed, so that a gate space is formed in the first insulating layer. A first conductive layer is formed in the gate space, so that a reduced gate space is formed. The reduced gate space is filled with a second conductive layer, which consists of a different material than the first conductive layer. The filled first conductive layer and the second conductive layer are recessed, so that a first gate recess is formed. A third conductive layer is formed over the first conductive layer and the second conductive layer in the first gate recess.After the first conductive layer and the second conductive layer have been deepened, the second conductive layer protrudes from the first conductive layer.

[0061] According to another aspect of the present disclosure, in a method for fabricating a semiconductor device, a first dummy gate structure for a first field-effect transistor (FET) with a gate length Lg1 is formed in a first region, and a second dummy gate structure for a second FET with a gate length Lg2 is formed in a second region. Lg2 is larger than Lg1. A first insulating layer is formed over the first and second dummy gate structures. The first and second dummy gate structures are removed, so that a first gate space and a second gate space, respectively, are formed in the insulating layer. A first conductive layer is formed in the first gate space, creating a first reduced gate space, and a second conductive layer is formed in the first gate space, creating a second reduced gate space.The first reduced-size gate space is filled with a first second conductive layer made of a different material than the first first conductive layer, and the second reduced-size gate space is filled with a second second conductive layer made of a different material than the second first conductive layer. The second region is covered with a masking layer. The filled first first conductive layer and the first second conductive layer are recessed to form a first gate recess, while the second region remains covered with the masking layer. A third conductive layer is formed over the first first conductive layer and the first second conductive layer in the first gate recess, while the second region remains covered with the masking layer. After the formation of the third conductive layer, the masking layer is removed.The third conductive layer in the first region and the second first conductive layer and the second second conductive layer in the second region are deepened.

[0062] According to another aspect of the present disclosure, a semiconductor device comprises a first field-effect transistor (FET) containing a first dielectric layer and a first gate electrode. The first gate electrode comprises a first lower conductive layer, a first upper conductive layer, and a conductive intermediate layer arranged between the first lower conductive layer and the first upper conductive layer. The first lower conductive layer comprises a first underlying conductive layer in contact with the first dielectric gate layer and a first conductive bulk layer. The first conductive bulk layer projects from the first underlying conductive layer.

[0063] Previously, features of several embodiments were presented so that those skilled in the field could better understand the aspects of the present disclosure. Those skilled in the field should appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages as the embodiments presented herein. Those skilled in the field should also recognize that such equivalent designs do not deviate from the nature and scope of the present disclosure and that they can make various changes, substitutions, and modifications without deviating from the nature and scope of the present disclosure.

Claims

[1] Method for manufacturing a semiconductor device, the method comprising: Forming dummy gate structures (40, 41, 42) for field-effect transistors, hereinafter referred to as FETs, with different gate lengths Lg1, Lg2 in a first region (A) and in a second region (B) to produce a short-channel FET and a long-channel FET; Forming a first insulating layer (70) over the dummy gate structures (40, 41, 42); Removing the dummy gate structures (40, 41, 42) so that gate spaces (81 - 83) are created in the first insulating layer (75); Forming a first conductive layer (90) in the gate spaces (81 - 83), so that smaller gate spaces are created; Filling the reduced gate spaces with a second conductive layer (100) made of a different material than the first conductive layer (90); Deepening the filled first conductive layer (90) and the second conductive layer (100) so that a first gate depression (87, 89) is formed in the first region (A); and Forming a third conductive layer (130) over the first conductive layer (90) and the second conductive layer (100) in the first gate recess (87, 89), Deepening of the third conductive layer (130) so that a second gate depression (91, 92) is formed; and Forming a second insulating layer (140) over the recessed third conductive layer (130) in the second gate recess (91, 92). [2] The method of claim 1, further comprising forming a fourth conductive layer (120) over the second conductive layer (100) prior to forming the third conductive layer (130). [3] Method according to claim 1 or 2, wherein after deepening the filled first conductive layer (90) and the second conductive layer (100) the second conductive layer (100) protrudes from the first conductive layer (90). [4] Method according to any of the preceding claims, wherein the material of the second conductive layer (100) is the same as a material of the third conductive layer (130). [5] Method according to any of the preceding claims, wherein the material of the second conductive layer (100) contains at least one of W, Co, Ti, Al and Cu. [6] Method according to any of the preceding claims, wherein the material of the first conductive layer (90) contains at least one of TiN, Al, TaAlC and TiAl. [7] Method according to claim 4 and one of the preceding claims, wherein the material of the fourth conductive layer (120) contains at least one of TiN, TaN and Ti. [8] Method for manufacturing a semiconductor device, the method comprising: Forming a first dummy gate structure (40, 41) for a first field-effect transistor with a gate length Lg1 in a first region (A) and a second dummy gate structure (42) for a second field-effect transistor with a gate length Lg2 in a second region (B), where Lg2 is greater than Lg1; Forming a first insulating layer (70) over the first and second dummy gate structures (40 - 42); Removing the first and second dummy gate structures (40 - 42) so that a first gate space (81, 82) and a second gate space (83) are created in the first insulating layer (70); Forming a first conductive layer (90A) in the first gate space (81, 82) so that a first reduced gate space is created, and a second conductive layer (90B) in the second gate space (83) so that a second reduced gate space is created; Filling the first reduced-size gate space with a first second conductive layer (100A) made of a different material than the first first conductive layer (90A), and the second reduced-size gate space with a second second conductive layer (100B) made of a different material than the second first conductive layer (90B); Covering the second region (B) with a layer of mask (110); Deepening the filled first conductive layer (90A) and the first second conductive layer (100A) so that a first gate depression (87, 89) is formed, while the second region (B) is covered with the mask layer (110); Forming a third conductive layer (130) over the first conductive layer (90A) and the first second conductive layer (100A) in the first gate recess (87, 89), while the second region (B) is covered with the mask layer (110); after forming the third conductive layer (130), removing the mask layer (110); and Deepening the third conductive layer (130) in the first region (A) and the second first conductive layer (90B) and the second second conductive layer (100B) in the second region (B). [9] Method according to claim 8, wherein after deepening the filled first conductive layer (90A) and the first second conductive layer (100A) the first second conductive layer (100A) protrudes from the first conductive layer (90A). [10] Method according to claim 8 or 9, wherein after deepening the third conductive layer (130) in the first region (A) and the second first conductive layer (90B) and the second second conductive layer (100B) in the second region (B) the second second conductive layer (100B) protrudes from the second first conductive layer (90B). [11] Method according to claim 8 or 9, wherein after deepening the third conductive layer (130) in the first region (A) and the second first conductive layer (90B) and the second second conductive layer (100B) in the second region (B) the height of the deepened third conductive layer (130) from a substrate (10) differs from the height of the deepened second second conductive layer (100B) from the substrate (10). [12] Method according to any one of claims 8 to 11, further comprising forming a fourth conductive layer (120) over the first second conductive layer (100A) prior to forming the third conductive layer (130). [13] Method according to any one of claims 8 to 12, further comprising, after deepening the third conductive layer (130) in the first region (A) and the second first conductive layer (90B) and the second second conductive layer (100B) in the second region (B), forming a second insulating layer (140) over the deepened third conductive layer (130) and the deepened second second conductive layer (100B) and the second first conductive layer (90B). [14] Method according to any one of claims 8 to 13, wherein the material of the first second conductive layer (100A) is the same as a material of the third conductive layer (130). [15] Method according to any one of claims 8 to 14, wherein the material of the first and second conductive layer (100A, 100B) contains at least one of W, Co, Ti, Al and Cu. [16] Method according to any one of claims 8 to 14, wherein the material of the first and second first conductive layer (90A, 90B) contains at least one of TiN, Al, TaAlC and TiAl. [17] Method according to claim 12 and one of claims 8 to 16, wherein the material of the fourth conductive layer (140) contains at least one of TiN, TaN and Ti. [18] Semiconductor device comprising: a first FET (101, 102) comprising a first dielectric gate layer (85A) and a first gate electrode, wherein the first FET has a first gate length Lg1; a second FET (103) comprising a second dielectric gate layer (85B) and a second gate electrode, wherein the second FET has a second gate length Lg2 greater than Lg1 and the first FET is a short-channel FET and the second FET is a long-channel FET; wherein: the first gate electrode includes: a first underlying conductive layer (90A) in contact with the first dielectric gate layer (85A); a first conductive volume layer (100A) above the first underlying conductive layer (90A); a first upper conductive layer (130A) above the volume layer (100A) and a conductive intermediate layer (120A) between the first lower conductive layer (90A) and the first upper conductive layer (130A); and wherein the first conductive volume layer (100A) projects from the first lower conductive layer (90A); furthermore the second gate electrode contains a second underlying conductive layer (90B) in contact with the second dielectric gate layer (85B) and a second conductive volume layer (100B); and an insulating layer (140) is provided in contact with an upper surface of the second underlying layer (90B) and the second conductive volume layer (100B). [19] Semiconductor device according to claim 18, wherein the height of the first upper conductive layer (130A) of a substrate differs from the height of the second conductive volume layer (100B) of the substrate.

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