Method for producing a layered structure

Abstract

Method (100) for manufacturing an electronic device, wherein the method comprises: Formation of at least one electronic component in a substrate (102); Forming a contact point in electrical contact with the at least one electronic component (104); wherein the formation of the contact point comprises (106): Forming a first layer over the substrate; Planarizing the first layer to form a planarized surface of the first layer, wherein the planarized surface has a roughness of less than 10 µm; and Forming a second layer over the planarized surface, the second layer having a lower porosity than the first layer.

Description

[0001] Various embodiments generally relate to a device and a method that processes a substrate. background

[0002] In general, semiconductor materials in semiconductor technology can be processed on or in a substrate (also called a wafer or support) to manufacture, for example, integrated circuits (also called chips). During the processing of the semiconductor material, certain processes can be applied, such as forming one or more layers on the substrate, structuring the one or more layers, or contacting the chips. Generally, a porous copper layer offers advantageous mechanical properties, for example, in the field of thick power metallization.

[0003] In contrast to a dense layer (bulk copper), a porous copper layer on silicon can exert less mechanical and / or thermal stress and therefore offers the possibility of producing a thick copper layer on a wafer and a chip without causing wafer or chip bending, delamination of the wafer or chip and / or cracks in the wafer or chip.

[0004] Conventionally, the properties of a porous copper layer are adjusted by changing manufacturing parameters such as the starting material (particle size or additives) or the process parameters (deposition parameters, furnace parameters, annealing parameters). This adjustment is severely limited to the range of manufacturing parameters and therefore quite restricted. Furthermore, this adjustment fails when sealing the pores, requires additional effort, and is highly sensitive to the copper particle-containing paste used, which reduces the scope for adjustment to other paste compositions.

[0005] Alternatively, two layers can be formed by printing different copper particle-containing pastes or a metal precursor paste on top of each other. This process is only capable of adjusting the spatial porosity of the porous copper layer, fails to seal the pores, requires additional effort, and is sensitive to the combination of copper particle-containing pastes used.

[0006] Alternatively, the porous copper layer can be coated with a metal by electrochemical or electroless chemical deposition. This can result in the incorporation of the electrolytes used, increasing the risk of impurities or contamination, or other consequences such as reduced reliability or damage to the device.

[0007] DE 10 2014 102 242 A1 describes a coating process in which a porous metal layer is deposited on a substrate, in which the porous metal layer is structured, and in which the porous metal layer is coated with a coating material.

[0008] DE 10 2016 101 564 A1 describes a method for producing a porous metallization layer, wherein a second sublayer of the porous metallization layer is formed over a first sublayer of the porous metallization layer, wherein the second sublayer has a lower degree of porosity than the first sublayer.

[0009] US 2015 / 0069638 A1 describes a bonding layer with a first sublayer and a second sublayer, wherein the first and second sublayers have different porosities. DE 102006047928 A1 describes a method for producing porous layers, wherein a suspension can be additively applied and dried repeatedly. US 2015 / 0047696 A1 describes a structure with a first barrier layer over a substrate and a second barrier layer over the first barrier layer, wherein the second barrier layer has a higher porosity than the first barrier layer.

[0010] A method for manufacturing an electronic device may comprise: forming at least one electronic component in a substrate; forming a contact point in electrical contact with the at least one electronic component. Forming the contact point comprises: forming a first layer over the substrate; planarizing the first layer to form a planarized surface, wherein the planarized surface has a roughness of less than approximately 10 µm; and forming a second layer over the planarized surface. The second layer has a lower porosity than the first layer.

[0011] In the drawings, identical reference numbers generally refer to identical parts throughout the various views. The drawings are not necessarily to scale; the emphasis has instead been placed on illustrating the principles of the invention. The following description details various embodiments of the invention with reference to the following drawings: The Fig. Figures 1A to 1D show a device according to different embodiments in a method according to different embodiments in a schematic cross-sectional view or side view; the Fig. Figures 2A to 2C show a device according to different embodiments in a processing stage of a method according to different embodiments in a schematic cross-sectional view or side view; the Fig. Figures 3A to 3D show, respectively, a device according to different embodiments in a processing stage of a method according to different embodiments in a schematic cross-sectional view or side view; the Fig. 4A and Fig. 4B show accordingly a device according to different embodiments in a processing stage of a method according to different embodiments in a schematic cross-sectional view or side view; the Fig. 5A and Fig. Figure 5B shows a schematic representation according to different embodiments; the Fig. 6A and Fig. Figure 6B shows a schematic representation according to different embodiments; the Fig. Figures 7A to 7C show a device according to different embodiments in a processing stage of a method according to different embodiments in a schematic cross-sectional view or side view; the Fig. Figures 8A to 8C show, respectively, a device according to different embodiments in a processing stage of a method according to different embodiments in a schematic cross-sectional view or side view; Fig. Figure 9 shows a process according to different embodiments in a flowchart; the Fig. 10A and Fig. Figure 10B shows a process according to different embodiments in a flowchart; the Fig. 11A and Fig. Figure 11B shows a device according to various embodiments in a processing stage of a method according to various embodiments in a schematic cross-sectional view or side view; the Fig. 12A and Fig. Figure 12B shows a device according to various embodiments in a processing stage of a method according to various embodiments in a schematic cross-sectional view or side view; the Fig. 13A and Fig. Figure 13B shows a device according to various embodiments in a processing stage of a method according to various embodiments in a schematic cross-sectional view or side view; and the Fig. 14A and Fig. Figure 14B shows a device according to various embodiments in a processing stage of a method according to various embodiments in a schematic cross-sectional view or side view.

[0012] The following detailed description refers to the accompanying drawings, which illustrate specific details and embodiments in which the invention can be practiced.

[0013] The word "exemplary" is used here to mean "as an example, case, or illustration." Any embodiment or design described here as "exemplary" is not necessarily to be interpreted as preferred or advantageous over other embodiments or designs.

[0014] The word "over," when used with regard to a deposited material formed "over" a side or surface, may be used here to mean that the deposited material can be formed "directly on," e.g., in direct contact with, said side or surface. The word "over," when used with regard to a deposited material formed "over" a side or surface, may also be used here to mean that the deposited material can be formed "indirectly on" said side or surface with one or more additional layers arranged between said side or surface and the deposited material.

[0015] The term “lateral,” when used with respect to the “lateral” extent of a structure (or substrate, wafer, or support), or “lateral” beside it, may be used herein to mean an extent or positional relationship along a face of a substrate, wafer, or support. This means that a face of a substrate (e.g., a face of a support or a face of a wafer) may serve as a reference point commonly referred to as the principal processing surface of the substrate (or the principal processing surface of the support or wafer). Furthermore, the term “width,” when used with respect to the “width” of a structure (or structural element), may be used herein to mean the lateral extent of a structure.Furthermore, the term “height,” used herein with respect to the height of a structure (or structural element), may be used to mean the extent of a structure along a direction perpendicular to the surface of a substrate (e.g., perpendicular to the main processing surface of a substrate). The term “thickness,” used herein with respect to the “thickness” of a layer, may be used to mean the spatial extent of the layer perpendicular to the surface of the support (material) on which the layer is deposited. If the surface of the support is parallel to the surface of the substrate (e.g., the main processing surface), the “thickness” of the layer deposited on the support may be the same as the height of the layer. Furthermore, a “vertical” structure may be defined as a structure that extends in a direction perpendicular to the lateral direction (e.g.,perpendicular to the main processing surface of a substrate), and a “vertical” extension can be defined as an extension along a direction perpendicular to the lateral direction (e.g., an extension perpendicular to the main processing surface of a substrate).

[0016] According to various embodiments, a substrate (also referred to as a support or wafer) can comprise or be formed from semiconductor materials of various types, including, for example, a Group IV semiconductor (e.g., silicon or germanium), a compound semiconductor such as a Group III-V compound semiconductor (e.g., gallium arsenide), or other types including Group III semiconductors, Group V semiconductors, or polymers. In one embodiment, the substrate is made of silicon (doped or undoped); in an alternative embodiment, the substrate is a silicon-on-insulator (SOI) wafer. Alternatively, any other suitable semiconductor material can be used for the substrate, such as semiconductor composites like gallium phosphide (GaP), indium phosphide (InP), or any suitable ternary or quaternary semiconductor composite such as indium gallium arsenide (InGaAs).

[0017] The substrate can be processed to form one or more semiconductor chips, at least one of which are located in and above the substrate. A semiconductor chip can have an active chip region. The active chip region can be located in a section of the substrate and can include one or more semiconductor circuit elements (also called electronic components) such as a transistor, resistor, capacitor, diode, or the like. The one or more semiconductor circuit elements can be configured to perform computational or storage operations. Alternatively or additionally, the one or more semiconductor circuit elements can be configured to perform switching or rectification operations, for example, in power electronics.

[0018] A semiconductor chip can be separated from the substrate by removing material from a kerf region of the substrate (also called singulation or cutting of the semiconductor region). Material removal from the kerf region of the substrate can be achieved, for example, by scoring and snapping, splitting, sawing, or mechanical sawing (e.g., using a cut-off saw). After singulation, the semiconductor chip can be electrically contacted and, for example, encapsulated in a chip carrier (also called a chip package) using mold materials. This package is then suitable for use in electronic devices. For example, the semiconductor chip can be bonded to a chip carrier using wires, and the chip carrier can be soldered onto a printed circuit board.

[0019] According to various embodiments, a metal may contain or be composed of one element from the following group of elements (in other words, a metal may contain or be composed of at least one of these): aluminum (Al), copper (Cu), nickel (Ni), magnesium (Mg), chromium (Cr), iron (Fe), zinc (Zn), tin (Sn), gold (Au), silver (Ag), iridium (Ir), platinum (Pt), titanium (Ti), and palladium (Pd). Alternatively or additionally, a metal may contain or be composed of a metal alloy including one or more elements from this group. For example, a metal alloy may contain an intermetallic compound, such as an intermetallic compound of gold and aluminum, an intermetallic compound of copper and aluminum, an intermetallic compound of copper and zinc (e.g., "brass"), or an intermetallic compound of copper and tin (e.g., "bronze").According to various embodiments, an electrically conductive material, such as a metal, can be electrically conductive, e.g., with an electrical conductivity greater than approximately 10. 4 S / m, e.g. larger than approximately 10 6 S / m.

[0020] A layered array can include a first layer and a second layer. The formation of the second layer can differ from that of the first layer. For example, the first layer can be printed and the second layer can be sputtered. At least one of the first layer and one of the second layer can be made of or composed of an electrically conductive material, such as a metal.

[0021] To illustrate, the layered arrangement can combine the material properties (e.g., physical, mechanical, and / or chemical properties) of the first and second layers. For example, the first layer can reduce stress transferred to the substrate interface (e.g., of a chip). The second layer can provide the mechanical properties (e.g., hardness, electrical conductivity, corrosion resistance, bondability, etc.) for bonding to a package. For instance, the first layer can act as a stress absorber. The second layer can serve as a protective layer and / or contact template. The material properties of the layered arrangement can be adjusted by changing the thickness of at least one of the second and first layers, such as by altering the ratio of their thicknesses.The protective layer may have a metallic hard coating or be formed from one.

[0022] According to various embodiments, it has been realized that due to the rough topography of a porous layer produced in this way (also referred to as the first layer), it can be difficult to seal the pores of the porous layer or to achieve planar filling of the pores. To illustrate, an electric field used to deposit further material into the porous layer may be inhomogeneous due to the rough topography and may exhibit maxima at the protruding sections of the rough topography, which increases the attraction of the (e.g., sputtered) material towards these protruding sections. Therefore, peak-like growth may dominate the growth process of the second layer.

[0023] The electric field can provide the basis for generating a plasma, for example, for sputtering or plasma-enhanced chemical vapor deposition. In other words, the formation of the second layer can involve the use of a plasma.

[0024] The topography of the first layer can be planarized to reduce its roughness. For example, a planarized first layer can provide a homogeneous electric field distribution, resulting in a spatially homogeneous material distribution when sputtering is used to form the second layer. The second layer can be formed from a gaseous material, for example, by at least one of the following processes: chemical vapor deposition (CVD) and physical vapor deposition (PVD, also known as evaporation), such as sputtering.

[0025] According to various embodiments, the planarization of the first layer can include or be formed from at least one of the following: machining, machine polishing, electrochemical polishing, and chemical-mechanical polishing.

[0026] According to various embodiments, a layer arrangement and a method for forming the layer arrangement can be provided. The method can include: providing a first layer; planarizing the first layer; and forming a second layer over the planarized first layer. Optionally, the first layer can be formed over a layer stack comprising at least one nucleation layer and one barrier layer. Optionally, the first layer can be formed by at least one of paste printing, plasma dust deposition, electrochemical deposition, and a combination thereof.

[0027] The density of the second layer can be greater than that of the first layer. Alternatively or additionally, the second layer can be non-porous or composed of a non-porous layer. For example, the layer structure can provide a hybrid layer that combines the advantages of both a porous and a non-porous layer. Optionally, the first layer can have or be composed of at least two sublayers that differ from each other in at least one pore property, chemical composition, and thickness.

[0028] According to various embodiments, the use of the method can be revealed by analyzing at least one aspect of the layer structure and the layer-to-layer interface, e.g., by at least one of scanning electron microscopy (SEM), focused ion beam ablation, and focused ion beam microscopy. Alternatively or additionally, at least one of the following can be analyzed: the grain boundaries at the layer interface (e.g., by electron backscatter diffraction), the presence of electrolyte (e.g., by energy-dispersive X-ray spectroscopy), and the topographic roughness of the final layers (which can reveal the use of sputtering).

[0029] The Fig. Figures 1A to 1D illustrate a device according to different embodiments in a processing stage of a method according to different embodiments in a schematic cross-sectional view or side view.

[0030] The device 100a can hold a substrate 102 as shown in Fig. 1A shows the substrate 102 can be a semiconductor material, such as silicon, or be formed from it.

[0031] Furthermore, the device 100b can have a first layer 104, which is formed in and above the substrate 102. The first layer 104 can have a surface region 104s located away from the substrate 102. The surface region 104s can define a surface 104t formed by the first layer 104 on one side of the first layer 104 facing the substrate 102.

[0032] The first layer 104 can be formed from a paste containing solid particles and a polymer binder, such as an organic binder. The paste can be applied over the substrate 102 by pressure deposition, such as stencil printing, screen printing, or inkjet printing.

[0033] The solid particles can consist of or be composed of an electrically conductive material, such as a metal like copper. The solid particles can also consist of or be composed of a solid substance.

[0034] The particles may be at least one of the following: nanoparticles, in other words particles with a size (e.g. a diameter) smaller than approximately 100 nm; mesoparticles, in other words particles with a size in the range of approximately 100 nm to approximately 1 µm; and macroparticles, in other words particles with a size larger than approximately 1 µm.

[0035] The paste can be arranged over the substrate 102 and annealed to remove the polymer components of the paste, such as the organic binder (e.g., an organic liquid). Removing the polymer components allows the volume of the first layer 104 to decrease. When the particles contact each other, the decrease in volume may plateau until the first layer 104 reaches a final volume. The remaining polymer components between the particles can be removed, leaving cavities that are filled with a gaseous material.

[0036] Alternatively or additionally, the first layer 104 can be formed by arranging particles over the substrate 102 using a plasma (also known as plasma dust deposition). The plasma can physically activate the particles in such a way that they react with each other through contact. Optionally, the particles can be annealed.

[0037] The annealing process can involve heating the first layer 104 to a sintering temperature in the range of approximately 30% to approximately 70% of the melting temperature of the particles.

[0038] The sintering temperature can be, for example, greater than approximately 200 °C, e.g., greater than approximately 250 °C, e.g., greater than approximately 300 °C, e.g., greater than approximately 350 °C, e.g., greater than approximately 400 °C, e.g., greater than approximately 500 °C, and less than the melting point of the particles (in other words, less than the melting point of a material within the particles), e.g., less than approximately 800 °C, e.g., less than approximately 700 °C, e.g., less than approximately 600 °C. During annealing, the particles can be sintered. In other words, the particles can be bonded together without melting to their liquefaction point. The contact area between the particles can increase during annealing.

[0039] The first layer 104, such as the surface region 104s, may have or be formed from a pore network of partially interconnected pores 304t (also referred to as porous structure 702) (see Fig. 3A). At least one pore (one or more

[0040] The pores of the first layer 104 can be opened at the surface 104t formed by the first layer 104, which can define a roughness of the first layer 104, e.g., in the range of the particle size. In other words, at least one pore can define an opening that extends into the first layer 104.

[0041] The roughness (e.g., square) of the first layer 104 (e.g., of the area 104t formed by the first layer 104) can be greater than the roughness of the substrate 102 (e.g., of an area of ​​the substrate covered by the first layer 104), such as approximately twice, approximately four times, approximately ten times, or more.

[0042] The roughness (e.g., a square roughness) of the first layer 104 before planarizing (in other words, the roughness of the surface 104t formed) can be in the range of approximately 0.1 µm to approximately 50 µm, e.g., in the range of approximately 1 µm to approximately 10 µm, e.g., in the range of approximately 1 µm to approximately 5 µm.

[0043] The device 100c can have a first layer 104 with a planarized surface 104p. The planarized surface 104p can be formed by removing the surface region 104s from the first layer 104, e.g., by at least one of: machining, machine polishing, electrochemical polishing, and chemical-mechanical polishing. This thins the first layer 104.

[0044] The thickness 114t of the surface region 104s can be in a range of approximately 0.1 µm to approximately 10 µm, e.g., in the range of approximately 1 µm to approximately 10 µm, or in the range of approximately 1 µm to approximately 5 µm. Alternatively or additionally, the thickness 114t of the surface region 104s can be greater than the roughness of the first layer 104.

[0045] During planarization, the roughness (e.g., quadratic roughness) of the first layer 104 can be reduced. The roughness (e.g., quadratic roughness) of the first layer 104 after planarization (in other words, the roughness of the planarized surface 104p) can be less than approximately 10 µm, e.g., less than approximately 5 µm, e.g., less than approximately 2 µm, e.g., less than approximately 1 µm.

[0046] The device 100d can have a second layer 106. The second layer 106 can be formed over the planarized surface 104p. The second layer 106 can be formed using a plasma, e.g., by physical vapor deposition (PVD), or by sputtering.

[0047] At least one of the first layer 104 (e.g., the particles) and the second layer 106 can comprise or be formed from at least one of the following material classes: a semiconductor and a metal. For example, the first layer 104 can comprise or be formed from at least one metal layer, such as a porous metal layer, e.g., a porous copper layer. Alternatively or additionally, the first layer 104 can comprise or be formed from a semiconductor layer, such as a porous semiconductor layer. Alternatively, at least one of the substrate 102 and the first layer 104 can also comprise or be formed from another material class (e.g., including a porous material), such as a ceramic, a glass, a metal oxide, a metal nitride, a metal carbide, or a dielectric.

[0048] In one embodiment, the first layer 104 and the second layer 106 can differ in their chemical composition, such as the material from which they are formed. For example, the second layer 106 can be of a different material class (e.g., a metal) than the first layer 104.

[0049] Alternatively, the first layer 104 and the second layer can be identical in at least one material class and chemical composition, such as in one material, like a metal. For example, both the first layer 104 and the second layer 106 can contain or be composed of at least one of the following metals: aluminum, copper, nickel, magnesium, chromium, iron, zinc, tin, gold, silver, iridium, platinum, palladium, and titanium.

[0050] Optionally, the substrate 102 can have at least one further layer 102i, which is formed, for example, between the semiconductor material and the first layer 104. The at least one further layer 102i can provide an area of ​​the substrate 102. The at least one further layer 102i can have or be formed from at least one barrier layer, a passivation layer, a rewiring layer, and an adhesion layer. The barrier layer can have or be formed from at least one of titanium and tungsten if, for example, the substrate 102 or the first layer 104 has a semiconductor (e.g., silicon). The barrier layer can provide a diffusion length in the barrier layer of less than at least one of the area of ​​the substrate 102 and the first layer 104.The adhesive layer can be configured to provide greater adhesion between two surfaces between which the adhesive layer is formed than between the two surfaces in contact with each other. The passivation layer can provide less chemical reactivity than the surface on which the passivation layer is formed. A rewiring layer can be made of or composed of an electrically conductive material and can be structured to provide multiple electrically conductive paths that, for example, connect electronic components of the device 100d.

[0051] According to various embodiments, the substrate 102 (e.g., an area of ​​the substrate), such as the at least one further layer 102i, can comprise at least one of a metal, a semiconductor (also referred to as a semiconductor material); for example, an oxide comprising at least one of the metal or the semiconductor (corresponding to semiconductor oxide or metal oxide), e.g., silicon oxide; a nitride comprising at least one of the metal or the semiconductor (corresponding to semiconductor nitride or metal nitride), e.g., silicon nitride; and a dielectric comprising at least one of the metal or the semiconductor (corresponding to semiconductor dielectric or metal dielectric).

[0052] According to various embodiments, the second layer 106 can be formed by at least one of the following: physical vapor deposition; pressure deposition; and chemical vapor deposition. The second layer can be formed using a fluid-free process, such as an electrolyte-free process. The physical vapor deposition can include or be formed from at least one of sputtering, thermal evaporation, and reactive sputtering. The pressure deposition can include or be formed from stencil printing, screen printing, or inkjet printing. The chemical vapor deposition can include plasma enrichment.

[0053] At least one of the first layer 104 and the second layer 106 can comprise or be formed from at least one of the following materials: a metal, a ceramic, a glass, a metal oxide, a metal nitride, a metal carbide, a dielectric, and a semiconductor. The first layer 104 and the second layer 106 can, for example, comprise or be formed from at least one of the same metal, the same ceramic, the same glass, the same metal oxide, the same metal nitride, the same metal carbide, the same dielectric, the same semiconductor, and the same chemical composition.

[0054] A porosity of the first layer 104 can be greater than a porosity of the second layer 106. For example, the porosity of the first layer 104 can range from approximately 20% to approximately 80%, e.g., from approximately 20% to approximately 70%, e.g., from approximately 20% to approximately 60%, e.g., from approximately 20% to approximately 35%, or e.g., from approximately 35% to approximately 60%. A porosity of at least one of the second layer 106 and the substrate 102 can be less than approximately 20%, e.g., less than approximately 10%, e.g., less than approximately 5%, e.g., approximately 0% (essentially zero).

[0055] The Fig. Figures 2A to 2C illustrate a device according to different embodiments in a processing stage of a method according to different embodiments in a schematic cross-sectional view or side view.

[0056] The device 200a can process a substrate 102 as shown in Fig. 2A shows, for example, that it is similar to device 100a.

[0057] Furthermore, the device 100b can have a first layer 104, which is formed in and above the substrate 102. The first layer 104 can project from an exposed surface 102s of the substrate 102.

[0058] The device 200c can have a first layer 104 with a planarized surface 104p. The planarized surface 104p can be formed by removing the surface region 104s from the first layer 104, e.g., by at least one of: machining, machine polishing, electrochemical polishing, and chemical-mechanical polishing. This thins the first layer 104.

[0059] Optionally, the device 200c can have a second layer 106 above the planarized surface 104p analogous to the device 100d.

[0060] Optionally, a contact point 1708, 1706 can be formed, which has the first layer 104 and optionally the second layer 106, or is formed from it.

[0061] Fig. 3A illustrates a device 300a according to various embodiments in a processing stage of a method according to various embodiments in a schematic cross-sectional view or side view.

[0062] The first layer 104, such as at least one of the planarized surface 104p, the surface formed 104t, and the surface region 104s, may have or be formed from at least one pore 314t (in other words, one or more pores 314t, e.g., several pores 314t) extending into the substrate 102. The at least one pore 314t may have or be formed from an opening 304o in the surface 104t, 104p.

[0063] According to various embodiments, the size (also referred to as pore size, e.g., a spatially averaged size) of the at least one pore 314t can be in the range of approximately 0.1 µm to approximately 10 µm, e.g., in the range of approximately 0.5 µm to approximately 10 µm, e.g., in the range of approximately 1 µm to approximately 5 µm. The size can include at least one extension from the at least one pore 314t parallel to a surface 104t, 104p of the first layer 104 (e.g., the planarized surface 104p or as a formed surface 104t), e.g., a transverse extension of the opening 304o; and an extension from the at least one pore 314t into the substrate. B. define perpendicular to surface 104t, 104p. A pore can be opened through the opening 304o (also referred to as an open-pore surface). In other words, at least one pore can be opened through surface 104t, 104p.

[0064] The at least one pore 314t can also be referred to as porous structure 702. At least two pores of the porous structure 702 can be connected to each other, for example, by being adjacent to one another and / or by other pores.

[0065] A pore property can exhibit at least one of the following: spatial pore density, spatial pore size, and porosity. In other words, the pore property can exhibit spatial pore density, spatial pore size, and / or porosity.

[0066] A pore density can denote a number of pores per area or per volume. A spatial pore size can denote a spatial pore volume or a spatial pore expansion (extent), such as at least one perpendicular and parallel to the surface 104t, 104p, such as a pore diameter. At least one of the spatial pore size and pore density can refer to a spatially averaged value, which is averaged, for example, over at least one of: the planarized surface 104p, the surface 104t formed as shown, and the surface region 104s. According to various embodiments, the pore network 702 can have or be formed from at least one of the following: micropores, in other words, pores 304t with an extent (e.g., at least one perpendicular or parallel to the surface 104t, 104p, such as a diameter) less than approximately 2 nm; Mesopores, in other words pores 304t with an extent (e.g.at least one of perpendicular or parallel to the surface 104t, 104p, such as a diameter) in the range of approximately 2 nm to approximately 50 nm; and macropores, in other words pores 304t with an extent (e.g. at least one of perpendicular and parallel to the surface 104t, 104p, such as a diameter) greater than approximately 50 nm.

[0067] Porosity (also referred to as void fraction) can refer to the pore space within a region and can be understood as a proportion of the volume of voids over the total volume or area of ​​the region. A porous layer, region, or material can have a porosity in the range of 0.1 to 0.9, or in other words, as a percentage in the range of 10% to 90%. The porosity can refer to a spatially averaged value, for example, averaged over a region such as at least one of the planarized surface 104p, the as-formed surface 104t, the surface region 104s, and the first layer 104. According to various embodiments, the pore density and the spatial pore size can define the porosity. Alternatively or additionally, the pore density and the spatial pore size can define the pore density.

[0068] The Fig. Figures 3B to 3D illustrate a device according to various embodiments in a processing stage of a method according to various embodiments in a schematic cross-sectional view or side view.

[0069] According to various embodiments, the device 300b can have a first layer 104 and a second layer 106. The second layer 106 can partially seal (in other words, partially or completely seal) the pores of the first layer 104. The device 300b can further have a mask structure 108 (e.g., a structured polymer layer, which includes or is formed from a resin) over the second layer 106.

[0070] The thickness 108d of the mask structure 108 can range from approximately 1 µm to approximately 10 µm, e.g., greater than approximately 2 µm, e.g., greater than approximately 4 µm, e.g., greater than approximately 6 µm, e.g., greater than approximately 8 µm. The mask structure 108 can be structured, e.g., using photolithography. The mask structure 108 can be structured according to a predetermined pattern (e.g., a mask pattern). After structuring the mask structure 108, at least one processing region 316 of the device 300b can be exposed (in other words, revealed) through an opening in the mask structure 108. Alternatively, the mask structure 108 can be formed from a base material according to a predetermined pattern (e.g., a mask pattern). The predetermined pattern can be configured to leave at least one processing region 316 exposed.

[0071] The device 300c can have at least one of the first layer 104 and the second layer 106 structured. The at least one processing region 316 exposed by the mask structure 108 (exposed region) can be processed, for example, by wet etching (e.g., using a liquid etchant) or dry etching (e.g., using at least one gaseous etchant, one plasma etchant, and one ionic etchant). For example, at least one trench 902 and one recess 902 can be formed in at least one of the first layer 104 and the second layer 106.

[0072] The device 300d can have at least two sections 1706, 1708a, 1708b of at least one of the first layer 104 and the second layer 106, which are separated from each other. After structuring, the mask structure 108 can be removed, e.g., using a solvent (e.g., a basic fluid, an organic fluid, or a water-based fluid).

[0073] The at least two sections 1706, 1708a, 1708b can each provide a contact point. Alternatively, only one section 1708a can be formed, e.g. similar to the device 200c.

[0074] Fig. 4A illustrates a device 400a according to various embodiments in a processing stage of a method according to various embodiments in a schematic cross-sectional view or side view.

[0075] According to various embodiments, the device 400a can have a porous structure 702 which is formed in the first layer 104, e.g., over a semiconductor region 704 of the substrate 102.

[0076] The porous structure 702 can be formed by a printing process, such as a paste printing process (e.g., a stencil printing process and / or a screen printing process), e.g., metal paste printing (e.g., using a paste containing metal particles). Alternatively or additionally, the porous structure 702 can be formed by plasma dust deposition (e.g., using a complex plasma).

[0077] According to various embodiments, the porosity of the porous structure 702 can be in the range of approximately 20% to approximately 80%, e.g., in the range of approximately 20% to approximately 70%, e.g., in the range of approximately 20% to approximately 50%, e.g., in the range of approximately 20% to approximately 30%, or in the range of approximately 30% to approximately 40%.

[0078] According to various embodiments, the pore size (e.g., a spatially averaged pore size) of the porous structure 702 can be in the range of approximately 0.1 µm to approximately 10 µm, e.g., in the range of approximately 0.5 µm to approximately 10 µm, or e.g., in the range of approximately 1 µm to approximately 5 µm. The pore size can be defined by at least one extension of the pores of the porous structure 702 parallel to the surface 104t, 104p; and an extension of the pores of the porous structure 702 into the substrate, e.g., perpendicular to the surface 104t as formed.

[0079] According to various embodiments, the roughness (e.g., a square roughness) of the porous structure 702 can be in the range of approximately 0.1 µm to approximately 10 µm, e.g., in the range of approximately 1 µm to approximately 10 µm, e.g., in the range of approximately 1 µm to approximately 5 µm.

[0080] According to various embodiments, the porous structure 702 can have or be formed from multiple pores. According to various embodiments, at least one pore of the porous structure 702 (e.g., multiple pores) can be opened on the surface 104t formed as described.

[0081] The porous structure 702 can be formed from particles (also referred to as granules). The particles can be sintered together, for example, in such a way that their grains contact each other in a certain area. During sintering, the particles can be compacted and bonded together, forming a solid mass of a skeletal structure (also referred to as a matrix).

[0082] According to various embodiments, the first layer 104 can have or be formed from a porous copper layer, which is printed, for example, from a paste onto the substrate 102 by stencil printing or screen printing. The paste can have or be formed from copper particles and an organic binder. The printed first layer 104 can be dried at a drying temperature (e.g., for 1 hour at approximately 60 °C or higher) to remove at least some of the organic components of the paste and then sintered at a sintering temperature, such as 400 °C. The drying step can be used to remove a liquid component of the paste before sintering. The drying temperature can be less than 30% of the melting temperature of the particles, such as less than the evaporation temperature of the liquid component (e.g., an organic solvent).

[0083] Heating the first layer 104 can involve a heating time of approximately 15 minutes and a holding time at sintering temperature ranging from approximately 15 minutes to approximately 90 minutes. During the holding time at sintering temperature, the organic components of the paste can be removed. The first layer 104 can be heated in a chemically reducing atmosphere, e.g., including a chemical reducing gas (e.g., at least formic acid or carbon monoxide) in an inert carrier gas (e.g., at least nitrogen or argon). Alternatively, the first metallization 304 can be formed using another solid particle deposition process, such as plasma dust deposition.

[0084] The porosity of the first layer 104 can range from approximately 40% to approximately 50%. A thickness of 404t (see also Fig. 1B) of the first layer 104 (e.g. before planarizing) can be in the range of approximately 10 µm to approximately 10 µm, e.g. in the range of approximately 10 µm to approximately 50 µm, e.g. in the range of approximately 10 µm to approximately 30 µm, e.g. in the range of approximately 10 µm to approximately 20 µm or in the range of approximately 20 µm to approximately 30 µm.

[0085] Fig. Figure 4B illustrates a device 400b according to various embodiments in a processing stage of a method according to various embodiments in a schematic cross-sectional view or side view.

[0086] The device 400b can have a second layer 106 formed over the planarized surface 104p of the first layer 104. The planarized surface 104p can be formed by machining.

[0087] The thickness of the first layer 104 can be increased to a thickness of 414 during planarizing (see also Fig. 1D) e.g., by at least the value of the roughness of the first layer 104, e.g., by a range of approximately 0.1 µm to approximately 10 µm, e.g., in the range of approximately 1 µm to approximately 10 µm, e.g., in the range of approximately 1 µm to approximately 5 µm. Planarizing the first layer 104 can increase layer thickness uniformity, e.g., at the wafer level. Alternatively or additionally, the final thickness of the first layer 104 can be adjusted more precisely.

[0088] Optionally, an oxide layer of the first layer 104 can be removed from the planarized surface 104p (before the second layer 106 is formed), such as by etching (e.g. by wet or plasma etching).

[0089] The second layer 106 can be formed using sputtering. The second layer 106 can have a surface (e.g., as produced) with a lower roughness than at least one of the surface 104t formed as and the surface region 104s.

[0090] The second layer 106 can be formed without pores. For example, the second layer 106 can be formed in bulk.

[0091] The thickness 106t of the second layer 106 can be greater than half the spatial pore size of the first layer 104, for example, greater than twice the spatial pore size of the first layer 104. This can result in the pores of the first layer 104 being sealed. Alternatively or additionally, the thickness 106t of the second layer 106 can be less than twice the spatial pore size of the first layer 104. This can reduce, for example, minimize, the stress-temperature gradient of the layer structure 104, 106. In other words, the difference in the stress-temperature gradient between the first layer 104 and the layer structure 104, 106 can be reduced.

[0092] The thickness 106t of the second layer 106 can be in a range of approximately 1 µm to approximately 10 µm, e.g. in the range of approximately 2 µm to approximately 7 µm, e.g. in the range of approximately 2 µm to approximately 5 µm.

[0093] By adjusting the ratio (also called thickness ratio) of the thickness 414t of the first layer 104 after planarization (also called planarized thickness 414t) and the thickness 106t of the second layer 106, the mechanical properties of the layer structure 104, 106 (layer stack 104, 106) can be adjusted. For example, hardness or mechanical strength can be increased by reducing the thickness ratio.

[0094] According to various embodiments, the thickness ratio can be in the range of approximately 1 to approximately 100, e.g. in the range of approximately 1 to approximately 50, e.g. in the range of approximately 1 to approximately 30, e.g. in the range of approximately 2 to approximately 20, e.g. in the range of approximately 3 to approximately 10, e.g. in the range of approximately 3.3 to approximately 4.5.

[0095] Optionally, one or more layers can be formed above the second layer 106, such as at least one layer stack that, for example, provides a surface for diffusion soldering. For example, one or more metallization layers can be formed above the second layer 106.

[0096] To illustrate, the first layer 104 can have or be formed from high porosity and high roughness. During planarizing and sputtering, the area 104t, 104p of the first layer 104 can be sealed.

[0097] The Fig. 5A and Fig. 5B illustrates a schematic representation 500a according to different embodiments.

[0098] Diagram 500a shows the stress 503 (in megapascals - MPa) as a function of the temperature 501 of the layer structure 104, 106. The stress 503 has a tensile region 503t and a compressive region 503c. A cooling cycle is represented by line 501c and a heating cycle by line 501h.

[0099] A stress-temperature gradient for a thickness ratio of approximately 3.3 (illustrated in diagram 500a), defined, for example, by a planarized thickness 414t of approximately 16.8 µm and a thickness 106t of the second layer 106 of approximately 5 µm, can be greater than a stress-temperature gradient for a thickness ratio of approximately 4.5 (illustrated in diagram 500b), defined, for example, by a planarized thickness 414t of approximately 22.5 µm and a thickness 106t of the second layer 106 of approximately 5 µm.

[0100] The stress-temperature gradient of the layer structure 104, 106 can be in the range of approximately 0.1 MPa / K to approximately 1 MPa / K, e.g. in the range of approximately 0.2 MPa / K to approximately 0.7 MPa / K, e.g. in the range of approximately 0.3 MPa / K to approximately 0.5 MPa / K.

[0101] Fig. Figure 6A illustrates a schematic representation 600a similar to diagram 500a for the layer structure 104, 106 before the formation of the second layer 106.

[0102] In comparison with diagrams 500a and 500b, the stress-temperature gradient is not significantly increased by the formation of the second layer 106 above the first layer 104. In other words, the first layer 104 can provide a stress compensation region (illustratively, a stress compensation layer 104).

[0103] Fig. Figure 6B illustrates a device according to different embodiments in a processing stage of a method according to different embodiments in a schematic representation 600b.

[0104] Diagram 600b shows a resistance (in milliohms - mOhm) that is exemplary for different layer structures 504, 506, 508 before planarizing 602, after planarizing 604, after planarizing and annealing 604 and after forming the second layer 106 604.

[0105] For a first layer structure 504, the resistance in 602 is approximately 5.96 mΩ, in 604 it is approximately 6.05 mΩ, in 606 it is approximately 4.65 mΩ, and in 608 it is approximately 2.85 mΩ. For a second layer structure 506, the resistance in 602 is approximately 6.09 mΩ, in 604 it is approximately 7.34 mΩ, in 606 it is approximately 3.37 mΩ, and in 608 it is approximately 1.95 mΩ. For a third layer structure 508, the resistance in 602 is approximately 5.66 mΩ, in 604 it is approximately 5.58 mΩ, in 606 it is approximately 2.59 mΩ, and in 608 it is approximately 2.01 mΩ.

[0106] For the examples shown, the specific resistance can be reduced from approximately 8.5 microohm centimeters (µOhm cm) before planarizing to 4.55 µOhm cm after forming the second layer 106.

[0107] According to various embodiments, the specific resistance of a layer structure 104, 106 before planarization can be more than approximately 5 µOhm cm, e.g. more than approximately 6 µOhm cm, e.g. more than approximately 7 µOhm cm, e.g. more than approximately 8 µOhm cm, e.g. in the range of approximately 7 µOhm cm up to approximately 10 µOhm cm.

[0108] The specific resistance of a layer structure 104, 106 after the formation of the second layer 106 can be less than approximately 7 µOhm cm, e.g. less than approximately 6 µOhm cm, e.g. less than approximately 5 µOhm cm, e.g. less than approximately 4 µOhm cm, e.g. in the range of approximately 3 µOhm cm to approximately 7 µOhm cm.

[0109] According to various embodiments, the specific resistance of a layer structure 104, 106 can be reduced by planarizing and forming the second layer 106 by more than approximately 10%, e.g., more than approximately 20%, e.g., more than approximately 30%, e.g., more than approximately 40%, e.g., in the range of approximately 10% to approximately 50%.

[0110] Alternatively or additionally, the specific resistance of a layer structure 104, 106 can be reduced by planarizing and forming the second layer 106 by more than approximately 1 µOhm cm, e.g. more than approximately 2 µOhm cm, e.g. more than approximately 3 µOhm cm, e.g. more than approximately 4 µOhm cm, e.g. in the range of approximately 1 µOhm cm to approximately 5 µOhm cm.

[0111] The Fig. Figures 7A to 7C illustrate a device according to different embodiments in a processing stage of a method according to different embodiments in a schematic cross-sectional view or side view.

[0112] The device 700a can have a first layer 104 formed over the substrate 102. The first layer 104 can be formed by sintering a granulate. The granulate can have or be formed from several particles 704p. After sintering the granulate, the first layer 104 can have or be formed from a porous structure 702 (e.g., including a network of partially interconnected pores 304t).

[0113] The size (e.g., an average extent) of the 704p particles before sintering can be in the range of approximately 0.1 µm to approximately 10 µm, e.g., in the range of approximately 1 µm to approximately 10 µm, e.g., in the range of approximately 1 µm to approximately 5 µm.

[0114] The device 700b can have a first layer 104 having a planarized surface 104p. The planarized surface 104p can be formed by at least one of the following processes: machining, machine polishing, electrochemical polishing, and chemical-mechanical polishing. The planarized surface 104p can also be formed after sintering the granules. The planarized surface 104p can be open-pored 304o; in other words, the pores 304t of the first layer 104 can have openings in the planarized surface 104p.

[0115] Planarizing the first layer 104 can reduce its roughness. In other words, the roughness of the planarized surface 104p can be smaller than the roughness of the surface 104t as formed. For example, planarizing the first layer 104 can be configured to reduce its roughness to a value less than at least one less than the spatial pore size and particle size of the first layer 104.

[0116] The device 700c can have a second layer 106 formed over the planarized surface 104p. The second layer 106 can seal the pores 304t of the planarized surface, such as covering the openings 304o of the pores 304t.

[0117] The second layer 106 can have or be formed from at least one (e.g. spatially averaged) property selected from the following properties: a pore size smaller than the first layer 104; a hardness greater than the first layer 104; a resistivity smaller than the first layer 104; a stress-temperature gradient greater than the first layer 104; or a density greater than the first layer 104.

[0118] The Fig. Figures 8A to 8C illustrate a device according to different embodiments in a processing stage of a method according to different embodiments in a schematic cross-sectional view or side view.

[0119] The device 800a can have the first layer 104 above the substrate 102. The first layer 104 can be formed by sintering a granulate. The granulate can consist of or be formed from several particles 704p. After sintering the granulate, the first layer 104 can have or be formed from a porous structure 702.

[0120] The device 800b can have a first layer 104 having a planarized surface 104p. The planarized surface 104p can be formed by at least one of the following processes: machining, machine polishing, electrochemical polishing, and chemical-mechanical polishing. The planarized surface 104p can also be formed after sintering the granules. The planarized surface 104p can optionally be closed-pored 304c; in other words, the pores 304t of the first layer 104 can be at least partially sealed by the planarized surface 104p.

[0121] Planarizing the first layer 104 can involve deforming a material of the first layer 104, such as the particles 704p. Therefore, the material of the first layer 104 can at least partially seal and / or at least partially fill the pores 304t. Illustratively, planarizing can involve pressing on the first layer 104 to deform the material of the first layer 104. A first section of the material of the first layer 104 can be removed, and a second section of the material of the first layer 104 can be deformed. Sealing the pores can facilitate the formation of the second layer 106 over the first layer 104.

[0122] During the planarization of the first layer 104, a pore property of surface 104t, 104p (e.g., surface layer 104s) of the first layer 104 can be increased. For example, a gradient in at least one pore property can be created by planarizing the first layer 104. In other words, at least one of the pore density, pore size, and porosity at surface 104t, 104p can be reduced by planarizing the first layer 104.

[0123] At least one pore property of the first layer 104 away from the substrate 102 can be smaller than near the substrate 102. For example, the gradient can be directed towards the substrate 102.

[0124] At least one pore property of the first layer 104 (e.g., the planarized layer 104p) can be reduced by planarization by more than approximately 10%, e.g., more than approximately 20%, e.g., more than approximately 30%, e.g., more than approximately 40%, e.g., more than approximately 50%, e.g., more than approximately 60%, e.g., more than approximately 70%, e.g., more than approximately 80%, e.g., more than approximately 90%, e.g., approximately 100%. For example, at least one pore property of the first layer 104 can be reduced to approximately zero by planarization. In this case, the pores 304t of the first layer 104 can be completely sealed after planarization.

[0125] The device 800c can have a second layer 106 formed over the planarized surface 104p. Optionally, the second layer 106 can seal the pores 304t of the planarized surface, such as the remaining openings 304o from the pores 304t.

[0126] Fig. Figure 9 illustrates a process 900 according to various embodiments in a flowchart.

[0127] Method 900, as described in 902, comprises the formation of at least one electronic component in a substrate. Method 900, as described in 904, further comprises the formation of a contact point in electrical contact with the at least one electronic component. The formation of the contact, as described in 906, comprises: the formation of a first layer over the substrate; the planarization of the first layer to form a planarized surface; and the formation of a second layer over the planarized surface. The second layer has a lower porosity than the first layer.

[0128] Fig. Figure 10A illustrates a process 1000a according to different embodiments in a flowchart.

[0129] Method 1000a can include in 1002 the formation of a first layer over a substrate. Method 1000a can further include in 1004 the planarization of the first layer to form a planarized surface of the first layer. Method 1000a can further include in 1006 the formation of a second layer over the planarized surface.

[0130] Optionally, the porosity of the first layer can be greater than at least one of the porosity of the substrate and the porosity of the second layer.

[0131] Optionally, the second layer can be formed by physical vapor deposition.

[0132] Optionally, the first layer and the second layer can be made from the same material (e.g., the same solid).

[0133] Fig. Figure 10B illustrates a process 1000b according to various embodiments in a flowchart.

[0134] Method 1000b can, in 1012, comprise the arrangement of solid particles over a substrate and the sintering of the solid particles to form a first layer that has a higher porosity than the substrate. Method 1000b can further comprise, in 1014, the planarization of the first layer to form a planarized surface. Method 1000b can further comprise, in 1016, the formation of a second layer, which has a lower porosity than the first layer, over the planarized surface.

[0135] Optionally, the second layer can be formed by physical vapor deposition, such as sputtering.

[0136] Fig. Figure 11A illustrates a semiconductor device 1100a according to various embodiments in a processing stage of a method according to various embodiments in a schematic cross-sectional view or side view.

[0137] According to various embodiments, the semiconductor device 1100a can have several electronic components (also referred to as semiconductor circuit elements) 1702a, 1702b, 1702c which are electrically connected in parallel to each other 1904 and are in electrical contact with one or more layer structures 104, 106.

[0138] The semiconductor device 1100a can have a first metallization 1922 on a first side 102t of the substrate 102, wherein the first metallization 1922 can optionally have or be formed from the first layer 104 and the second layer 106. Each electronic component of the multiple electronic components 1702a, 1702b, 1702c can be electrically connected to the first metallization 1922 1904.

[0139] Alternatively or additionally, the semiconductor device 1100a can have a second metallization 1822 on a second side 102b of the substrate 102, wherein the second metallization 1822 can optionally have or be formed from the first layer 104 and the second layer 106. Each electronic component of the multiple electronic components 1702a, 1702b, 1702c can be electrically connected 1904 to the second metallization 1822.

[0140] At least one contact point 1706, 1708a, 1708b (see, for example) Fig. 3 or Fig. 11B) can, for example, be formed from at least one of the first metallization 1922 and the second metallization 1822. Alternatively, a rewiring layer can be formed from at least one of the first metallization 1922 and the second metallization 1822.

[0141] Each electronic component of the multiple electronic components 1702a, 1702b, 1702c can have or be formed from a diode structure (also called a diode cell) or a transistor structure (also called a transistor cell). The multiple electronic components 1702a, 1702b, 1702c can be part of or form a power electronic component 1702. For example, each electronic component of the multiple electronic components 1702a, 1702b, 1702c (e.g., the power electronic component 1702) can have or be formed from a transistor (e.g., a power transistor). Alternatively or additionally, each electronic component of the multiple electronic components 1702a, 1702b, 1702c (e.g., the power electronic component) can have or be formed from a vertical structure.A vertical structure can be understood as providing a current flow from the first side 102t of the substrate 102 to the second side 102b of the substrate 102, or vice versa. Alternatively or additionally, each of the multiple electronic components 1702a, 1702b, 1702c (e.g., the power electronic component 1702) can have at least one gate contact point. The at least one gate contact point can be provided by (e.g., formed from) the first metallization 1922 (if present).

[0142] According to various embodiments, the second layer 106 can be at least one of the following: a protective layer, a solderable layer, a bondable layer, and a pore-sealing layer. The protective layer can optionally have or be formed from a metallic hard coating.

[0143] Fig. 11B illustrates a semiconductor device 1100b according to various embodiments in a processing stage of a method according to various embodiments in a schematic cross-sectional view or side view.

[0144] The semiconductor device 1100b can comprise at least one electronic component 1702a, 1702b, 1702c, such as a power electronic component 1702, which is formed at least one of and within the semiconductor region. The at least one electronic component 1702a, 1702b, 1702c, 1702 can, for example, comprise or be formed from at least one transistor (in other words, one or more transistors) in electrical contact 1704 with at least one layer structure 104, 106. The electronic component 1702a, 1702b, 1702c, 1702 can comprise or be formed from a bipolar transistor with an insulated gate electrode.

[0145] According to various embodiments, the semiconductor device 1100b can have at least one first contact point 1706 (e.g., at least one collector contact point 1706). The at least one first contact point 1706 can be electrically connected to the at least one electronic component 1702a, 1702b, 1702c, 1702. Optionally, the at least one first contact point 1706 can be formed by structuring the layer structure 104, 106 as described above.

[0146] Alternatively or additionally, the semiconductor device 1100b can have at least one second contact point 1708a, 1708b (e.g., a source / drain contact point 1706) that is in electrical contact 1710 with the at least one electronic component 1702a, 1702b, 1702c, 1702. The at least one second contact point 1708a, 1708b can optionally have a gate contact point 1708b, which can be, for example, electrically insulated from the substrate 102. Optionally, the at least one second contact point 1708a can be formed by structuring the layer structure 104, 106 as described above.

[0147] In other words, at least one of the at least one first contact point 1706 and at least one second contact point 1708a, 1708b can have the layer structure 104, 106.

[0148] A method for forming a device 1100a, 1000b may comprise: forming an active chip region comprising at least one electronic component 1702a, 1702b, 1702c, 1702 at least one of which is in and above a substrate 102; forming at least one contact point 1706, 1708a, 1708b in electrical contact with the active chip region. The at least one contact point 1706, 1708a, 1708b may comprise or be formed from a first layer 104 and a second layer 106, wherein the first layer 104 is arranged between the second layer 106 and the active chip region. The second layer 106 has at least one of the following properties: a porosity smaller than that of the first layer 104; a hardness greater than that of the first layer 104; a resistivity smaller than that of the first layer 104; a stress-temperature gradient greater than the first layer 104; and a density greater than the first layer 104.The first layer 104 may have or be formed a porous stress compensation layer to provide a stress temperature gradient less than at least one between the first layer 104 and the substrate 102.

[0149] Fig. Figure 12A illustrates a semiconductor device 1200a according to various embodiments in a processing stage of a method according to various embodiments in a schematic cross-sectional view or side view, such as an electronic component 1702a, 1702b, 1702c, e.g. a power electronics component 1702.

[0150] The semiconductor device 1200a can have the doped semiconductor layer 108l formed on a second side 102b of the substrate. The doped semiconductor layer 108l can have or be formed from a first type of doping. The doped semiconductor layer 108l can have or be formed from a collector region (a doped region in the form of a collector region).

[0151] The semiconductor device 1200a can further comprise a first contact point 1706 in the form of a collector contact point 1706 (e.g., a drain contact point). The first contact point 1706 can electrically contact the doped semiconductor layer 108l. The first contact point 1706 can have the layer structure 104, 106 or be formed therefrom. The first contact point 1706 can cover more than half of the doped semiconductor layer 108l, such as covering substantially all of the doped semiconductor layer 108l (e.g., more than approximately 80% of the doped semiconductor layer 108l).

[0152] Furthermore, the semiconductor device 1200a can have a first doped region 2006 (the first doped semiconductor region 2006). The first doped region 2006 can have a base region or be formed from one. The first doped region 2006 can have a doping type (e.g., a dopant with a doping type) identical to the doped semiconductor layer 108l (in other words, the dopant of the doped semiconductor layer 108l), such as a first doping type. The semiconductor device 1200a can further have a second contact point 1708a which electrically contacts the first doped region 2006. The second contact point 1708a can have an emitter contact point 1708a (e.g., a source contact point 1708a) or be formed from one. The second contact point 1708a can have the layer structure 104, 106 or be formed from one.

[0153] Furthermore, the semiconductor device 1200a can have a second doped region 2004 formed between the first doped region 2006 and the doped semiconductor layer 108l. The second doped region 2004 can be a drift region or be formed from one. The second doped region 2004 can have a doping type (second doping type) that differs from that of the doped semiconductor layer 108l, such as a dopant with a second doping type. The second doped region 2004 can optionally have an epitaxially formed layer.

[0154] The semiconductor device 1200a can further comprise a second contact point 1708b. This second contact point 1708b can be a gate contact point 1708b or be formed from one. The second contact point 1708b can be electrically isolated from the second doped region 2004, for example, by an electrically insulating layer formed between the second contact point 1708b and the second doped region 2004. The second contact point 1708b can have the layer structure 104, 106 or be formed from one.

[0155] Furthermore, the semiconductor device 1200a can have a third doped region 2008. The third doped region 2008 can be an emitter region or be formed from one. The third doped region 2008 can have a doping type (e.g., a dopant with a doping type) that differs from that of the doped semiconductor layer 108l, such as the second doping type. The doping concentration of the third doped region 2008 can be higher than that of the second doped region 2004.

[0156] Optionally, the semiconductor device 1200a can have a fourth doped region 2002 between the second doped region 2004 and the doped semiconductor layer 108l. The fourth doped region 2002 can have a field stop region or be formed from one. The fourth doped region 2002 can have a dopant with a doping type that differs from that of the doped semiconductor layer 108l. The fourth doped region 2002 can have a doping concentration that is higher than that of the second doped region 2004.

[0157] The first doping method can be n-type and the second doping method can be p-type. Alternatively, the first doping method can be p-type and the second doping method can be n-type.

[0158] The semiconductor device 1200a, such as an electronic component 1702, may have or be formed from a transistor structure, such as a planar transistor structure (which, for example, provides vertical current flow). A transistor structure may have or be formed from multiple pn junctions. A pn ​​junction may be formed by an interface between two doped regions that differ in their doping types, such as an interface between at least one of the following: the first doped region 2006 and the second doped region 2004; the first doped region 2006 and the third doped region 2008; the second doped region 2004 and the doped semiconductor layer 108l; or the second doped region 2004 and the fourth doped region 2002 (if present).

[0159] The electronic component 1702 may include or be formed from a bipolar transistor with an insulated gate electrode.

[0160] Fig. Figure 12B illustrates a device 1200b according to various embodiments in a processing stage of a method according to various embodiments in a schematic cross-sectional or side view. The semiconductor device 1200b can have the doped semiconductor layer 108l formed on the second side 102b. The doped semiconductor layer 108l can have or be formed from a first type of doping. The doped semiconductor layer 108l can have or be formed from a first transition region.

[0161] The semiconductor device 1200b can further comprise a first contact point 1706 which electrically contacts the doped semiconductor layer 108l. The first contact point 1706 can be an electrode contact point or be formed from one. The first contact point 1706 can have the layer structure 104, 106 or be formed from one. The first contact point 1706 can substantially cover the doped semiconductor layer 108l.

[0162] Furthermore, the semiconductor device 1200b can have a first doped region 2006. The first doped region 2006 can have or be formed from a second transition region. The first doped region 2006 can have a dopant with a doping type that differs from that of the doped semiconductor layer 108l (in other words, the dopant of the doped semiconductor layer 108l), such as the second doping type. The semiconductor device 1200b can also have a second contact point 1708a, which electrically contacts the first doped region 2006. The second contact point 1708a can have or be formed from another electrode contact point. The second contact point 1708a can have or be formed from the layer structure 104, 106.

[0163] Optionally, the semiconductor device 1200b can have a second doped region 2002 between the first doped region 2006 and the doped semiconductor layer 108l. The second doped region 2002 can be a field stop region or be formed from one. The second doped region 2002 can have a doping type (e.g., a dopant with a doping type) identical to that of the doped semiconductor layer 108l. The second doped region 2002 can have a doping concentration that is higher than that of the first doped region 2006.

[0164] The semiconductor device 1200b, such as an electronic component 1702b, 1702b, 1702b, e.g., a power electronics component 1702, may have or be formed from a diode structure, such as a planar diode structure (which provides a vertical current flow). A diode structure may have or be formed from a pn junction, which is formed, for example, by an interface between two doped regions that differ in their doping types, such as an interface between the first doped region 2006 and the doped semiconductor layer 108l, or an interface between the second doped region 2002 (if present) and the first doped region 2006.

[0165] Optionally, the doped semiconductor layer 108l can have or be composed of several first segments exhibiting the first doping type and several second segments exhibiting the second doping type. The segments of the multiple first segments and the segments of the multiple second segments can be arranged in an alternating sequence. In this case, the doped semiconductor layer 108l can be part of a reverse diode structure.

[0166] The Fig. 13A and Fig. Figure 13B shows a device according to various embodiments in a processing stage of a method according to various embodiments in a schematic cross-sectional view or side view.

[0167] The device 1300a can have a first layer 104 and a second layer 106. Furthermore, the device 1300a can have a solder joint 1302 formed over the first layer 104, e.g., over the second layer 106, for example, in electrical contact with the second layer 106. The first layer 104 can be in electrical contact with at least one of the substrate 102 and the second layer 106. At least one contact point 1708a, 1708b, 1706 can, for example, be electrically contacted by the solder joint 1302.

[0168] The solder joint 1302 may contain or be formed from a solder material. The solder material may contain or be formed from at least one of the following metals: lead (Pb), tin (Sn), silver (Ag), aluminum (Al). Optionally, the solder material may contain or be formed from a metal alloy (also referred to as a solder alloy) containing at least one of the following metals: Pb, Sn, Ag, Al. For example, the solder alloy may be an Sn-based solder alloy or a Pb-based solder alloy. The solder alloy may optionally contain alloying elements such as magnesium (Mg), zinc (Zn), zirconium (Zr), nickel (Ni), palladium (Pd), or gold (Au).

[0169] The device 1300b can have a first layer 104 and a second layer 106. Furthermore, the device 1300b can have a bond connection 1304 formed over the first layer 104, e.g., over the second layer 106, for example, in electrical contact with the second layer 106. The first layer 104 can be in electrical contact with at least one of the substrate 102 and the second layer 106. At least one contact point 1708a, 1708b, 1706 can, for example, be electrically contacted by the bond connection 1304.

[0170] Bond compound 1304 may contain or be composed of a bonding material. The bonding material may contain or be composed of at least one of the following metals: Ag, Al, Au, copper (Cu). Optionally, the bonding material may contain or be composed of a metal alloy (also referred to as a bonding alloy) containing at least one of the following metals: Ag, Al, Au, Cu. For example, the bonding alloy may be an Ag-based alloy (in other words, an alloy that is predominantly Ag) or an Al-based alloy. The bonding alloy may optionally contain alloying elements such as Mg, Zn, Zr, Sn, Ni, and Pd.

[0171] The Fig. 14A and Fig. Figure 14B shows a device according to various embodiments in a processing stage of a method according to various embodiments in a schematic cross-sectional view or side view.

[0172] The device 800a can have the first layer 104 above the substrate 102. The first layer 104 can consist of or be formed from granules. The granules can consist of or be formed from multiple particles 704p. The first layer 104 can be formed from a paste 1404 comprising the particles 704p and an organic binder 1406.

[0173] The first layer 104 can be planarized by pressing it, for example, using a pressing tool 1402. The pressing tool 1402 (e.g., a press ram) can exert a force 1402f on the first layer 104 to compact it. Pressing the first layer 104 can reduce its roughness and / or increase its density. During pressing, the first layer 104 can be dried, for example, to remove liquid components of the paste.

[0174] Optionally, the first layer 104, such as at least the area of ​​the first layer 104, can be compacted. Compaction (also referred to as compression) can reduce at least one pore property.

[0175] The densified surface of the first layer 104 can optionally provide the shape of the second layer 106 by electrophoretic coating, such as electrochemical deposition.

[0176] During the pressing of the first layer 104, the granules can be heated to remove the organic binder 1406. Furthermore, the granules can be sintered during the pressing of the first layer 104. In other words, the first layer 104 can be planarized before or during sintering.

[0177] The device 1400b can have the second layer 106, which is formed over the first layer 104 as previously described.

[0178] Furthermore, various embodiments are described below.

[0179] 1. A method for producing a layered structure, wherein the method comprises: Forming a first layer of at least one of in and above a substrate, wherein the first layer protrudes from an exposed surface of the substrate and has at least one of a greater porosity, a larger pore size and a greater pore density than the substrate; and planarizing the first layer to e.g. smaller than the pore size of the first layer.

[0180] 2. The method of paragraph 1, forming a second layer over the first layer which has at least one of a lower porosity, a lower pore size and a lower pore density than the first layer.

[0181] 3. A method for producing a layered structure, wherein the method comprises: Forming a first layer of at least one of [something] in and above a substrate; mechanically strengthening a surface of the layer structure by at least one of: Compaction of at least one surface region of the first layer, wherein at least one of the porosity, pore size and pore density of the surface region is reduced by compaction (e.g. freed of pores); and Replacing the surface area of ​​the first layer with a (e.g., pore-free) second layer that has at least one lower porosity, smaller pore size, and lower pore density than the first layer. 4. A method for producing a layered structure, wherein the method comprises: Forming a first layer of at least one of in and above a substrate; Planarize the first layer to form a planarized surface of the first layer; and Forming a second layer over the planarized surface, which has at least one lower porosity, smaller pore size and lower pore density porosity than the first layer. 5. A method for manufacturing an electronic device, wherein the method comprises: Formation of at least one electronic component in a substrate; Forming a contact point in electrical contact with the at least one electronic component; wherein the formation of the contact point comprises: Forming a first layer over the substrate; Planarize the first layer to form a planarized surface of the first layer; and Forming a second layer over the planarized surface, wherein the second layer has at least one of lower porosity, smaller pore size and lower pore density than the first layer. 6. The procedure of one of paragraphs 2 to 5, the second layer is formed by physical vapor deposition. 7. The procedure of one of paragraphs 2 to 6, the second layer is formed using a plasma, such as by sputtering. 8. The procedure of one of paragraphs 2 to 7, wherein the first layer and the second layer consist of the same material (e.g. the same solid), such as a metal (e.g. at least one of copper, silver and nickel) or a non-metal. 9. The procedure of one of paragraphs 2 to 8, wherein the first layer and the second layer are formed from the same material (e.g. the same solid), such as a metal (e.g. at least one of copper, silver and nickel) or a non-metal. 10. A method for producing a layered structure, wherein the method comprises: Forming a first layer over a substrate; Planarize the first layer to form a planarized surface of the first layer; and Forming a second layer above the planarized surface; wherein at least one of the porosity, pore size and pore density of the first layer is greater than a corresponding porosity, pore size and pore density of the substrate and greater than a corresponding The porosity, pore size, and pore density of the second layer are; the second layer is formed by physical vapor deposition; and wherein the first layer and the second layer consist of or are formed from the same material, such as the same solid. 11. The procedure of one of paragraphs 1 to 9, wherein at least one of the porosity, pore size and pore density of the first layer is greater than a corresponding porosity, pore size and pore density of the substrate and a corresponding porosity, pore size and pore density of the second layer. 12. The procedure of any one of paragraphs 1 to 11, the first layer is formed from solid particles. 13. The procedure of any one of paragraphs 1 to 12, the first layer is formed by solid particle deposition. 14. The procedure of any one of paragraphs 1 to 13, the first layer is formed from solid particles that are arranged above the substrate and sintered. 15. A method for producing a layered structure, wherein the method comprises: Arranging solid particles over a substrate and sintering the solid particles to form a first layer that has at least one of greater porosity, larger pore size and greater pore density than the substrate; Planarize the first layer to form a planarized surface of the first layer; and Forming a second layer, which has at least one layer with a lower porosity, smaller pore size and lower pore density porosity than the first layer, over the planarized surface; the second layer is formed using a plasma, such as by sputtering. 16. The procedure of any one of paragraphs 1 to 15, wherein the first layer is a porous layer or has at least one porous region. 17. The procedure of one of paragraphs 2 to 16, where the second layer seals at least one pore of the first layer. 18. The procedure of any one of paragraphs 1 to 17, wherein at least one of the first layer and the second layer comprises or can be formed from an electrically conductive material. 19. The procedure of any one of paragraphs 1 to 18, where the hardness of the first layer is less than the hardness of at least one of the second layer and the substrate. 20. The procedure of one of paragraphs 1 to 19, where the specific resistance of the first layer is at least one less than the specific resistance of the second layer and greater than the specific resistance of the substrate. 21. The procedure of any one of paragraphs 1 to 20, where a stress temperature gradient of the first layer is smaller than a stress temperature gradient of at least one of the second layer and the substrate. 22. The procedure of any one of paragraphs 1 to 21, where the density of the first layer is less than the density of at least one of the second layer and the substrate. 23. The procedure referred to in any of paragraphs 2 to 22, wherein the second layer is formed by at least one of the following (in other words, at least one deposition process selected from the following deposition processes): physical vapor deposition; pressure deposition; and chemical vapor deposition. 24. The procedure of paragraph 23, where the physical vapor deposition may include or be formed from sputtering or reactive sputtering. 25. The procedure of paragraph 23 or 24, where the chemical vapor deposition includes or is formed from plasma-enhanced chemical vapor deposition. 26. The procedure of any one of paragraphs 1 to 25, wherein the formation of at least one of the first layer and the second layer involves the use of a fluid-free deposition process. 27. The procedure of any one of paragraphs 1 to 26, wherein the formation of at least one of the first layer and the second layer involves the use of or is formed from an electrolyte-free deposition process. 28. The procedure of any one of paragraphs 1 to 27, wherein at least one of the substrate and the second layer is essentially pore-free. 29. The method of any one of paragraphs 2 to 28, wherein the thickness of the second layer is at least one of: greater than half a spatial pore size of the first layer and less than twice the spatial pore size of the first layer. 30. The procedure of one of paragraphs 1 to 4 or 6 to 29, further comprising: Forming a contact point including at least one from the first layer and the second layer. 31. The procedure of any one of paragraphs 2 to 30, wherein the second layer and the first layer comprise at least one of, or are formed from, the same metal, ceramic, glass, metal oxide, metal nitride, metal carbide, dielectric, semiconductor and chemical composition. 32. The procedure referred to in any of paragraphs 2 to 31, wherein the second layer comprises or is formed from at least one of the following materials: a metal, a ceramic, a glass, a metal oxide, a metal nitride, a metal carbide, a dielectric and a semiconductor. 33. The procedure of one of paragraphs 2 to 32, wherein the second layer is at least one of the following: a protective layer, a solderable layer, a bondable layer and a pore sealing layer. 34. The procedure of any one of paragraphs 1 to 33, wherein the first layer comprises or is formed from at least one of the following materials: a metal, a ceramic, a glass, a metal oxide, a metal nitride, a metal carbide, a dielectric and a semiconductor. 35. The procedure of any one of paragraphs 1 to 34, wherein the first layer has or is formed from an open-pore surface of at least one of before planarizing the first layer and after planarizing the first layer. 36. The procedure of any one of paragraphs 1 to 35, where the planarization of the first layer exhibits or is formed by the thinning of the first layer. 37. The procedure of any one of paragraphs 1 to 36, where planarizing the first layer involves forming a gradient in at least one of the following pore properties of the first layer: a pore density; a pore size; and a porosity. 38. The procedure of any one of paragraphs 1 to 37, where the planarization of the first layer involves a reduction of a pore property of a surface of the first layer or is formed from it. 39. The procedure of any one of paragraphs 1 to 38, where the formation of the first layer involves the sintering of a granulate or is formed from it. 40. The procedure of any one of paragraphs 1 to 39, wherein the planarization of the first layer includes or is formed from at least one of the following: machining, machine polishing, electrochemical polishing and chemical-mechanical polishing. 41. The procedure of paragraphs 14, 15, 39 or 40, the first layer is planarized after it has been sintered. 42. The procedure of any one of paragraphs 1 to 41, where the planarization of the first layer involves or is formed by the pressing of the first layer. 43. The procedure of paragraphs 14, 15, 39, 40 or 42, where the first layer is planarized at least one before and during sintering. 44. The procedure of any one of paragraphs 1 to 43, further comprising: Heating the first layer after planarizing, e.g. before forming the second layer, to at least one temperature below the evaporation temperature of an organic binder and the sintering temperature. 45. The procedure of any one of paragraphs 1 to 44, further comprising: Forming a solder joint across at least one of the first layer and the second layer. 46. ​​The method of any one of paragraphs 2 to 45, further comprising: electrical contacting of the second layer. 47. The procedure of any one of paragraphs 1 to 46, further comprising: Forming a bond connection across at least one of the first layer and the second layer. 48. The method of any one of paragraphs 1 to 47, forming at least one barrier layer and one adhesive layer between the first layer and the substrate. 49. The procedure of any one of paragraphs 1 to 48, where planarizing the first layer reduces the roughness of the first layer. 50. The procedure of any one of paragraphs 1 to 49, where the planarization of the first layer is configured to form a roughness of the first layer of less than a spatial pore size of the first layer. 51. The procedure of any one of paragraphs 1 to 50, the first layer is formed by a printing process. 52. The procedure of any one of paragraphs 1 to 4 and 6 to 51, further comprising: Forming an electronic component in the substrate, wherein the electronic component is electrically connected to at least one of the first layer and the second layer. 53. The procedure of any one of paragraphs 1 to 52, wherein the planarizing of the first layer comprises at least one of at least partial filling and at least partial sealing of the pores of the first layer away from at least one of the surface and the substrate with material of the first layer. 54. The procedure of any one of paragraphs 1 to 53, where the planarization of the first layer exhibits the formation of a pore property of the first layer that is larger near the substrate than farther from the substrate. 55. The procedure of any one of paragraphs 1 to 54, where the planarization of the first layer exhibits the formation of a gradient in a pore property directed towards the substrate. 56. The procedure of any one of paragraphs 2 to 55, where the planarization of the first layer exhibits the formation of a gradient in a pore property directed away from the second layer. 57. The procedure of any one of paragraphs 1 to 56, wherein at least one of the following pore properties of at least one of the substrate or the second layer is essentially zero: a pore density; a pore size; and a porosity. 58. A layered structure that exhibits: a first layer formed in and above a substrate, wherein the first layer protrudes from the exposed surface of the substrate; at least one of which has a greater porosity, a larger pore size and a greater pore density than the substrate; and a planarized surface with, for example, a roughness smaller than the pore size of the first layer. 59. The procedure of paragraph 58, wherein a second layer formed above the planarized surface has at least one of lower porosity, smaller pore size and lower pore density than the first layer. 60. A layered structure that exhibits: a first layer that is formed in and above a substrate; a mechanically hardened surface consisting of at least one of: a compacted surface region of the first layer, wherein the surface region has at least one of lower porosity, smaller pore size and lower pore density than the first layer in a region near the substrate; and a second layer, wherein at least one of the porosity, pore size and pore density of the second layer is smaller than a corresponding porosity, pore size and pore density of the first layer. 61. A layered structure that exhibits: a first layer that is formed in and above a substrate; wherein the first layer has a planarized surface; and a second layer formed above the planarized surface having at least one of lower porosity, lower pore size and lower pore density than the first layer. 62. A layered structure in an electronic device, wherein the electronic device comprises: at least one electronic component formed in a substrate; a contact point which is in electrical contact with the at least one electronic component; wherein the contact point comprises: a first layer formed above the substrate, wherein the first layer has a planarized surface; and a second layer formed on top of the planarized surface, wherein the second layer has at least one of lower porosity, lower pore size and lower pore density than the first layer. 63. The layer structure of one of paragraphs 59 to 62, wherein the first layer and the second layer consist of the same material (e.g. the same solid), such as a metal (e.g. at least one of copper, silver and nickel) or a non-metal. 64. The layer structure of one of paragraphs 59 to 63, wherein the first layer and the second layer are formed from the same material (e.g. the same solid), such as a metal (e.g. at least one of copper, silver and nickel) or a non-metal. 65. A layered structure that exhibits: a first layer formed over a substrate and exhibiting a planarized surface; and a second layer formed above the planarized surface; wherein at least one of the porosity, pore size and pore density of the first layer is greater than a corresponding porosity, pore size and pore density of the substrate and greater than a corresponding porosity, pore size and pore density of the second layer; wherein the first layer and the second layer consist of or are made of the same material (e.g. the same solid). 66. The layer structure of one of paragraphs 58 to 65, wherein at least one of a porosity, a pore size and a pore density of the first layer is greater than at least one of: a corresponding porosity, pore size and pore density of the substrate and a corresponding porosity, pore size and pore density of the second layer. 67. The layer structure of one of paragraphs 58 to 66, the first layer is formed from solid particles. 68. The layer structure of one of paragraphs 58 to 67, the first layer is formed from solid particles that are arranged above the substrate and sintered. 69. A layered structure that exhibits: a first layer formed over a substrate, wherein the first layer comprises sintered particles and at least one of which has a greater porosity, a larger pore size and a greater pore density than the substrate; wherein the first layer has a planarized surface; and a second layer, which has at least one layer of lower porosity, smaller pore size and smaller pore density than the first layer and is formed above the planarized surface; the second layer is formed using a plasma, e.g. by sputtering. 70. The layer structure of one of paragraphs 58 to 69, wherein the first layer is a porous layer or has at least one porous region. 71. The layer structure of one of paragraphs 58 to 70, where the second layer seals at least one pore of the first layer. 72. The layer structure of one of paragraphs 58 to 71, where a pore property of the first layer is greater than a pore property of at least one of the second layer and the substrate. 73. The layer structure of one of paragraphs 58 to 72, where the hardness of the first layer is less than the hardness of at least one of the second layer and the substrate. 74. The layer structure of one of paragraphs 58 to 73, where the specific resistance of the first layer is at least one less than the specific resistance of the second layer and greater than the specific resistance of the substrate. 75. The layer structure of one of paragraphs 58 to 74, where a stress temperature gradient of the first layer is smaller than a stress temperature gradient of at least one of the second layer and the substrate. 76. The layer structure of one of paragraphs 59 to 75, where the density of the first layer is less than the density of at least one of the second layer and the substrate. 77. The layer structure of one of paragraphs 58 to 76, wherein at least one of the first layer and the second layer is free of a fluid. 78. The layer structure of one of paragraphs 58 to 77, wherein at least one of the first layer and the second layer is free of an electrolyte. 79. The layer structure of one of paragraphs 58 to 78, wherein at least one of the second layer and the substrate is essentially pore-free. 80. The layer structure of one of paragraphs 59 to 79, where the thickness of the second layer is at least one of: greater than half the spatial pore size of the first layer and less than twice the spatial pore size of the first layer. 81. The layer structure of one of paragraphs 59 to 80, wherein the second layer and the first layer have the same material (e.g. the same solid) or are formed from it. 82. The layer structure of one of paragraphs 59 to 81, wherein the second layer and the first layer contain or are formed from at least one of: the same metal, the same ceramic, the same glass, the same metal oxide, the same metal nitride, the same metal carbide, the same dielectric, the same semiconductor and the same chemical composition. 83. The layer structure of one of paragraphs 59 to 82, wherein the second layer comprises or is formed from at least one of the following materials: a metal, a ceramic, a glass, a metal oxide, a metal nitride, a metal carbide, a dielectric and a semiconductor. 84. The layer structure of one of paragraphs 59 to 83, wherein the second layer is at least one of the following: a protective layer, a solderable layer, a bondable layer and a pore sealing layer. 85. The layer structure of one of paragraphs 58 to 84, wherein the first layer comprises or is formed from at least one of the following materials: a metal, a ceramic, a glass, a metal oxide, a metal nitride, a metal carbide, a dielectric and a semiconductor. 86. The layer structure of one of paragraphs 58 to 85, the first layer has an open-pored surface. 87. The layer structure of one of paragraphs 58 to 86, wherein the first layer has a gradient in at least one of the following pore properties: a pore density; a pore size; and a porosity. 88. The layer structure of one of paragraphs 58 to 87, where a pore property of a surface region of the first layer is smaller than a pore property of a region of the first layer near the substrate. 89. The layer structure of one of paragraphs 58 to 88, wherein the first layer consists of or is formed from sintered granules. 90. The layer structure of one of paragraphs 58 to 89, wherein the first layer has a planarized surface formed by at least one of the following: machining, machine polishing, electrochemical polishing and chemical-mechanical polishing. 91. The layer structure of one of paragraphs 58 to 90, wherein the first layer has a planarized surface formed by pressing the first layer. 92. The layer structure of one of paragraphs 58 to 91, further comprising: a soldered joint formed over at least one of the first layer and the second layer. 93. The layer structure of one of paragraphs 59 to 92, further comprising: an electrical contact to the second layer. 94. The layer structure of one of paragraphs 58 to 93, further comprising: a bond connection that extends over at least one of the first layers and is formed in the second layer. 95. The layer structure of one of paragraphs 58 to 94, further comprising: at least one of a barrier layer and an adhesive layer formed between the first layer and the substrate. 96. The layer structure of one of paragraphs 58 to 95, where the roughness of the planarized surface is smaller than the spatial pore size of the first layer. 97. The layer structure of one of paragraphs 58 to 96, the first layer is formed by a printing process. 98. The layer structure of one of paragraphs 58 to 61 and 63 to 97, further comprising: an electronic component formed in the substrate, wherein the electronic component is electrically connected to the first layer. 99. The layer structure of one of paragraphs 58 to 98, wherein the first layer has pores away from the substrate, at least one of which is at least partially filled with material from the first layer and at least partially sealed with it. 100. The layer structure of one of the paragraphs 58 to 99, where a pore property of the first layer is larger near the substrate than further away from the substrate. 101. The layer structure of one of the paragraphs 58 to 100, where a gradient in a pore property of the first layer is directed towards the substrate. 102. The layer structure of one of paragraphs 59 to 101, where a gradient in a pore property of the first layer is seen away from the second layer. 103. The layer structure of one of paragraphs 58 to 102, where at least one of the following pore properties of at least one of the substrate and the second layer is essentially zero: a pore density; a pore size; and a porosity. 104. The method of any of paragraphs 1 to 57 or the layer structure of one of paragraphs 58 to 102, wherein the first layer contains or is composed of at least one of copper, silver and nickel.

Claims

Method (100) for manufacturing an electronic device, the method comprising: forming at least one electronic component in a substrate (102); forming a contact point in electrical contact with the at least one electronic component (104); the formation of the contact point comprising (106): forming a first layer over the substrate; planarizing the first layer to form a planarized surface of the first layer, wherein the planarized surface has a roughness of less than 10 µm; and forming a second layer over the planarized surface, wherein the second layer has a lower porosity than the first layer. Method (100) according to claim 1, wherein the second layer is formed by at least one of a physical vapor deposition; a pressure deposition; and a chemical vapor deposition. Method (100) according to claim 1 or 2, wherein the first layer and the second layer comprise the same material. Method (100) according to any one of claims 1 to 3, wherein at least one of the following pore properties of at least one of the substrate or the second layer is substantially zero: a pore density; a pore size; and a porosity. Method (100) according to any one of claims 1 to 4, wherein the first layer is formed by depositing solid particles over the substrate. Method (100) according to claim 5, wherein the formation of the first layer comprises the sintering of the solid particles. Method (100) according to claim 6, wherein the first layer is planarized after it has been sintered. Method (100) according to claim 6, wherein the first layer is planarized before and / or during sintering. Method (100) according to any one of claims 1 to 8, wherein a stress-temperature gradient of the first layer is smaller than a stress-temperature gradient of at least one of the second layer and the substrate. Method (100) according to any one of claims 1 to 9, wherein the density of the first layer is less than the density of at least one of the second layer and the substrate. Method (100) according to any one of claims 1 to 10, wherein the thickness of the second layer is at least one of: greater than half a spatial pore size of the first layer and less than twice the spatial pore size of the first layer. Method (100) according to any one of claims 1 to 11, wherein the first layer has an open-pore surface of at least one before planarizing the first layer and after planarizing the first layer. Method (100) according to any one of claims 1 to 12, wherein the first layer comprises at least one of copper, silver and nickel. Method (100) according to any one of claims 1 to 13, wherein the planarizing of the first layer comprises the formation of a gradient in at least one of the following pore properties of the first layer: a pore density; a pore size; and a porosity. Method (100) according to any one of claims 1 to 14, wherein the planarizing of the first layer comprises at least one of the following: machining, machine polishing, electrochemical polishing and chemical-mechanical polishing. Method (100) according to any one of claims 1 to 15, further comprising: forming at least one of a solder joint and a bond joint over the contact point in order to electrically contact the contact point. Method (100) according to any one of claims 1 to 16, wherein planarizing the first layer reduces the roughness of the first layer. Method (100) according to any one of claims 1 to 17, wherein the planarizing of the first layer comprises the formation of a pore property of the first layer near the substrate larger than far from the substrate, wherein the pore property comprises a pore density, a pore size and / or a porosity. A method for producing a layered structure, comprising: forming a first layer over a substrate; planarizing the first layer to form a planarized surface of the first layer, wherein the planarized surface has a roughness of less than 10 µm; and forming a second layer over the planarized surface; wherein the porosity of the first layer is greater than the porosity of the substrate and greater than the porosity of the second layer; wherein the second layer is formed by physical vapor deposition; and wherein the first layer and the second layer are formed from the same solid. A method for producing a layered structure, comprising: arranging solid particles over a substrate and sintering the solid particles to form a first layer having a greater porosity than the substrate; planarizing the first layer to form a planarized surface of the first layer, wherein the planarized surface has a roughness of less than 10 µm; and forming a second layer with a lower porosity than the first layer over the planarized surface; wherein the second layer is formed by sputtering.

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