Method for polishing a semiconductor wafer

Abstract

Method for polishing a semiconductor disk, which is simultaneously polished on both sides on the front and on the back between an upper polishing plate (11) and a lower polishing plate (12), each of which is covered with a polishing cloth (21, 22), wherein a polishing gap (x1+x2), which corresponds to a difference in the distances of the upper polishing cloth (21) and the lower polishing cloth (22) at the inner edge (B) and at the outer edge (A) of the polishing cloths (21, 22), wherein the distance of the upper polishing cloth (21) to the lower polishing cloth (22) at the inner edge (B) is greater than at the outer edge (A), is changed in size in steps or continuously during the polishing process.

Description

[0001] The invention relates to a method for polishing a semiconductor disk.

[0002] The planarization of the disks (also called wafers) sawn from a single crystal of semiconductor material is usually carried out in several steps: a. mechanical processing (lapping, grinding) b. chemical treatment (alkaline or acid etching) c. Chemo-mechanical processing: Single-sided polishing, double-sided polishing (DSP) and single-sided haze-free or gloss polishing with a soft polishing cloth (CMP)

[0003] The mechanical processing of the semiconductor wafers primarily serves to flatten the semiconductor wafer globally and to remove the crystalline damaged surface layer and processing marks (saw marks, incision marks) caused by the previous separation process.

[0004] Etching involves the chemical removal of impurities and / or native oxides from the surface of the semiconductor wafers.

[0005] Finally, the surfaces of the semiconductor wafer are smoothed by a chemical-mechanical polishing process.

[0006] The present invention relates to double-sided polishing (DSP), a process from the group of chemo-mechanical processing steps.

[0007] According to an embodiment described in patent EP 0208315 B1, semiconductor disks in rotor disks made of metal or plastic, which have suitably dimensioned recesses, are moved and polished between two rotating polishing discs covered with a polishing cloth, with a working gap being formed between the polishing discs, in the presence of a polishing agent on a path predetermined by the machine and process parameters.

[0008] A method for double-sided polishing is known from DE 10 2013 201 663 A1, in which the required wafer geometry is achieved by setting a targeted working gap through the processing of the polishing cloths, wherein the distance from the upper to the lower polishing cloth is greater in the inner area than in the outer area.

[0009] A device is also known from DE 10 2006 037 490 B4 with which the polishing gap can be adjusted independently of the mechanically prepared gap. This is made possible by the fact that the convexity or concavity of the upper polishing plate is continuously adjustable.

[0010] According to DE 11 2013 006 059 T5, the working gap is adjusted by bellows due to the flatness of the wafers (measurement of already processed wafers).

[0011] According to DE 10 2010 024 040 A1, the shape of one of the two polishing discs is mechanically or thermally deformed to achieve an optimal working gap.

[0012] The solutions proposed in the prior art aim to optimize the geometry of the semiconductor wafers. This involves setting a suitable working gap for the polishing process.

[0013] One problem is that choosing a geometry-optimizing working gap is usually associated with a low material removal rate and therefore a low throughput.

[0014] The object of the invention is to improve the state of the art and in particular to achieve an optimized geometry when polishing a semiconductor wafer and at the same time a high material removal rate.

[0015] The invention relates to a method for polishing a semiconductor disk, which is simultaneously polished on both sides on the front and on the back between an upper polishing plate ( 11 ) and a lower polishing plate ( 12 ), each with a polishing cloth ( 21 , 22) are covered, is polished, characterized in that a polishing gap x1+x2, which corresponds to a difference in the respective distances between the surfaces of the upper polishing cloth coming into contact with the semiconductor disk ( 21 ) and lower polishing cloth ( 22 ) on the inner edge ( B ) and at the outer edge ( A ) the polishing cloths ( 21 , 22 ) corresponds to the size being changed in stages or continuously during the polishing process.

[0016] Embodiments of this method can be found in the following description, the figures and the dependent claims. List of characters Fig. Figure 1 shows two polishing pads covered with polishing cloths and the polishing gap. Fig. 2 - Fig. Figure 7 shows the change in the polishing gap over time until the polishing process is completed according to a preferred embodiment of the method. Reference symbol list 1 polishing plate 11 Upper polishing plate 12 Lower polishing plate 2 polishing cloths 21 Top polishing cloth 22 Lower polishing cloth A Outer edge / area of ​​polishing pad / polishing cloth B Inner edge / area of ​​polishing pad / polishing cloth x1 Upper polishing gap x2 Lower polishing gap

[0017] A distance between the upper polishing cloth and the surface is preferable. 21 to the lower polishing cloth 22 in the inner area B larger than in the outer area A This version is in Fig. 1 shown. From the difference of the two distances at the inner edge A and at the outer edge B or the sum of the upper polishing gap x1 and lower polishing gap x2 The polishing gap is formed. In this case, the working gap has a wedge shape.

[0018] Similarly, a distance of the upper polishing cloth can be 21 to the lower polishing cloth 22 in the inner area B be almost the same size as in the outer area A In this case, the polishing gap x1+x2 is very small, close to zero. In one embodiment of the method, the polishing run is started with a smaller polishing gap x1+x2 (nearly parallel working gap, i.e., the polishing cloth surfaces are nearly parallel) in order to ensure that the upper polishing pad is properly aligned at the start of the process. 11 as parallel as possible to the lower polishing plate 22 to set up the process and thus prevent wafer breakage and start it gently. During a short ramp, the polishing gap x1+x2 is then increased to a larger value.

[0019] The essential aspect of the invention is that the polishing gap x1+x2, defined as the difference in the distances of the upper polishing cloth 21 and the lower polishing cloth 22 in the inner area B and in the outer area A, is varied during polishing. This can be done in one or more stages, or continuously, i.e., steplessly.

[0020] The inventive method is based on the observation that a relatively small polishing gap x1+x2 is required for good wafer geometry (e.g. GBIR, ESFQR), which, however, results in a relatively small removal rate, whereas a relatively large polishing gap x1+x2 has a relatively large removal rate, but causes a poorer geometry.

[0021] In one embodiment, the invention provides for starting the process with a large polishing gap x1+x2, or, after a gentle start with a small polishing gap x1+x2, transitioning to a large polishing gap x1+x2, with a small polishing gap x1+x2 being set towards the end of the process. The final polishing step with a low material removal rate serves to optimize the geometry, while the preceding polishing step(s) are performed with a high material removal rate. The polishing step with a small polishing gap is essential to ensure the required geometry of the semiconductor wafer.

[0022] The polishing gap x1+x2 can be reduced by deformation of the polishing pads. 1 be adjusted. Before the process starts, the polishing cloths may need to be adjusted. 2 processed (dressing), whereby the shape of the polishing cloths 2The dressing also contributes to the polishing gap x1+x2. Thus, the geometry of the working gap and the polishing gap x1+x2 (as the difference between the inner and outer distances) result from a combination of polishing pad and polishing cloth geometry.

[0023] In one embodiment of the invention, prior to polishing both sides of a semiconductor disk, between the surfaces on the polishing plates, a process is carried out. 1 attached polishing cloths 2 A so-called cloth dressing. This involves the polishing cloths that are glued to the polishing pads. 2 Before the polishing process, the cloth dressing is adapted to the specific shape of the polishing pad on the polishing machine. Such methods are known in principle from the prior art and are described, for example, in EP 2 345 505 A2 or US 6,682,405 B2. Cloth dressing is advantageous because a polishing pad 1It can typically exhibit differences in local flatness of up to ± 50 µm. It serves to correct the surface on the polishing pad through mechanical processing. 1 polishing cloth 2 Using suitable tools, which usually include diamond grinding elements, both a desired polishing cloth geometry and thus a desired initial working gap geometry, as well as the desired properties of the cloth surface of the polishing cloth, can be achieved. 2 to adjust.

[0024] The invention relates to the simultaneous polishing of the front and back sides (DSP) of at least one semiconductor wafer, wherein semiconductor materials are compound semiconductors such as preferably, for example, gallium arsenide or elemental semiconductors such as mainly silicon, but also germanium, or layered structures thereof.

[0025] DSP polishing cloths 2They are usually ring-shaped, with a circular recess in the middle of the polishing cloth surface for the mechanics of the polishing machine, such as a rotary shaft for the rotary drive.

[0026] With DSP, an undesirable rounding of the disc edge (edge ​​roll-off, ERO) typically occurs. This rounding, which leads to poor edge geometry, depends, among other things, on how far the semiconductor disc is embedded in the upper polishing cloth during polishing. 21 , the lower polishing cloth 22 or in both polishing cloths 2 sinks in. This occurs when the semiconductor disc sinks into the polishing cloth. 2 Stronger material-removing forces act on the edge than on the rest of the surface.

[0027] To prevent the semiconductor disk from sinking into the polishing cloth 2 To minimize or completely avoid polishing during the polishing process, polishing cloths are preferably used in the inventive method. 2used with a high fabric stiffness and low fabric compressibility.

[0028] Preferably, a hard polishing cloth is used. 2 Shore hardness A preferably 80-100°C. A suitable, commercially available polishing cloth. 2 For example, the EXTERION™ SM- 11 D by Nitta Haas Inc. with a hardness of 85° according to JIS- A . Wipes of type MH-S24A from Nitta Haas Inc., for example, have a hardness of up to 86 JIS- A (JIS K 6253A) specified, with a hardness according to JIS- A Shore hardness A corresponds.

[0029] Unless otherwise stated, all parameters were determined at atmospheric pressure, i.e., approximately 1000 hPa, and at a relative humidity of 50%.

[0030] Shore hardness A The measurement is carried out according to DIN EN ISO 868. A durometer type is used. Afor use (Zwick hardness tester) 3130 The tip of the hardened steel rod presses into the material. The indentation depth is measured on a scale of 0–100. The steel rod has the geometry of a truncated cone. Five measurements are taken, of which the median value is reported. The measurement time is 15 seconds, and the material to be tested was exposed to standard climate conditions for 1 hour. 23 Stored at 0°C, 50% relative humidity. The durometer's contact pressure is 12.5 N ± 0.5.

[0031] A polishing cloth preferably has 2 with a low compressibility of 0.2% to less than 3%, the compressibility of the polishing cloth is particularly preferred. 2 less than 2.5%. The compressibility of the polishing cloth is particularly preferred. 2 less than 2.0%.

[0032] The compressibility of a material describes the change in pressure required in all directions to produce a specific change in volume. Compressibility is calculated analogously to JIS L-1096 (Testing Methods for Woven Fabrics).

[0033] After applying a defined pressure to the fabric surface, for example 300 g / cm² 2 The fabric thickness T1 is measured after one minute. The pressure is then increased to six times the initial pressure, in this case 1800 g / cm². 2 After one minute, the cloth thickness T2 is measured. The compressibility of the polishing cloth is calculated from the values ​​T1 and T2 using the formula: Compressibility [%] = (T1-T2) / T1 x 100.

[0034] As polishing cloths 2 Foamed polishing cloths, with their high cloth hardness and low cloth compressibility, are both suitable. 2 (foamed pads) as well as polishing cloths 2 with a fiber structure (non-woven pads).

[0035] Preferably the polishing cloth 2 a porous matrix. Preferably, the polishing cloth consists of 2 made from a thermoplastic or heat-curable polymer and has a porous matrix (foamed pad).

[0036] A wide variety of materials are preferably considered as materials, e.g. polyurethanes, polycarbonate, polyamide, polyacrylate, polyester, etc.

[0037] Preferably the polishing cloth consists of 2 made of solid micro-porous polyurethane.

[0038] The use of polishing cloths is also preferred. 2 made from foamed sheets or felt or fiber substrates impregnated with polymers (non-woven pad).

[0039] In the inventive method, the thickness of the polishing cloth is 2 preferably in the range of 0.5 to 1.3 mm, particularly preferably in the range of 0.5 to 0.9 mm.

[0040] For polishing, the semiconductor wafers are placed in a suitably sized recess of a rotor disk. Preferably, the polishing cloths are placed in the space between the working layers. 2 A liquid is supplied to the working gap formed during polishing. This liquid is preferably a polishing compound suspension. The use of colloidally dispersed silica, optionally with additives such as sodium carbonate (Na₂CO₃), potassium carbonate (K₂CO₃), sodium hydroxide (NaOH), potassium hydroxide (KOH), ammonium hydroxide (NH₄OH), or tetramethylammonium hydroxide (TMAH), as the polishing compound suspension is particularly preferred.

[0041] The polishing gap x1+x2 between the two corresponding polishing plates 1 (each with polishing cloths) 2 (as documented) ranges from 0 µm to 220 µm.

[0042] The different distances (heights) in the polishing gap x1+x2 are achieved in the inventive method by deformation of at least one of the two polishing plates. 1 This is achieved. Therefore, a double-sided polishing machine is preferably suitable for the method according to the invention, in which at least one of the two polishing discs 11, 12 can be selectively deformed during polishing.

[0043] In one embodiment, the method comprises a polishing step with a large polishing gap x1+x2 of size 130 µm to 220 µm and a polishing step with a small polishing gap x1+x2 of size 50 µm - 110 µm.

[0044] The working gap can be linear or non-linear (convex or concave).

[0045] The polishing gap x1+x2 results from the difference in the distance between the surfaces of the upper polishing cloth. 21 and the lower polishing cloth 22 the two corresponding polishing plates 1on the inner edge of the polishing plate B of the working gap and the distance between the surfaces of the upper polishing cloth 21 and the lower polishing cloth 22 the two corresponding polishing plates 1 on the outer edge of the polishing plate A of the working gap, wherein the polishing plate 1 in its center has a circular recess (for the rotary shaft of the rotary drive) which forms the inner edge of the polishing plate B educates.

[0046] When simultaneously polishing both sides of the semiconductor disk with hard and inconspicuous polishing cloths, a surface removal of less than or equal to 15 µm per side is preferably achieved, with the range of preferably 4 µm to 10 µm being particularly preferred in this respect.

[0047] The process offers increased economic efficiency compared to known DSP processes, as it results in significantly higher overall material removal rates, while achieving the required geometry of the semiconductor wafer.

[0048] In one embodiment of the method, the ratio of small polishing gap x1+x2 to large polishing gap x1+x2 is preferably 1:4 to 3:4.

[0049] Or to put it another way: If the large polishing gap x1+x2 is 100%, the small polishing gap x1+x2 is preferably between 25% and 75%.

[0050] The large polishing gap x1+x2 is preferably 150 to 220 µm, particularly preferably 150 to 190 µm, while the small polishing gap x1+x2 is preferably 0 to 130 µm, 70-120 µm and particularly preferably 50 to 110 µm.

[0051] In one embodiment, the process is a two-stage procedure in which the first stage has a larger polishing gap x1+x2 at the beginning of the procedure and the second stage has a smaller polishing gap x1+x2 at the end of the procedure, wherein the first step preferably lasts 80-90% of the polishing time and the second step preferably lasts 10-20% of the polishing time, wherein the polishing gap x1+x2 decreases in size from the first stage to the last stage by preferably 60% to 20%.

[0052] The polishing step with the large polishing gap x1+x2 should last as long as possible to achieve the highest possible material removal rate. However, the step with the small polishing gap x1+x2 must be long enough to ensure proper geometry.

[0053] In one embodiment, the process is multi-stage, in which the first stage has a large polishing gap x1+x2 at the beginning of the process and in the subsequent stages increasingly smaller polishing gaps x1+x2 towards the end of the process, wherein in a multi-stage process the reduction of the polishing gap x1+x2, which starts at 100%, to the preceding larger polishing gap x1+x2 is in the range of preferably 10% to 40% of the last preceding polishing gap x1+x2.

[0054] For example, the initial polishing gap x1+x2 is 100%, at the next polishing stage the polishing gap x1+x2 is 75% of the first polishing gap x1+x2 and has thus decreased by 25%, or at the next polishing stage the polishing gap x1+x2 is 60% of the height of the first polishing gap x1+x2 and has thus decreased by a total of 40%.

[0055] For example, the polishing gap x1+x2 could initially be 200 µm. In a first stage, the polishing gap x1+x2 is reduced by 10% to 180 µm. In a further stage, the polishing gap is reduced by 33% to 120 µm. In the final stage, the polishing gap x1+x2 is reduced by 16.7% to 100 µm.

[0056] In one embodiment of a four-stage polishing process, the first three stages with a large polishing gap x1+x2 account for a total of 80-90% of the polishing time, and the last stage with the smallest polishing gap x1+x2 preferably accounts for 10-20% of the polishing time. In principle, the first three stages can each have different polishing times; for example, the first stage could account for 40%, the second stage for 30%, the third stage for 20%, and the last stage for 10% of the total polishing time.

[0057] If the size of the polishing gap x1+x2 is 100% in the first stage, the size of the polishing gap in the following polishing stage, preferably in the second stage, is 75% of the initial height of 100%, in the third stage the size of the polishing gap x1+x2 is preferably 60% of the initial height of 100%, and in the last stage the size of the polishing gap x1+x2 is preferably 50% of the initial height of 100%, the largest polishing gap, wherein the size of the polishing gap x1+x2 of the individual stages may preferably have different values.

[0058] In one embodiment, the polishing gap x1+x2 is continuously reduced in a first step. At the beginning of a second step, the continuous reduction of the polishing gap x1+x2 is stopped, and the polishing process continues for a specific duration at the polishing gap x1+x2 that the machine has at that time, and is then finally terminated. If the polishing gap x1+x2 starts at 100% and ends at 50% of the initial polishing gap x1+x2, the polishing gap x1+x2 is continuously reduced, for example, from 200 µm to 100 µm, for a period of 80-90% of the total polishing time. Then, in the final step, polishing is performed at 50% of the initial polishing gap x1+x2 (100 µm) for a period of 10-20% of the total polishing time.

[0059] The reduction rate of the height of the polishing gap x1+x2 can preferably be linear or non-linear, preferably 80-90% of the total polishing time, wherein the last polishing step can preferably also form a single stage, which preferably accounts for 10-20% of the total polishing time.

[0060] In another embodiment, the method starts with a higher polishing gap x1+x2, in order to proceed through several stages to a stage with a smaller polishing gap height x1+x2, whereby at each polishing stage the polishing gap x1+x2 is increased again within the respective stage, wherein the polishing gap x1+x2 is first reduced in height at the next stage, in order to then increase in height again.

[0061] In another embodiment, the process starts with a parallel or nearly parallel polishing gap x1+x2 between the two corresponding polishing plates, where the difference in the distance between the two polishing plates 1 indoors B and the distance between the two polishing discs 1 in the outer area A is equal to or nearly 0 µm, in order to then continue the polishing process with a large polishing gap x1+x2, e.g. 200 µm, wherein the polishing gap x1+x2 is subsequently reduced in stages or continuously as in one of the embodiments described above.

[0062] The last polishing step, i.e. the one with the smallest polishing gap x1+x2, should account for at least 10% of the total polishing time, with the small polishing gap x1+x2 preferably being between 120 µm and 70 µm, and particularly preferably between 110 µm and 80 µm.

[0063] The polishing steps with a relatively small polishing gap x1+x2 can be carried out with a lower polishing pressure of approximately 1200 - 1500 daN.

[0064] The material removal steps with a relatively large polishing gap x1+x2 should be carried out at a polishing pressure of, for example, 1600 - 2100 daN.

[0065] In one embodiment, the polishing pressure is controlled analogously to the polishing gap x1+x2.

[0066] In one embodiment of the method, the duration of a polishing step is variable. Preferably, this polishing step is the penultimate polishing step.

[0067] In one embodiment, in-situ thickness measurement of the semiconductor wafer is provided. Suitable sensors for in-situ thickness measurement in polishing machines are known.

[0068] In one embodiment, an in-situ thickness measurement is performed, and the result of the measurement is used to vary the duration of a polishing step, in particular the ablation step(s) at a large polishing gap x1+x2. The time-varying polishing step is adjusted, i.e., its duration is lengthened or shortened, so that the semiconductor wafer has the desired target thickness at the end of the process.

[0069] The duration of the final polishing step, which optimizes the geometry, can also be variable, depending on the result of the in-situ thickness measurement of the semiconductor wafer during the process. The final polishing step can be lengthened or shortened by the time required to achieve the desired thickness of the semiconductor wafer.

[0070] Another processing step involves chemical-mechanical polishing of only the front surface of the semiconductor wafer (so-called CMP), as is known, for example, from DE 10 2008 045 534 B4. In this process, a semiconductor wafer is pressed onto a polishing cloth (which may be located on a polishing pad) by means of a carrier and then moved under pressure, usually in a rotating motion. The front surface of the semiconductor wafer is then polished using a suitable polishing compound or a polishing compound suspension. The CMP of the front surface can be carried out in one or more steps. CMP involves one or more smoothing steps (without significant removal of semiconductor material).

[0071] Optionally, a coating process follows the CMP, in which a layer is epitaxially deposited onto the CMP-polished front surface of the semiconductor wafer. This step involves depositing the epitaxial layer onto the front surface of the semiconductor wafer using chemical vapor deposition (CVD). A CVD performed in a single-wafer reactor at atmospheric pressure is particularly suitable. Typical process parameters for such a process are published in US patent 5355831 A and can be considered exemplary.

[0072] The features specified for the aforementioned embodiments of the method according to the invention can be implemented either separately or in combination as embodiments of the invention. Furthermore, they can describe advantageous embodiments that are independently patentable.

[0073] The term polishing gap and some embodiments of the method according to the invention are explained below with reference to figures. Figures

[0074] Fig. Figure 1 shows the size of the polishing gap. It shows an upper polishing plate. 11 and a lower polishing plate 12 shown, with the polishing cloth 21 of the upper polishing plate 11 at the outer edge A is thicker than at the inner edge B In contrast, the polishing cloth 22 of the lower polishing plate 12 at the outer edge A and on the inner edge B of equal thickness. This, in combination with the deformed polishing plates, results in... 11 and 12 a polishing gap of size x1 + x2.

[0075] Fig. Figure 2 shows the change in the polishing gap x1+x2 over time until the end of the polishing process according to one embodiment of the method. This is a two-stage process in which the polishing gap x1+x2 is initially constant, is reduced at a specific time, and then remains constant again until the end of the process.

[0076] Fig. Figure 3 shows the change in the polishing gap x1+x2 over time until the end of the polishing process according to a further embodiment of the method. This is a multi-stage process in which the polishing gap is reduced at three points in time, while the polishing gap is kept constant before and after these points in time. The process comprises four phases, each with constant polishing gaps.

[0077] Fig. Figure 4 shows the change in the polishing gap over time until the end of the polishing process according to another embodiment of the method. This is a continuous process without stepless transitions. The method comprises various polishing steps, during which the polishing gap is continuously reduced. Towards the end of the process, a polishing step is provided in which the polishing gap is kept constant.

[0078] Fig. Figure 5 shows the change in the polishing gap over time until the end of the polishing process according to another embodiment of the method. This is again a continuous process without stepless transitions. The method comprises only one polishing step in which the polishing gap is continuously reduced.

[0079] Fig. Figure 6 shows the change in the polishing gap over time until the end of the polishing process according to another embodiment of the method. This is a multi-stage process that starts with a polishing gap of 0 µm.

[0080] Fig. Figure 7 shows the change in the polishing gap over time until the end of the polishing process according to a further embodiment of the method. The method starts with a larger polishing gap and proceeds through several stages to a stage with a smaller polishing gap. At each polishing stage, the polishing gap is increased again within that stage. At the next stage, the polishing gap is first decreased in height and then increased again. At the following stage, the polishing gap is decreased again and then increased in height within that stage.

[0081] The foregoing description of exemplary embodiments is to be understood as illustrative. The disclosure thereby enables the person skilled in the art, on the one hand, to understand the present invention and its associated advantages, and, on the other hand, also encompasses, in the understanding of the person skilled in the art, obvious modifications and alterations of the described structures and methods. Therefore, all such modifications and alterations, as well as equivalents, are intended to be covered by the scope of protection of the claims. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] EP 0208315 B1

[0007] DE 102013201663 A1

[0008] DE 102006037490 B4

[0009] DE 112013006059 T5

[0010] DE 102010024040 A1

[0011] EP 2345505 A2

[0023] US 6682405 B2

[0023] DE 102008045534 B4

[0070] US 5355831 A

[0071] Zitierte Nicht-Patentliteratur

[0000] DIN EN ISO 868

[0030]

Claims

[1] Method for polishing a semiconductor disk which is simultaneously polished on both sides on the front and on the back between an upper polishing plate (11) and a lower polishing plate (12), each of which is covered with a polishing cloth (21, 22), characterized by , that a polishing gap (x1+x2), which corresponds to a difference in the respective distances between the surfaces of the upper polishing cloth (21) and the lower polishing cloth (22) coming into contact with the semiconductor disk at the inner edge (B) and at the outer edge (A) of the polishing cloths (21, 22), is changed in size in steps or continuously during the polishing process. [2] Method according to claim 1, comprising a two-stage method, wherein the first stage has a larger polishing gap (x1+x2) at the beginning of the method and the second stage has a smaller polishing gap (x1+x2) at the end of the method. [3] Method according to claim 1 or according to claim 2, comprising a multi-stage method wherein the polishing gap (x1+x2) is gradually reduced in size. [4] Method according to claim 1, comprising at least two polishing steps, wherein the polishing gap (x1+x2) in the second polishing step is 25% to 75% of the polishing gap (x1+x2) in the first polishing step. [5] Method according to claim 1, wherein the polishing gap (x1+x2) is continuously reduced steplessly. [6] Method according to claim 1, wherein in a first polishing step the polishing gap (x1+x2) is continuously reduced steplessly, then the reduction of the polishing gap (x1+x2) is stopped and subsequently the polishing gap (x1+x2) is kept constant until the end of the process. [7] Method according to one or more of claims 1 to 6, characterized by, that at the beginning of the process a polishing gap (x1+x2) is started with a parallel or nearly parallel gap of 0 or nearly 0, in order to then increase the polishing gap (x1+x2) to a certain size and subsequently decrease its size in stages or continuously. [8] Method according to one or more of claims 1 to 7, comprising several polishing steps, wherein a final polishing step has the smallest polishing gap (x1+x2) and accounts for at least 10% of the total polishing time. [9] Method according to claim 8, wherein the polishing gap (x1+x2) is 50 - 110 µm during the final polishing step. [10] Method according to claim 8 or according to claim 9, wherein the polishing pressure during the final polishing step is 1200 - 1500 daN. [11] Method according to one or more of claims 1 to 10, wherein the polishing pressure is changed in steps or continuously during the polishing process. [12] Method according to one or more of claims 1 to 11, comprising several polishing steps, wherein the method is carried out during at least one polishing step, which accounts for a maximum of 90% of the total polishing time, at a polishing gap (x1+x2) of 130 - 220 µm. [13] Method according to claim 12, wherein the polishing pressure in this method is 1600 - 2100 daN for at least one polishing step. [14] Method according to one or more of claims 1 to 13, comprising at least two polishing steps, wherein at least one polishing step is variable in duration. [15] Method according to one or more of claims 1 to 14, wherein a thickness measurement of the semiconductor disk is carried out during the polishing of both sides of a semiconductor disk. [16] Method according to claim 15, wherein the result of the thickness measurement is used to determine the duration of a polishing step with variable duration. [17] Method according to one or more of claims 1 to 16, further comprising a CMP polish of the front side of the semiconductor disk. [18] Method according to claim 17, further comprising an epitaxial coating of the CMP-polished front side of the semiconductor disk.