SEMICONDUCTOR DEVICE
The semiconductor device design addresses the complexity of forming contacts in miniaturized devices by using direct and buried contacts with landing pads, improving contact resistance and reliability.
Patent Information
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- SAMSUNG ELECTRONICS CO LTD
- Filing Date
- 2020-06-08
- Publication Date
- 2026-06-11
Smart Images
Figure 00000000_0000_ABST
Abstract
Description
BACKGROUND 1. Technical Area
[0001] The present disclosure relates to a semiconductor device and a method for its manufacture, and in particular to a semiconductor device comprising several wiring leads and buried contacts that intersect, and to a method for manufacturing the semiconductor device. 2. Description of the state of the art
[0002] As semiconductor devices become increasingly integrated, individual circuit patterns are miniaturized to enable the realization of more semiconductor devices in the same space. For example, as the level of integration of semiconductor devices increases, the design rules for components of the semiconductor devices are simplified.
[0003] In a greatly miniaturized semiconductor device, the process of forming multiple wiring leads and multiple buried contacts arranged between the wiring leads becomes increasingly complicated and difficult.
[0004] US 2018 / 0040561A1 discloses: A semiconductor memory device comprises word lines extending in a first direction on a semiconductor substrate, bit line structures that intersect the word lines and extend in a second direction that intersects the first direction, and contact surface structures between the word lines and between the bit line structures in a top view. A spacer structure extends between the bit line structures and the contact surface structures. The spacer structure includes a first gap extending in the second direction along the sidewalls of the bit line structures and a second gap surrounding each of the contact surface structures and coupled to the first gap.
[0005] US 2018 / 0286870A1 discloses: A volatile storage device may contain a bit-line structure with a vertical sidewall. A lower spacer may be located at a lower portion of the vertical sidewall, wherein the lower spacer may be defined by a first thickness extending from the vertical sidewall to an outer sidewall of the lower spacer. An upper spacer may be located at an upper portion of the vertical sidewall above the lower portion, wherein the upper spacer may be defined by a second thickness that is less than the first thickness, the upper spacer exposing a top portion of the outer sidewall of the lower spacer.
[0006] US 2013 / 0049209A1 discloses: A semiconductor device comprising first conductive patterns lying side by side and isolated by a trench including first and second trenches, a second conductive pattern formed in the first trench, and an insulating pattern that partially fills the second trench under the second conductive pattern and is formed between the first conductive patterns and the second conductive pattern.
[0007] US 2015 / 0262625A1 discloses: A semiconductor device comprising a bitline structure located on a semiconductor substrate, an outer bitline spacer located on a first side face of the bitline structure, an inner bitline spacer including a first part located between the bitline structure and the outer bitline spacer, and a second part located between the semiconductor substrate and the outer bitline spacer, and a block bitline spacer located between the outer bitline spacer and the second part of the inner bitline spacer. A first gap is defined by the outer bitline spacer, the inner bitline spacer, and the block bitline spacer. SUMMARY
[0008] Aspects of the present disclosure provide for a semiconductor device with improved reliability and performance, as set forth in the accompanying claims. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] These and / or other aspects will become apparent and easier to understand from the following description of the embodiments in conjunction with the accompanying drawings, in which: Fig. 1 a schematic layout view of a cell area of a semiconductor device according to embodiments; Fig. 2 is a schematic layout view of the semiconductor device, which includes the cell area of Fig. 1 contains; Fig. 3 a layout view of only word lines and active areas of Fig. 1 is; Fig. 4A and Fig. 4C Cross-sectional views along line AA from Fig. 1 according to different embodiments; Fig. 4B an enlarged view of section P of Fig. 4A is; Fig. 5 a cross-sectional view along line BB from Fig. 1 is; Fig. 6A and Fig. 6B Cross-sectional views along line CC from Fig. 2 according to different embodiments; Fig. 7, Fig. 8, Fig. 9 to Fig. 10 semiconductor devices according to different embodiments are illustrated; Fig. 11, Fig. 12 to Fig. 13 Illustrate semiconductor devices according to different embodiments; Fig. 14, Fig. 15 to Fig. 16 semiconductor devices according to different embodiments are illustrated; and Fig. Figures 17A to 34C illustrate the steps of a method for manufacturing a semiconductor device according to embodiments. DETAILED DESCRIPTION
[0010] Fig. Figure 1 is a schematic layout view of a cell area 20 of a semiconductor device according to embodiments. Fig. Figure 2 is a schematic layout view of the semiconductor device, which includes cell area 20 of Fig. 1 contains. Fig. 3 is a layout view that shows word lines WL and active areas ACT. Fig. 1. Fig. 4A and Fig. 4C are cross-sectional views along line AA of Fig. 1 according to different embodiments. Fig. 4B is an enlarged view of section P of Fig. 4A. Fig. Figure 5 is a cross-sectional view along line BB of Fig. 1. Fig. 6A and Fig. 6B are cross-sectional views along line CC of Fig. 2 according to different embodiments. For reference: Fig. 6A and Fig. 6B can display cross-sectional views along the bit lines BL of Fig. 1. According to various embodiments. In the drawings of the semiconductor device according to embodiments, a dynamic random access memory (DRAM) is shown as an example.
[0011] With reference to Fig. 1, Fig. 2 to Fig. 3. According to embodiments, the semiconductor device can include the cell region 20, a cell boundary region 22 and a border region 24.
[0012] Cell boundary region 22 can be formed along the edges of cell region 20. Cell boundary region 22 can separate cell region 20 and boundary region 24.
[0013] Cell area 20 can comprise several active areas ACT. The active areas ACT can be separated by a device insulating layer 105 (see Fig. 4A) are defined, which are in a substrate 100 (see Fig. 4A). Since the design rules of the semiconductor device are reduced, the active regions ACT, as shown in the drawings, can be arranged in the form of diagonal or slanted bars. For example, the active regions ACT can extend in a third direction D3.
[0014] Multiple gate electrodes can extend across the active regions ACT in a first direction D1. The gate electrodes can extend parallel to each other. The gate electrodes can, for example, be multiple word lines WL. The word lines WL can be arranged at equal intervals (i.e., spaced apart) in a second direction D2, which differs from the first direction D1. A width of each word line WL or a spacing between adjacent word lines WL can be determined according to the design rules. The first direction D1, the second direction D2, and the third direction D3 can correspond to horizontal directions with respect to a top surface of the substrate 100 and can differ from each other. For example, the third direction D3 can correspond to a diagonal direction between the first direction D1 and the second direction D2.
[0015] Each of the active areas ACT can be subdivided into three parts by two word lines WL extending in the first direction D1. Each of the active areas ACT can contain memory link areas 103b and one bit line link area 103a. The bit line link area 103a can be located in a central part of each of the active areas ACT, and the memory link areas 103b can be located at opposite ends of each of the active areas ACT. For example, the bit line link area 103a can be located between the two word lines WL that intersect each of the active areas ACT. One of the two word lines can be located between the bit line link area 103a and one of the two memory link areas 103b, and the other can be located between the bit line link area 103a and the other of the two memory link areas 103b.
[0016] Multiple bit lines BL can be arranged on the word lines WL such that they extend orthogonally to the word lines WL in the second direction D2. The bit lines BL can run parallel to each other. The bit lines BL can be arranged at equal intervals (i.e., spaced apart) in the first direction D1. The width of each bit line BL or the spacing between adjacent bit lines BL can be determined according to the design rules.
[0017] The semiconductor device, according to its embodiment, can contain various contact arrays formed on the active areas ACT. These different contact arrays can include, for example, direct contacts DC, buried contacts BC, and landing pads LP.
[0018] Here, the direct contacts can be DC contacts that electrically connect the active areas ACT to the bit lines BL. The buried contacts BC can be contacts that connect the active areas ACT to the lower electrodes 191 (see Fig. 4A) of capacitors. Due to the arrangement structure, the contact areas between the buried contacts BC and the active areas ACT can be small. Therefore, conductive landing pads LP can be introduced to increase the contact areas of the buried contacts BC with the active areas ACT and also to increase the contact areas of the buried contacts BC with the lower electrodes 191 (see Fig. 4A) to increase the number of capacitors.
[0019] The landing pads LP can be arranged between the buried contacts BC and the lower electrodes 191 of the capacitors. Although not shown, the landing pads LP can also be arranged between the active areas ACT and the buried contacts BC. In the semiconductor device according to the embodiments, the landing pads LP can be arranged between the buried contacts BC and the lower electrodes 191 of the capacitors. The increased contact areas resulting from the introduction of the landing pads LP can reduce the contact resistance between the active areas ACT and the lower electrodes 191 of the capacitors.
[0020] The direct contacts DC can be connected to the bit line connection areas 103a. The buried contacts BC can be connected to the memory connection areas 103b. Since the buried contacts BC are located at opposite ends of each active area ACT, the landing pads LP can be positioned at opposite ends of each active area ACT to partially overlap the buried contacts BC. For example, the buried contacts BC can be configured to overlap the active areas ACT and the device insulating layer 105 (see Fig. 4A), which are arranged between adjacent word lines WL and between adjacent bit lines BL.
[0021] The word lines WL can be buried in substrate 100. The word lines WL can cross the active areas ACT, which are located between the direct contacts DC or the buried contacts BC. As shown, two word lines WL can cross one active area ACT. Since the active areas ACT extend in the third direction D3, the word lines WL can run at an angle of less than 90 degrees to the active areas ACT.
[0022] The direct contacts (DC) and the buried contacts (BC) can be arranged symmetrically or repetitively on the active areas (ACT). For example, the direct contacts (DC) and the buried contacts (BC) can be spaced apart in the first direction (D1) and in the second direction (D2). In contrast to the direct contacts (DC) and the buried contacts (BC), the landing pads (LP) on the active areas (ACT) can be arranged in a zigzag pattern in the second direction (D2), where the bit lines (BL) run. Furthermore, the landing pads (LP) can overlap the same side of each bit line (BL) in the first direction (D1), where the word lines (WL) run. For example, each landing pad (LP) of a first line can overlap the left side of a corresponding bit line (BL), and each landing pad (LP) of a second line can overlap the right side of the corresponding bit line (BL).
[0023] With reference to Fig. According to embodiments 1 to 6B, the semiconductor device can include several gate structures 110, several bit line structures 130, several memory contacts 120 and an information storage part (i.e. a storage capacitor) 190.
[0024] Substrate 100 can be, for example, bulk silicon or silicon-on-insulator (SOI). Alternatively, substrate 100 can be a silicon substrate or a substrate made from another material, such as silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited to these. In the following description, substrate 100 is described as a silicon substrate.
[0025] The device insulating layer 105 can be formed in the substrate 100. The device insulating layer 105 can have an STI structure (STI = shallow trench isolation), which exhibits excellent element insulating properties. The device insulating layer 105 can define the active regions ACT in the substrate 100. The active regions ACT defined by the device insulating layer 105 can be shaped like elongated islands, each containing a short axis and a long axis, as shown in Fig. Figure 1 shows that the active areas ACT can be shaped like diagonal lines at an angle of less than 90 degrees to the word lines WL formed in the device insulating layer 105. Furthermore, the active areas ACT can be shaped like diagonal lines at an angle of less than 90 degrees to the bit lines BL on the device insulating layer 105.
[0026] In the cell boundary area 22, a cell boundary separating layer exhibiting the STI structure can be formed.
[0027] The device insulating layer 105 can, for example, contain at least one silicon oxide layer, one silicon nitride layer, and one silicon oxynitride layer. Although the device insulating layer 105 in Fig. The fact that 4A to 5 is formed as a single insulating layer serves only to simplify the description, and embodiments are not limited to this case. Furthermore, the cell boundary separator can, for example, contain at least one silicon oxide layer, one silicon nitride layer, and one silicon oxynitride layer.
[0028] In Fig. 6A and Fig. 6B, an upper surface of the device insulating layer 105, an upper surface of the substrate 100, and an upper surface of the cell boundary separating layer of the cell boundary region 22 lie in the same plane (i.e., they are coplanar). However, this is merely for the sake of simplicity, and the embodiments are not limited to this case.
[0029] The gate structures 110 can be formed in the substrate 100 and the device insulating layer 105. The gate structures 110 can be formed above the device insulating layer 105 and the active areas ACT defined by the device insulating layer 105. A gate structure 110 can be formed in the substrate 100 and the device insulating layer 105 in the first direction D1 in which the gate structure 110 extends. Each of the gate structures 110 can include a gate trench 114 formed in the substrate 100 and the device insulating layer 105, a gate insulating layer 111, a gate electrode 112, and a gate cover pattern 113. Here, the gate electrode 112 can correspond to a word line WL.
[0030] The gate insulating layer 111 can extend along the side walls and a bottom surface of the gate trench 114. The gate insulating layer 111 can extend along the profile of at least a portion of the gate trench 114. The gate insulating layer 111 can contain silicon oxide, silicon nitride, silicon oxynitride, or a material with a high dielectric constant (high-k) that is higher than that of silicon oxide. The material with a high dielectric constant can contain, for example, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate and combinations thereof.
[0031] The gate electrode 112 can be formed on the gate insulating layer 111. The gate electrode 112 can fill part of the gate groove 114.
[0032] The gate electrode 112 can, for example, be made of at least one of the following materials: polysilicon, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide Contains (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V) and combinations thereof.
[0033] The gate covering pattern 113 can be formed on the gate electrode 112. The gate covering pattern 113 can fill the remaining part of the gate trench 114, except for the portion in which the gate electrode 112 is formed. Although the gate insulating layer 111 is shown extending along the side walls of the gate covering pattern 113, the embodiments are not limited to this case.
[0034] The gate cover pattern 113 can contain at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN) and combinations thereof.
[0035] In Fig. 5. The position of the bottom part of a gate structure 110 formed in the substrate 100 can differ from the position of the bottom part of a gate structure 110 formed in the device insulating layer 105. Due to a difference between the etch rate of the substrate 100 and the etch rate of the device insulating layer 105 during the gate groove formation process 114, the position of the bottom part of the gate structure 110 formed in the substrate 100 can differ from the position of the bottom part of the gate structure 110 formed in the device insulating layer 105. Although not shown, a doping region can form on at least one side of each gate structure 110. The doping region can be a source / drain region of a transistor.
[0036] Each bitline structure 130 can be formed on the substrate 100 and the device insulating layer 105, in which the gate structures 110 are formed or embedded. Each bitline structure 130 can intersect the device insulating layer 105 and an active region ACT defined by the device insulating layer 105. Each bitline structure 130 can contain a bitline contact part 130_1 and a bitline pass-through part 130_2. For example, in each bitline structure 130, the bitline contact part 130_1 and the bitline pass-through part 130_2 can be repeated alternately in the second direction D2. In this case, the bit line contact part 130_1 of a bit line structure 130 can be spaced apart in the first direction D1 from the bit line pass-through part 130_2 of another bit line structure 130, which is adjacent to the first bit line structure 130, in the first direction D1. (See e.g. Fig. 1 and Fig. 4A).
[0037] The bit line contact part 130_1 can be electrically connected to the active area ACT. For example, the bit line contact part 130_1 of any bit line structure 130 can be connected to the active area ACT. The bit line contact part 130_1 can be located on the bit line connection area 103a. The bit line contact part 130_1 can be connected to the bit line connection area 103a. The bit line contact part 130_1 can be a part containing a direct DC contact. Part of the bit line contact part 130_1 can correspond to the direct DC contact.
[0038] The bit line pass-through part 130_2 of each bit line structure 130 is not electrically connected to the active area ACT. The bit line pass-through part 130_2 is electrically connected to the active area ACT, but is also electrically connected to the active area ACT via the bit line contact part 130_1. The bit line pass-through part 130_2 can be arranged in the second direction D2 between adjacent bit line contact parts 130_1. For example, in each bit line structure 130, the bit line contact part 130_1 and the bit line pass-through part 130_2 can be repeated alternately in the second direction D2.
[0039] The bit line pass-through part 130_2 can be located in the first direction D1 on the device insulating layer 105 between the adjacent memory connection areas 103b. The bit line pass-through part 130_2 of a bit line structure 130 can be spaced in the first direction D1 from the bit line contact part 130_1 of another bit line structure 130, which is adjacent to the first bit line structure 130, in the first direction D1. (See e.g. Fig. 1 and Fig. 4A).
[0040] In the views ( Fig. 4A and Fig. 4C) In a region between adjacent word lines WL along the first direction D1, the bit line contact part 130_1 can be located on the bit line connection area 103a and the device insulating layer 105, and the bit line pass-through part 130_2 can be located on the memory connection area 103b and the device insulating layer 105. For example, the bit line connection area 103a and the memory connection area 103b, which are spaced apart in the first direction D1, can each be located on two different active areas that are spaced apart in the first direction D1.
[0041] A bitline structure 130 can contain a bitline stack 140, a bitline spacer 150 and a bitline mask pattern 155.
[0042] In the bit line contact part 130_1, the bit line spacer 150 can contain a bit line contact opening 150op, which exposes an active area ACT, e.g., the bit line connection area 103a. In the bit line contact part 130_1, the bit line spacer 150, which defines the bit line contact opening 150op, exposes the active area ACT. The bit line structure 130 can be connected to the active area ACT through the bit line contact opening 150op. For example, in the bit line contact part 130_1, the bit line spacer 150 can be arranged on opposite side walls of the bit line stack 140, e.g., a lower part thereof.
[0043] In the bit line feed-through section 130_2, the bit line spacer 150 can extend along the side walls of the bit line stack 140 and a bottom surface of the bit line stack 140. The bit line spacer 150 can define a bit line trench 150t.
[0044] The bit line spacer 150 can include a lower line spacer 151 and an upper line spacer 152. The upper line spacer 152 can be arranged on top of the lower line spacer 151. The upper line spacer 152 can, for example, vertically overlap the lower line spacer 151. In the semiconductor device according to embodiments, the stacked structure of the lower line spacer 151 can differ from that of the upper line spacer 152.
[0045] In the bit line contact part 130_1, the lower line spacer 151 can define the bit line contact opening 150op, which exposes the bit line connection area 103a. In the bit line contact part 130_1, the lower line spacer 151 exposes the active area ACT. The lower line spacer 151 can be arranged on a portion of each side wall of the bit line stack 140. In the bit line feed-through part 130_2, the lower line spacer 151 can include one or more insulating layers that extend continuously along a portion of each side wall of the bit line stack 140 and the bottom surface of the bit line stack 140. In the semiconductor device according to embodiments, the lower conductor spacer 151 can contain an insulating layer that extends continuously along a part of the opposite side walls of the bit conductor stack 140 and the bottom surface of the bit conductor stack 140.
[0046] The upper conduit spacer 152 can include the first to third upper sub-spacers 152a to 152c. The first upper sub-spacer 152a can be L-shaped. The first upper sub-spacer 152a can include a base portion extending along an upper surface of the lower conduit spacer 151, as well as a projecting portion extending from the base portion and vertically in the direction of the thickness of the substrate 100. Here, the "L-shape" includes not only a case in which the base portion and the projecting portion form a 90-degree angle, but also a case in which the base portion and the projecting portion meet at an angle greater than 90 degrees and less than 180 degrees, or at an angle greater than 0 degrees and less than 90 degrees. Furthermore, the "L-shape" here includes not only an L-shape having an angled curved portion, but also an L-shape having a rounded curved portion.The first upper sub-spacer 152a can be bent towards the bit line stack 140.
[0047] The second upper sub-spacer 152b can be arranged on the base of the first upper sub-spacer 152a. The third upper sub-spacer 152c can be arranged on the first and second upper sub-spacers 152a and 152b.
[0048] Each of the lower sub-spacer 151, the first upper sub-spacer 152a, and the third upper sub-spacer 152c can, for example, contain at least one of silicon oxide, silicon oxycarbide (SiOC), silicon nitride (SiN), silicon oxynitride (SiON), and silicon oxycarbonitride (SiOCN), respectively. The second upper sub-spacer 152b can be an air spacer (i.e., an air gap). If at least one of the first upper sub-spacer 152a and the third upper sub-spacer 152c contains the same material as the lower sub-spacer 151, the first upper sub-spacer 152a and / or the third upper sub-spacer 152c can be considered integrated with the lower sub-spacer 151. Since the second upper sub-spacer 152b is an air spacer, the upper sub-spacer 152 can contain an air spacer. The lower conductor spacer 151 does not contain an air spacer.The term "air" discussed here can refer to atmospheric air or other gases that may be present during the manufacturing process.
[0049] In Fig. 4A and Fig. 4C, the second upper sub-spacer 152b can be inserted between the first upper sub-spacer 152a and the third upper sub-spacer 152c. In one exemplary embodiment, the first upper sub-spacer 152a, a sacrificial layer, and the third upper sub-spacer 152c can be arranged sequentially on the side walls of the bit line stack 140, and then the sacrificial layer is removed to form the air spacer of the second upper sub-spacer 152b. However, this is only for the sake of simplicity, and embodiments are not limited to this case.
[0050] The bitline stack 140 can be arranged on the substrate 100, and the device insulating layer 105 is located in the second direction D2, in which the bitline stack 140 extends. The bitline stack 140 can fill a portion (e.g., a lower portion) of the bitline trench 150t. The bitline stack 140 can be configured to intersect the gate structures 110. Here, the bitline stack 140 can correspond to a bitline BL. Furthermore, in the bitline contact part 130_1, a portion of the bitline stack 140 can correspond to the direct contact DC.
[0051] The bitline stack 140 can, for example, contain a first conductive layer 141, a second conductive layer 142, and a third conductive layer 143. The first to third conductive layers 141 to 143 can be stacked sequentially on the substrate 100 and the device insulating layer 105. Each of the first to third conductive layers 141 to 143 can contain at least one of an impurity-doped semiconductor material, a conductive silicide compound, a conductive metal nitride, and a metal. For example, the first conductive layer 141 can contain a pattern of doped semiconductor material, the second conductive layer 142 can contain a conductive silicide pattern, and the third conductive layer 143 can contain a metallic conductive layer pattern. The metallic conductive layer pattern can contain at least one conductive metal nitride and a metal, but is not limited to these.
[0052] Although the third conductive layer 143 in Fig. 4A, Fig. 4C, Fig. 6A and Fig. The fact that 6B is shown as a single layer is merely for the sake of simplicity, and embodiments are not limited to this case. The third conductive layer 143 can contain a conductive barrier layer and a conductive filler layer that fills a barrier notch defined by the conductive barrier layer. The conductive barrier layer can extend along an upper surface of the second conductive layer 142 and a portion of each sidewall of the bit-line trench 150t.
[0053] In the bit line contact part 130_1, part of the first conductive layer 141 can correspond to the direct DC contact. The first conductive layer 141 can electrically connect the bit line stack 140 to the active area ACT, for example, to the bit line connection area 103a.
[0054] The bitline mask pattern 155 can be placed on the bitline stack 140. The bitline mask pattern 155 can fill the other part (e.g., an upper part) of the bitline trench 150t. The bitline mask pattern 155 can, for example, contain at least one of silicon oxide, silicon oxycarbide (SiOC), silicon nitride (SiN), silicon oxynitride (SiON), and silicon oxycarbonitride (SiOCN).
[0055] The bit line stack 140 can be arranged across cell area 20 and cell boundary area 22. Part of the bit line stack 140 can also be arranged on cell boundary area 22.
[0056] In Fig. 2 and Fig. 6A The thickness t12 of the third conductive layer 143 in cell region 20 can be greater than the thickness t11 of the third conductive layer 143 in cell boundary region 22. Although the thickness t11 of the third conductive layer 143 in cell boundary region 22 is shown to be smaller than the thickness t12 of the third conductive layer 143 in cell region 20, embodiments are not limited to this case. In cell boundary region 22, the third conductive layer 143 can also include a portion having the thickness t12 of the third conductive layer 143 in cell region 20 and a portion having a thickness t11 that is smaller than the thickness t12 of the third conductive layer 143 in cell region 20.
[0057] Since part of an edge buffer insulating layer 106 and part of a cell buffer insulating layer 107 are arranged between the bit line stack 140 and the cell boundary region 22, the thickness t11 of the third conductive layer 143 in the cell boundary region 22 can be smaller than the thickness t12 of the third conductive layer 143 in the cell region 20. The edge buffer insulating layer 106 and the cell buffer insulating layer 107 do not extend into the cell region 20.
[0058] In Fig. 2 and Fig. 6B, the thickness t12 of the third conductive layer 143 in cell region 20 can be substantially the same as the thickness t11 of the third conductive layer 143 in cell boundary region 22. The edge buffer insulating layer 106 and the cell buffer insulating layer 107 may not be located between the bit line stack 140 and the cell boundary region 22.
[0059] In Fig. 4A and Fig. 4B The bit line structure 130 can contain an interface 130i that meets the device insulating layer 105 and the memory interconnect areas 103b. The bit line pass-through part 130_2 can contain the interface 130i that meets the device insulating layer 105 and the memory interconnect areas 103b. The interface 130i of the bit line pass-through part 130_2 contains a first sub-interface 130ia that meets the device insulating layer 105, and a second sub-interface 130ib that meets the memory interconnect areas 103b.
[0060] For example, the first sub-boundary surface 130ia of the bit line pass-through part 130_2 can be concave. The second sub-boundary surface 130ib of the bit line pass-through part 130_2 can be curved towards the bit line stack 140.
[0061] The bit line pass-through part 130_2 extends into the memory connection areas 103b. If, for example, no etching occurs during a manufacturing process, each of the memory connection areas 103b may have an OL outline. However, a portion of each of the memory connection areas 103b may be etched during the process of forming the bit line structure 130. In this way, a portion (e.g., a lower end) of the bit line pass-through part 130_2 may extend into the memory connection areas 103b. Thus, for example, the lower end of the bit line pass-through part 130_2 may be buried in the memory connection areas 103b. The second sub-boundary surface 130ib of the bit line pass-through part 130_2 is recessed more towards the substrate 100 than the OL outline of each of the memory connection areas 103b.Unlike in the drawings, in outline OL each of the memory connection areas 103b can be a part in which an upper surface of outline OL is connected to each side wall of outline OL.
[0062] In Fig. 4A and Fig. 4C, the bit line pass-through section 130_2, which extends into the memory interconnect areas 103b, is symmetrical with respect to the device insulating layer 105. However, this is merely for the sake of simplicity, and embodiments are not limited to this case. In one exemplary embodiment, the bit line pass-through section 130_2, which extends into the memory interconnect areas 103b, is not symmetrical with respect to the device insulating layer 105. For example, the depth of the bit line pass-through section 130_2, which extends into the memory interconnect area 103b on one side of the device insulating layer 105, may differ from the depth of the bit line pass-through section 130_2, which extends into the memory interconnect area 103b on the other side of the device insulating layer 105.
[0063] Fence patterns 170 can be formed on the substrate 100 and the device insulating layer 105. The fence patterns 170 can be formed such that they overlap the gate structures 110, which are formed or buried in the substrate 100 and the device insulating layer 105. The fence patterns 170 can be formed on the gate structures 110 and extend in the first direction D1. The fence patterns 170 can be arranged between the bitline structures 130, which extend in the second direction D2. The fence patterns 170 can, for example, contain at least one silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. Although each of the fence patterns 170 is shown as a single layer, this is merely for the sake of simplicity, and the embodiments are not limited to this case.
[0064] Each of the memory contacts 120 can be formed between adjacent gate structures 110 and between adjacent bitline structures 130. Each of the memory contacts 120 can overlap the substrate 100 and the device insulating layer 105 between adjacent gate structures 110 and adjacent bitline structures 130. Here, the memory contacts 120 can correspond to the buried contacts BC. Each of the memory contacts 120 can include a portion that extends along the sidewalls of the bitline structures 130 and the sidewalls of the fence patterns 170.
[0065] Each of the memory contacts 120 can contain, for example, at least one impurity-doped semiconductor material, one conductive silicide compound, one conductive metal nitride and metal.
[0066] In the semiconductor device according to embodiments, the height h12 of the lowest part of each memory contact 120 from the bottom surface of the device insulating layer 105 can be less than the height h13 of the lowest part of the bit line pass-through part 130_2 from the bottom surface of the device insulating layer 105. Furthermore, the height h12 of the lowest part of each memory contact 120 from the bottom surface of the device insulating layer 105 can be greater than the height h11 of the lowest part of the bit line contact part 130_1. Here, the height comparison can be based on a cross-sectional view along the first direction D1 of Fig. 1 will be carried out.
[0067] In Fig. In embodiments 4A to 4C, each memory contact 120 does not vertically overlap a bottom surface of the bit line pass-through part 130_2. However, the embodiments are not limited to this case. Depending on a margin in the manufacturing process, a portion of each memory contact 120 may extend along the bottom surface of the bit line pass-through part 130_2 to overlap the bottom surface of the bit line pass-through part 130_2. In this case, each memory contact 120 may have a shape similar to the letter L.
[0068] In Fig. 4A and Fig. 4B Each memory contact 120 can contain an interface 120i corresponding to the device insulating layer 105 and a memory connection area 103b. The interface 120i of each memory contact 120 contains a third sub-interface 120ia that meets the device insulating layer 105 and a fourth sub-interface 120ib that meets the memory connection area 103b. For example, the fourth sub-interface 120ib of each memory contact 120 can be located at a greater height from the bottom surface of the device insulating layer 105 than the third sub-interface 120ia of each memory contact 120. Fig. In 4B, part of the fourth sub-boundary surface 120ib of the memory contact 120 is located at the same height as the third sub-boundary surface 120ia of the memory contact 120. However, the embodiments are not limited to this case. Depending on the tolerance in the manufacturing process, the fourth sub-boundary surface 120ib of each memory contact 120 can be higher overall than the third sub-boundary surface 120ia of each memory contact 120.
[0069] In the semiconductor device according to embodiments, the height h13 of the lowest part of the bit line through-part 130_2 from the bottom surface of the device insulating layer 105 can be less than a height h14 of a highest part of the fourth sub-boundary surface 120ib of each memory contact 120 and greater than the height h12 of a lowest part of the fourth sub-boundary surface 120ib of each memory contact 120.
[0070] Each of the memory connection areas 103b can contain an upper part 130b_1 that abuts a memory contact 120, and a lower part 130b_2 that does not abut the memory contact 120. Each of the memory contacts 120 extends into a memory connection area 103b. The fourth sub-boundary surface 120ib of each memory contact 120 is recessed further towards the substrate 100 than the outline OL of a memory connection area 103b. In the semiconductor device according to embodiments, the upper part 130b_1 of each memory connection area 103b is recessed further towards the substrate 100 than the outline OL of each memory connection area 103b.
[0071] In Fig. 4A and Fig. 4B, the upper part 130b_1 of each memory connection area can be rounded to 103b. Alternatively, with reference to Fig. 4C by considering Fig. 4B in the upper part 130b_1 of each memory interconnection area 103b an upper surface of the memory interconnection area 103b and each side wall of the memory interconnection area 103b meet at an angle.
[0072] Memory pads 160 can be formed on the memory contacts 120. The memory pads 160 can be electrically connected to the memory contacts 120. The memory pads 160 can correspond to the landing pads LP. The memory pads 160 can partially overlap the upper surfaces of the bit line structures 130 or not overlap the upper surfaces of the bit line structures 130. The memory pads 160 can contain, for example, at least one impurity-doped semiconductor material, a conductive silicide compound, a conductive metal nitride, or a metal.
[0073] A pad separator layer 180 can be formed on the memory pads 160, the bitline structures 130, and the fence patterns 170. The pad separator layer 180 can define each of the spaced memory pads 160. Furthermore, the pad separator layer 180 can be structured to expose a portion of the upper surface of each memory pad 160. The pad separator layer 180 can contain an insulating material to electrically isolate the memory pads 160 from one another. For example, the pad separator layer 180 can contain at least one silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof.
[0074] An etch stop layer 185 can be formed on the pad separator layer 180 and the memory pads 160. The etch stop layer 185 can contain at least one silicon nitride layer, one silicon carbonitride layer, one silicon oxynitride layer, and one silicon oxycarbide layer.
[0075] The information storage part 190 can be formed on the pad separator layer 180. The information storage part 190 can be electrically connected to the storage pads 160. For example, the information storage part 190 can be electrically connected to the storage contacts 120. Part of the information storage part 190 can be arranged in the etch stop layer 185. The information storage part 190 can, for example, contain capacitors. The information storage part 190 contains the lower electrodes 191, a capacitor insulating layer 192, and an upper electrode 193.
[0076] Each of the lower electrodes 191 is shown having a cylindrical shape. However, the shape of each of the lower electrodes 191 is not limited to a cylindrical shape, and each of the lower electrodes 191 can also have a columnar shape or an L-shape. The capacitor insulating layer 192 is formed on the lower electrodes 191. The capacitor insulating layer 192 can be formed along the profiles of the lower electrodes 191. The capacitor insulating layer 192 can be formed along the outer and inner side walls of the lower electrodes 191. The upper electrode 193 is formed on the capacitor insulating layer 192. The upper electrode 193 can cover the outer side walls of the lower electrodes 191.
[0077] The lower electrodes 191 may contain, but are not limited to, a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, or tungsten nitride), a metal (e.g., ruthenium, iridium, titanium, or tantalum), or a conductive metal oxide (e.g., iridium oxide). The capacitor insulating layer 192 may contain, among other materials, silicon oxide, silicon nitride, silicon oxynitride, a high-k material, and combinations thereof. The upper electrode 193 may, for example, contain at least one of the following: a doped semiconductor material, a metal, a conductive metal nitride, and a metal silicide.
[0078] In the edge region 24, an edge transistor PRTr can be formed. An edge insulating layer 50 can be formed around the edge transistor PRTr. The edge insulating layer 50 can include a lower edge insulating layer 52 and an upper edge insulating layer 51.
[0079] A connecting wire 165 can be arranged on the edge insulating layer 50. The connecting wire 165 can be connected to the bit line stack 140 by a bit line edge contact 166. The bit line edge contact 166 can be formed in the cell boundary region 22. The connecting wire 165 can connect the edge transistor PRTr and the bit line stack 140. The connecting wire 165 and the bit line edge contact 166 can contain at least one conductive metal nitride or a metal.
[0080] Fig. 7, Fig. 8, Fig. 9 to Fig. Figure 10 illustrates semiconductor devices according to various embodiments. To simplify the description, the main differences compared to the embodiments of the Fig. 1 to 6B described.
[0081] With reference to Fig. 7 In a semiconductor device according to embodiments, an upper conductor spacer 152 can contain a fourth upper sub-spacer 152d instead of the second upper sub-spacer 152b (see Fig. 4).
[0082] The fourth upper sub-spacer 152d can, for example, contain at least one silicon oxide, silicon oxycarbide (SiOC), silicon nitride (SiN), silicon oxynitride (SiON), and silicon oxycarbonitride (SiOCN). In the semiconductor device according to embodiments, the upper conductor spacer 152 may not contain an air spacer.
[0083] With reference to Fig. 8 In a semiconductor device according to embodiments, a bit line through-section 130_2 may possibly not contain a first conductive layer 141.
[0084] For example, a bit line stack 140 of the bit line pass-through part part 130_2 can have a structure in which a second conductive layer 142 and a third conductive layer 143 are stacked.
[0085] With reference to Fig. 9. According to the embodiments, a memory contact 120, which is arranged on a first side of a bit line contact part 130_1, may not extend into a memory connection area 103b in a semiconductor device. A memory contact 120, which is arranged on a second side of the bit line contact part 130_1 opposite the first side, may extend into a memory connection area 103b.
[0086] On the first side of the bit line contact part 130_1, an interface 120i between the memory connection area 103b and the memory contact 120 can define the outline OL of the memory connection area 103b. Fig. 4B. On the second side of the bit line contact part 130_1, a side wall of the memory connection area 103b may have a step.
[0087] With reference to Fig. 10 a semiconductor device according to embodiments may further include the aforementioned buffer patterns 131 which protrude from the side walls of a bit line through-part 130_2.
[0088] Each of the aforementioned buffer patterns 131 can be arranged on a portion of an upper surface of a memory interconnect region 103b. For example, the width of each aforementioned buffer pattern 131 in the first direction D1 (see Fig. 1) smaller than the width of each memory contact 120 in the first direction D1. For example, each of the preceding buffer patterns 131 extends into a memory contact 120, but not to a bit line contact portion 130_1. At least one portion of each preceding buffer pattern 131 can be manufactured using the same manufacturing process as the cell buffer insulating layer 107 of the Fig. 6A and Fig. 6B. The foregoing buffer patterns 131 can, for example, contain at least one of silicon oxide, silicon oxycarbide (SiOC), silicon nitride (SiN), silicon oxynitride (SiON), and silicon oxycarbonitride (SiOCN). Although each of the foregoing buffer patterns 131 is shown as a single layer, this is merely for the sake of simplicity of description, and the embodiments are not limited to this case.
[0089] Fig. 11, Fig. 12 to Fig. Figure 13 presents semiconductor devices according to various embodiments. To simplify the description, the main differences compared to the embodiments of the Fig. 1 to 6B described.
[0090] With reference to Fig. In a semiconductor device according to embodiment 11, a bit line spacer 150 can further comprise a bottom line spacer 153. A lower line spacer 151 can be arranged on the bottom line spacer 153. For example, the lower line spacer 151 can be arranged between the bottom line spacer 153 and the upper line spacer 152.
[0091] The bottom surface of a bitline structure 130 can have a curved shape because part of the bitline structure 130 extends into the memory connection areas 103b. The bottom line spacer 153 can fill a curved part of the bottom surface of the bitline structure 130. The bottom line spacer 153 can be located in a bitline pass-through section 130_2.
[0092] The bottom-connection spacer 153 can, for example, contain at least one of silicon oxide, silicon oxycarbide (SiOC), silicon nitride (SiN), silicon oxynitride (SiON), and silicon oxycarbonitride (SiOCN). Although the bottom-connection spacer 153 is shown as a single layer, this is merely for the sake of simplicity, and the embodiments are not limited to this case.
[0093] With reference to Fig. 12 In a semiconductor device according to embodiments, a lower line spacer 151 can include a first to third lower sub-spacer 151a to 151c. Each of the first to third lower sub-spacers 151a to 151c can extend continuously along a portion of each side wall of a bit line stack 140 and a bottom surface of the bit line stack 140.
[0094] The first to third lower sub-spacers 151a to 151c can be stacked sequentially on a substrate 100. In a bit line contact part 130_1, the first and second lower sub-spacers 151a and 151b can be L-shaped.
[0095] Each of the first to third lower sub-spacers 151a to 151c can, for example, contain at least one of silicon oxide, silicon oxycarbide (SiOC), silicon nitride (SiN), silicon oxynitride (SiON) and silicon oxycarbonitride (SiOCN).
[0096] Although the lower conductor spacer 151 is shown as having three lower sub-spacers, the embodiments are not limited to this case. The lower conductor spacer 151 can also include two lower sub-spacers or four or more lower sub-spacers.
[0097] With reference to Fig. 13 In a semiconductor device according to the embodiments, an upper conductor spacer 152 can include a first upper sub-spacer 152a and a fifth upper sub-spacer 152e.
[0098] The first upper sub-spacer 152a can, for example, be I-shaped. Part of the fifth upper sub-spacer 152e can be arranged between a bitline stack 140 and a bitline mask pattern 155. The fifth upper sub-spacer 152e can extend along the side walls and the upper surface of a third conductive layer 143.
[0099] The fifth upper sub-spacer 152e can extend along a portion of each of the opposite side walls of the bitline mask pattern 155. A portion of the bitline mask pattern 155 can project beyond an upper surface of the bitline spacer 150. The fifth upper sub-spacer 152e can, for example, contain at least one of silicon oxide, silicon oxycarbide (SiOC), silicon nitride (SiN), silicon oxynitride (SiON), and silicon oxycarbonitride (SiOCN).
[0100] Unlike in the drawing, the fifth upper sub-spacer 152e between the third conductive layer 143 and the first upper sub-spacer 152a may have an air gap or a seam pattern.
[0101] Fig. 14, Fig. 15 to Fig. Figure 16 illustrates semiconductor devices according to various embodiments. To simplify the description, the main differences compared to the embodiments of the Fig. 1 to 6B described.
[0102] With reference to Fig. 14 and Fig. 15 can in semiconductor devices according to the embodiments include an upper conductor spacer 152 and a sixth upper sub-spacer 152f.
[0103] The sixth upper sub-spacer 152f can be arranged on a second upper sub-spacer 152b. The sixth upper sub-spacer 152f can extend along part of a third upper sub-spacer 152c. A first upper sub-spacer 152a, the third upper sub-spacer 152c, and the sixth upper sub-spacer 152f can be arranged around the second upper sub-spacer 152b, which is an air spacer.
[0104] The sixth upper sub-spacer 152f, for example, may contain at least one of silicon oxide, silicon oxycarbide (SiOC), silicon nitride (SiN), silicon oxynitride (SiON) and silicon oxycarbonitride (SiOCN).
[0105] Since each memory contact is 120 in Fig. 14, in a cross-sectional view along the first direction D1, extends along part of the first upper sub-spacer 152a, but does not include any part extending along the sixth upper sub-spacer 152f. For example, each memory contact 120 does not laterally overlap the sixth upper sub-spacer 152f.
[0106] In Fig. Each memory contact 120 can contain a portion extending along the sixth upper sub-spacer 152f. For example, each memory contact 120 can laterally overlap the sixth upper sub-spacer 152f. A portion of each memory contact 120 can be located on an upper surface of the first upper sub-spacer 152a. A portion of each memory contact 120 that is located higher than a lower surface of the third conductive layer 143 can, for example, be T-shaped.
[0107] With reference to Fig. 16 In a semiconductor device according to embodiments, the height h12 of the lowest part of each memory contact 120 from the bottom surface of a device insulating layer 105 can be greater than the height h13 of the lowest part of a bit line pass-through part 130_2. Furthermore, the height h12 of the lowest part of each memory contact 120 from the bottom surface of the device insulating layer 105 can be greater than the height h11 of the lowest part of the bit line contact part 130_1.
[0108] Each memory contact 120 must not extend into a memory connection area 103b. An interface 120i between the memory connection area 103b and each memory contact 120 may define the outline OL of the memory connection area 103b. Fig. exhibit 4B.
[0109] Fig. Figures 17A to 34C are views illustrating the steps of a method for manufacturing a semiconductor device according to embodiments.
[0110] With reference to Fig. In 1, 2 and 17A to 17C, a device insulating layer 105 can be formed in a cell region 20 to define active regions ACT extending in the third direction D3. Several gate structures 110 extending in the first direction D1 can be formed in a substrate 100 and the device insulating layer 105.
[0111] Next, a pre-cell buffer insulating layer 107a can be formed on an edge buffer insulating layer 106, exposing the cell region 20. The pre-cell buffer insulating layer 107a can be formed over the entire surface of the substrate 100. The edge buffer insulating layer 106 and the pre-cell buffer insulating layer 107a are patterned to expose an edge region 24. An edge transistor PRTr can be formed on the exposed edge region 24. Although the pre-cell buffer insulating layer 107a is shown as a single layer, the embodiments are not limited to this case.
[0112] With reference to Fig. From 18A to 18C, an edge insulating layer 50 can be formed on the substrate 100. The edge insulating layer 50 can be formed on the entire surface of the substrate 100. The edge insulating layer 50 can cover the edge transistor PRTr.
[0113] The edge insulating layer 50 can comprise a lower edge insulating layer 52 and an upper edge insulating layer 51. After the lower edge insulating layer 52 has been formed on the substrate 100, the upper surface of the lower edge insulating layer 52 can be flattened by a planarization process. Then the upper edge insulating layer 51 can be formed. Each of the lower edge insulating layer 52 and the upper edge insulating layer 51 can, for example, contain at least one of silicon oxide, silicon oxycarbide, silicon nitride, silicon oxynitride, and silicon oxycarbonitride. Although the edge insulating layer 50 is illustrated as containing multiple layers, the embodiments are not limited to this case. The edge insulating layer 50 can also be a single layer.
[0114] With reference to Fig. 19A to 19C the edge insulating layer 50 on the cell area 20 can be structured to expose the pre-cell buffer insulating layer 107a on the cell area 20.
[0115] Next, a cell etch stop layer 53 can be formed on the substrate 100. The cell etch stop layer 53 can extend along the pre-cell buffer insulating layer 107a on the cell area 20 and the side walls and upper surface of the edge insulating layer 50.
[0116] A fence-forming layer 54 can be formed on the cell-etch stop layer 53. After the fence-forming layer 54 has been formed on the substrate 100, the cell-etch stop layer 53 can be exposed on an upper surface of the edge-insulating layer 50 by a planarization process. Each of the cell-etch stop layer 53 and the fence-forming layer 54 can contain, but are not limited to, at least one silicon nitride layer, one silicon oxynitride layer, and one silicon carbonitride layer.
[0117] With reference to Fig. In steps 20A to 20C, initial mask patterns 55 can be formed on the fence mold layer 54 and the edge insulating layer 50. The fence mold layer 54 can be textured using the initial mask patterns 55. Accordingly, fence mold patterns 54p can be formed on the cell area 20. The fence mold patterns 54p can expose the upper surfaces of the gate structures 110. While the fence mold layer 54 is being textured, a portion of the edge insulating layer 50 can also be etched. Additionally, while the fence mold layer 54 is being textured, the pre-cell buffer insulating layer 107a and the cell etch stop layer 53 can be textured to form a cell buffer insulating layer 107 and cell etch stop pattern 53p.
[0118] With reference to Fig. In 21A to 21C, fence patterns 170 extending along the gate structures 110 can be formed on the gate structures 110 using fence shape patterns 54p. Then, the fence shape patterns 54p and the first mask patterns 55 can be removed. Additionally, the cell etch stop patterns 53p formed on the cell area 20 can be removed. While the cell etch stop patterns 53p extending along an upper surface of the substrate 100 of the cell area 20 are removed, the cell etch stop patterns 53p formed on the side walls of the edge insulating layer 50 can remain without being removed.
[0119] In contrast to the case that uses Fig. As described in sections 19A to 21C, the edge insulating layer 50 can be structured to form fence patterns 170 on the gate structures 110, so that the fence patterns 170 extend along the gate structures 110.
[0120] Referring to Fig. Second mask patterns 56 can be formed on substrate 100 at 22A to 22D. These second mask patterns 56 can cover a cell boundary region 22 and the edge region 24. Furthermore, the second mask patterns 56 can be arranged in the form of columns on the cell region 20.
[0121] In Fig. 22D can simultaneously cover at least partially the ends of adjacent active areas ACT with each of its second mask patterns 56. For example, each of its second mask patterns 56 can simultaneously cover at least partially adjacent memory interconnect areas 103b. The second mask patterns 56 can be carbon mask patterns, but are not limited to them.
[0122] Part of the substrate 100 and part of the device insulating layer 105 are removed using the second mask pattern 56, forming first bit line contact recesses 130r_1. A bottom surface of each of the first bit line contact recesses 130r_1 can be defined by the device insulating layer 105 and the substrate 100.
[0123] The second mask pattern 56 can cover one or more gate structures 110 adjacent to the cell boundary region 22. Since the substrate 100 between the gate structures 110 adjacent to the cell boundary region 22 is not removed, the first bit line contact recesses 130r_1 cannot be formed therein. In contrast to the case described above, as in Fig. 27D shows that the first bit line contact recesses 130r_1 are also formed on bit line connection areas 103a using a mask pattern that has openings.
[0124] With reference to Fig. 23A and Fig. 23B, the second mask patterns 56 can be removed.
[0125] Then the cell buffer insulating layer 107 on cell area 20 can be removed. However, the cell buffer insulating layer 107 on cell boundary area 22, which is covered by the edge insulating layer 50, can remain. While the cell buffer insulating layer 107 on cell area 20 is being removed, the upper parts of the first bit line contact recesses 130r_1 are rounded off. However, the embodiments are not limited to this case.
[0126] With reference to Fig. From 24A to 24C, a buried contact layer 121 can be formed on the substrate 100. The buried contact layer 121 can fill any space between adjacent fence patterns 170. The buried contact layer 121 can fill the first bit line contact recesses 130r_1.
[0127] The buried contact layer 121 is formed to cover the fence patterns 170. The upper surfaces of the fence patterns 170 can be exposed by a planarization process. The buried contact layer 121 can contain, for example, polysilicon.
[0128] With reference to Fig. From 25A to 25C, third mask patterns 57 can be formed on the substrate 100. The buried contact layer 121 and the fence patterns 170 can be partially removed using the third mask patterns 57 to form conductor structure trenches 130t extending in the second direction D2. The conductor structure trenches 130t can intersect the gate structures 110 formed in the substrate 100. The conductor structure trenches 130t can extend to a portion of the cell boundary region 22. The conductor structure trenches 130t can pass through the first bitline contact recesses 130r_1. While the conductor structure trenches 130t are being formed, second bitline contact recesses 130r_2 can be formed in the bottom surfaces of the first bitline contact recesses 130r_1. The second bit line contact recess 130r_2 can be formed at positions that overlap the first bit line contact recesses 130r_1.Since the buried contact layer 121 is structured by the conduit structure trenches 130t, buried contact patterns 121p can be formed on the substrate 100.
[0129] In Fig. In 25C, the cell buffer insulating layer 107 and the edge buffer insulating layer 106 on the cell boundary region 22 are not removed while the conduit structure trenches 130t are formed. However, the embodiments are not limited to this case. Unlike in the drawing, the cell buffer insulating layer 107 and the edge buffer insulating layer 106 on the cell boundary region 22 can be removed while the conduit structure trenches 130t are formed. In this case, the cell buffer insulating layer 107 and the edge buffer insulating layer 106 can be removed, as shown in Fig. 6B is shown, shaped.
[0130] With reference to Fig. 26A to 26C, a pre-spacer layer 151p can be formed along the side walls and bottom surface of each 130t conduit structure trench. The pre-spacer layer 151p can extend along the upper surfaces of the third mask pattern 57.
[0131] With reference to Fig. A fourth mask pattern 58 can be formed on substrate 100 at 27A to 27D. This fourth mask pattern 58 can cover not only the cell boundary region 22 and the edge region 24, but also the cell region 20.
[0132] In Fig. 27D can contain the fourth mask pattern 58 mask openings 58op formed at positions corresponding to the bit line connection areas 103a.
[0133] The fourth mask pattern 58 can be a carbon mask pattern, but is not limited to that.
[0134] The pre-spacer layer 151p can be removed using the fourth mask pattern 58 to form a lower sub-spacer 151pp. The pre-spacer layer 151p located at positions corresponding to the mask openings 58op can be removed. The lower sub-spacer 151pp can contain bit line contact openings 150op that expose the bit line connection areas 103a of the active areas ACT. The bit line contact openings 150op can be formed at positions that overlap the second bit line contact recesses 130r_2.
[0135] With reference to Fig. From 28A to 28C, the fourth mask pattern 58 is removed.
[0136] With reference to Fig. 29A and Fig. 29B A first conductive layer 141 can be formed between parts of the lower sub-spacer 151pp. The first conductive layer 141 can fill a portion of each conductor structure trench 130t. The first conductive layer 141 can be connected to each active area ACT, e.g., to each bit line connection area 103a, via a bit line contact opening 150op.
[0137] With reference to Fig. From 30A to 30C, a portion of the lower sub-spacer 151pp can be removed to form a lower conduit spacer 151. A portion of the lower sub-spacer 151pp formed on opposite side walls of each conduit structure trench 130t and the lower sub-spacer 151pp located on the upper surfaces of the third mask pattern 57 can be removed.
[0138] With reference to Fig. 31A and Fig. 31B, a pre-upper spacer 152p can be formed on the lower conduit spacer 151 to extend along a portion of each sidewall of each conduit structure trench 130t. The pre-upper spacer 152p can include a first to third pre-upper spacer 152ap to 152cp. After the first and second pre-upper spacers 152ap and 152bp have been formed to expose an upper surface of the first conductive layer 141, the third pre-upper spacer 152cp can be formed along the sidewalls of the first and second pre-upper spacers 152ap and 152bp.
[0139] With reference to Fig. 32A to 32C, a second conductive layer 142 and a third conductive layer 143 can be formed on the first conductive layer 141. A bitline stack 140 can contain the first to third conductive layers 141 to 143. The bitline stack 140 can fill part of each conductor structure trench 130t. A bitline mask pattern 155 can be formed on the bitline stack 140 to fill the other part of each conductor structure trench 130t. The third mask pattern 57 can be removed.
[0140] Unlike in the drawings, part of the upper front spacer 152p can also be removed when the third mask patterns 57 are removed. In this case, the bit line mask patterns 155 can protrude above an upper surface of the upper front spacer 152p and the upper surfaces of the buried contact patterns 121p.
[0141] With reference to Fig. 33A and Fig. 33B The buried contact patterns 121p can be partially removed to form memory contacts 120. The buried contact patterns 121p can be partially removed to partially expose the side walls of the upper front spacer 152p.
[0142] The first and second upper sub-spacers 152ap and 152bp, which have exposed side walls, can be partially removed. Then the buried contact patterns 121p can be partially removed again to form the memory contacts 120.
[0143] With reference to Fig. 34A to 34C, a conductive pad layer can be formed to cover the memory contacts 120 and the bitline mask patterns 155, and then a pad separator layer 180 can be formed to divide the conductive pad layer into memory pads 160. To form the pad separator layer 180, the conductive pad layer and each bitline mask pattern 155 are partially removed to expose the second upper sub-spacer 152bp, and then the exposed second upper sub-spacer 152bp is removed to form an air gap. After the air gap is formed, the pad separator layer 180 can be formed to create the second upper sub-spacer 152b, which is an air spacer. Similarly, an upper line spacer 152 can be formed.
[0144] Unlike in Fig. 22A to 23B, the device insulating layer 105 can additionally be removed by a wet etching process if the side walls of the memory connection areas 103b are not exposed by the bit line contact recesses 130r_1. In this case, the resulting structure can be described as in Fig. 9 is shown, shaped.
[0145] In Fig. In 22A to 22D, only the cell buffer insulating layer 107 may be removed using the second mask pattern 56. After the second mask pattern 56 has been removed, a portion of the device insulating layer 105 can be removed. In one exemplary embodiment, the buried contact layer 121 can be formed in this state to create the resulting structure as shown in Fig. 10 can be represented, shaped.
[0146] After the entire cell buffer insulating layer 107 on cell area 20 has been removed, a portion of the device insulating layer 105 in cell area 20 can be removed. In one exemplary embodiment, the buried contact layer 121 can be formed in this state to create the resulting structure, as shown in Fig. 16 shown, can be shaped.
Claims
Semiconductor device comprising: a device insulating layer (105) formed in a substrate (100) defining a first active region (ACT) and a second active region (ACT) spaced apart in a first direction (D1); a buried contact (BC) connected to the second active region (ACT); a first bitline structure (130) arranged on the first active region (ACT) and extending in a second direction (D2) different from the first direction (D1); and a second bitline structure (130) spaced apart in the first direction (D1) from the first bitline structure (130) and arranged on the second active region (ACT), wherein: each of the first and second bitline structures (130) comprises a bitline stack (140) extending in the second direction (D2).Each of the first and second bitline structures (130) comprises a bitline contact part (130_1) and a bitline through-part (130_2) arranged alternately in the second direction (D2), the bitline contact part (130_1) of the first bitline structure (130) is located on the first active area (ACT) and electrically connected to the first active area (ACT), the bitline through-part (130_2) of the second bitline structure (130) is located on the device insulating layer (105), the height of a bottom part of the buried contact (BC) from a bottom surface of the device insulating layer (105) is less than the height of a bottom part of the bitline through-part (130_2) of the second bitline structure (130) from the bottom surface of the device insulating layer (105).the height of the lowest part of the buried contact (BC) from the bottom surface of the device insulating layer (105) is greater than the height of a lowest part of the bit line contact part (130_1) of the first bit line structure (130) from the bottom surface of the device insulating layer (105), and a lower end of the bit line through-part (130_2) of the second bit line structure (130) is buried in the second active area (ACT), wherein the bit line through-part (130_2) includes an interface (130i) that contains a first sub-interface (130ia) that meets the device insulating layer (105) and a second sub-interface (130ib) that meets the second active area (ACT), and wherein the first sub-interface (130ia) is concave. Semiconductor device according to claim 1, wherein each of the first and second bitline structure further comprises a bitline spacer (150) and a bitline mask pattern (155), wherein the bitline mask pattern (155) is arranged on the bitline stack (140), and wherein the bitline stack (140) fills a portion of a bitline trench (150t) defined by the bitline spacer (150). Semiconductor device according to claim 2, wherein in the bit line pass-through part (130_2) of the second bit line structure the bit line spacer (150) extends along opposite side walls of the bit line stack (140) and a bottom surface of the bit line stack (140), and wherein in the bit line pass-through part (130_2) of the second bit line structure the bit line spacer (150) is arranged between the second active area and the bit line stack (140). Semiconductor device according to claim 2, wherein in the bit line contact part (130_1) of the first bit line structure the bit line spacer (150) exposes the first active area. Semiconductor device according to claim 2, wherein the bit line spacer (150) comprises a lower line spacer (151) and an upper line spacer (152), and wherein the upper line spacer (152) is arranged on the lower line spacer (151) and the upper line spacer (152) comprises an air spacer. Semiconductor device according to claim 1, wherein in the bit line contact part (130_1) of the first bit line structure the bit line stack (140) has a semiconductor material pattern, a silicide pattern arranged on the semiconductor material pattern and a metallic conductive layer pattern arranged on the silicide pattern. Semiconductor device according to claim 1, wherein the second active region comprises an upper part (130b_1) that meets the buried contact and a lower part (130b_2) that does not meet the buried contact, and a portion of the upper part (130b_1) of the second active region is recessed. Semiconductor device according to claim 1, further comprising: a buffer pattern (131) projecting in the first direction from each of the opposite side walls of the bit line pass-through part (130_2) of the second bit line structure, wherein a width of the buffer pattern (131) in the first direction is less than a width of the buried contact in the first direction. Semiconductor device according to claim 1, wherein the buried contact comprises an interface (120i) which, in a cross-sectional view, meets the second active area in the first direction, the interface (120i) extends in the first direction from a first height to a second height different from the bottom surface of the device insulating layer (105), and the height of the lowest part of the bit line pass-through part (130_2) of the second bit line structure lies between the first height and the second height. Semiconductor device comprising: a device insulating layer (105) formed in a substrate (100) defining a first active region (ACT) and a second active region (ACT) spaced apart in a first direction (D1); a buried contact connected to the second active region (ACT); a first bit line structure arranged on the first active region (ACT) and extending in a second direction (D2) different from the first direction (D1); and a second bitline structure arranged on the second active area (ACT) and spaced from the first bitline structure in the first direction (D1), wherein: each of the first and second bitline structures has a bitline spacer (150), a bitline stack (140) filling a part of a bitline trench (150t) defined by the bitline spacer (150), and a bitline mask pattern (155).which is arranged on the bitline stack (140), comprises, each of the first and second bitline structures comprising a bitline contact part (130_1) and a bitline through-part (130_2) arranged alternately in the second direction (D2), the bitline contact part (130_1) of the first bitline structure being electrically connected to the first active area (ACT), a lower end of the bitline through-part (130_2) of the second bitline structure being buried in the second active area (ACT), the bitline spacer (150) comprising a lower line spacer (151) and an upper line spacer (152), the lower line spacer (151) being arranged on a part of each side wall of the bitline stack (140), and the upper line spacer (152) being arranged on the lower line spacer (151), wherein the bit line through section (130_2) contains an interface (130i) which has a first sub-interface (130ia),which meets the device insulating layer (105), and contains a second sub-interface (130ib) which meets the second active area (ACT), wherein the first sub-interface (130ia) is concave. Semiconductor device according to claim 10, wherein in the bit line pass-through part (130_2) of the second bit line structure the lower line spacer (151) extends along a bottom surface of the bit line stack (140), and wherein in the bit line pass-through part (130_2) of the second bit line structure the lower line spacer (151) is arranged between the second active area and the bit line stack (140). Semiconductor device according to claim 10, wherein in the bit line contact part (130_1) of the first bit line structure the lower line spacer (151) exposes the first active area. Semiconductor device according to claim 10, wherein the height of a lowest part of the buried contact from a bottom surface of the device insulating layer (105) is less than the height of a lowest part of the bit line through part (130_2) of the second bit line structure from the bottom surface of the device insulating layer (105), and wherein the height of the lowest part of the buried contact from the bottom surface of the device insulating layer (105) is greater than the height of a lowest part of the bit line contact part (130_1) of the first bit line structure from the bottom surface of the device insulating layer (105). Semiconductor device according to claim 10, wherein a stacked structure of the lower conductor spacer (151) differs from that of the upper conductor spacer (152). Semiconductor device according to claim 14, wherein the upper conductor spacer (152) comprises an air spacer and the lower conductor spacer (151) does not include an air spacer. Semiconductor device according to claim 10, wherein in the bit line through-part (130_2) of the second bit line structure the lower line spacer (151) comprises one or more insulating layers extending along a part of each side wall of the bit line stack (140) and a bottom surface of the bit line stack (140). Semiconductor device comprising: a device insulating layer (105) formed in a substrate (100) and defining a first active region (ACT) and a second active region (ACT) spaced apart in a first direction (D1), each of the first and second active regions (ACT) containing a pair of memory interconnect regions and an intermediate bit line interconnect region (103a); a pair of word lines extending in the first direction (D1) and arranged in the substrate (100) and the device insulating layer (105), the pair of word lines being spaced apart in a second direction (D2) different from the first direction (D1).and wherein the bitline interconnect (103a) of the first active area (ACT) and one of the pair of memory interconnects of the second active area (ACT) are arranged between the pair of word lines and spaced apart in the first direction (D1); a buried contact connected to one of the two memory interconnects; a first bitline structure extending in the second direction (D2) and arranged on the bitline interconnect (103a) of the first active area (ACT); a second bitline structure extending in the second direction (D2) and arranged on the bitline interconnect (103a) of the second active area (ACT); a landing pad located on and connected to the buried contact; and a storage capacitor located on and connected to the landing pad.wherein: each of the first and second bitline structures comprises a bitline contact part (130_1) and a bitline through-part (130_2), the bitline contact part (130_1) of each of the first and second bitline structures is electrically connected to the bitline connection area (103a) of each of the first and second active areas (ACT), the height of a lowest part of the buried contact from a bottom surface of the device insulating layer (105) is less than the height of a lowest part of the bitline through-part (130_2) of the second bitline structure from the bottom surface of the device insulating layer (105), the height of the lowest part of the buried contact from the bottom surface of the device insulating layer (105) is greater than the height of a lowest part of the bitline contact part (130_1) of the first bitline structure from the bottom surface of the device insulating layer (105) is,and a lower end of the bit line pass-through part (130_2) of the second bit line structure is buried in one of the pair of memory interconnect areas of the second active area (ACT), wherein the bit line pass-through part (130_2) contains an interface (130i) that includes a first sub-interface (130ia) that meets the device insulating layer (105) and a second sub-interface (130ib) that meets the second active area (ACT), and wherein the first sub-interface (130ia) is concave. Semiconductor device according to claim 17, wherein each of the first and second bitline structures comprises a bitline spacer (150), a bitline stack (140) filling a part of a bitline trench (150t) defined by the bitline spacer (150), and a bitline mask pattern (155) arranged on the bitline stack (140). Semiconductor device according to claim 18, wherein the bit line spacer (150) comprises a lower line spacer (151) and an upper line spacer (152), and the upper line spacer (152) is arranged on the lower line spacer (151) and comprises an air spacer. Semiconductor device according to claim 18, wherein in the bit line contact part (130_1) each of the first and the second bit line structure of the bit line stack (140) comprises a semiconductor material pattern, a silicide pattern arranged on the semiconductor material pattern and a metallic conductive layer pattern arranged on the silicide pattern.