Integrated clock gate circuit

By distributing circuit blocks across multiple rows and using multi-finger transistors, the integrated clock gate circuit achieves high-speed operation with improved power efficiency, addressing the challenges of nanoscale manufacturing limitations.

DE102020115693B4Active Publication Date: 2026-05-28SAMSUNG ELECTRONICS CO LTD
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Patent Information

Application Number
DE102020115693
Authority / Receiving Office
DE · DE
Patent Type
Patents
Current Assignee / Owner
Priority Date
2019-11-12
Filing Date
2020-06-15
Publication Date
2026-05-28
Estimated Expiration
2040-06-15

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Abstract

Integrated circuit with gate circuitry, comprising: a first control stage (110) which is configured to output a first internal signal (NET1) based on an enable signal (EN) and a clock signal (CLK); a second control stage (120) connected to the first control stage (110) via a first node (n0) and configured to output a second internal signal (NET2) based on the first internal signal (NET1) and the clock signal (CLK); and an output driver (130) configured to output a clock signal (CLK_OUT) based on the second internal signal (NET2), wherein the second control stage (120) comprises a first multi-finger transistor (MMN1) connected between a second node (n2) which outputs the second internal signal (NET2) and the first node (n0), and is configured to operate based on the clock signal (CLK), and wherein a first section of the first multi-finger transistor (MMN1) is formed in a first row (ROW1) on a semiconductor substrate between a first current line (PL1) and a second current line (PL2), and a second section of the first multi-finger transistor (MMN1) is formed in a second row (ROW2) on the semiconductor substrate between the second current line (PL2) and a third current line (PL3).
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Citation Information

Patent Citations

  • Clock gating circuit operates at high speed

    US10014862B2

  • US000010014862B2