METAL GATE STRUCTURES AND METHOD FOR MAKING THE SAME IN FIELD EFFECT TRANSISTORS

Abstract

Procedure, comprehensive: Forming a dummy gate stack (210) over a fin (204) which protrudes from a semiconductor substrate (202); Forming gate spacer elements (212) on side walls of the dummy gate stack (210); Formation of source / drain features (214) over sections of the fin (204); Forming a gate trench (220) between the gate spacer elements (212), wherein forming the gate trench (220) comprises trimming upper sections (242a) of the gate spacer elements (212) to form a funnel-shaped opening (222) in the gate trench (220); and Forming a metal gate structure (230) in the gate trench (220); further comprising: Removing an upper section of the metal gate structure (230) to form a gate recess (240); and Forming a dielectric layer (242) in the gate recess (240), wherein upper sections of the dielectric layer (242) extend laterally beyond side walls of the metal gate structure (230); furthermore comprehensive: Removing sections of the dielectric layer (242) to form a contact opening that exposes the metal gate structure (230); and Forming a gate contact (262) in the contact opening, wherein the formation of the metal gate structure (230) comprises the formation of a high k-value dielectric layer (232) over the gate spacer elements (212), the formation of an exit work metal layer (234) over the high k-value dielectric layer (232) and the formation of a bulk conductive layer (236) over the exit work metal layer (234), and wherein, to remove the upper section of the metal gate structure (230), the sections of the high k-value dielectric layer (232), the exit work metal layer (234) and the bulk conductive layer (236) are selectively removed, wherein the gate contact (262) is formed such that lower sections of the gate contact (262) extend in such a way that they contact side walls of the high k-value dielectric layer (232) and the bulk conductive layer (236).

Description

STATE OF THE ART

[0001] The semiconductor industry has experienced rapid growth. Technological advances in semiconductor materials and design have produced generations of semiconductor devices, each generation featuring smaller and more complex circuits than the previous one. As integrated circuits (ICs) have evolved, functional density (the number of interconnected components per unit area of ​​the chip) has generally increased, while geometric size (the smallest component or trace / line that can be created using a manufacturing process) has decreased. This miniaturization process typically offers benefits through increased production efficiency and a reduction in associated costs. However, these advances have also increased the complexity of processing and manufacturing semiconductor devices.

[0002] With continuously shrinking feature sizes, challenges arise in the formation of multi-layer metal gate stacks in field-effect transistors (FETs). For example, after forming at least one dielectric gate layer and one exit work metal layer in a gate trench, the remaining space in the gate trench available for a bulk-conducting layer is inevitably limited during a gate replacement process, and this can cause difficulties in depositing the bulk-conducting layer. For this reason, at least, improvements to the methods for forming metal gate stacks are desirable.

[0003] From US patent 2019 / 0305113A1, structures and fabrication methods for a semiconductor device structure are known. The semiconductor device structure comprises a gate stack over a semiconductor substrate and a cover element over the gate stack. The cover element has an upper section and a lower section, with the upper section being wider than the lower section. The semiconductor device structure also includes a spacer element over a side wall of the cover element and a side wall of the gate stack.

[0004] US Patent 2014 / 0231885A1 discloses integrated circuits and methods for fabricating integrated circuits. In an exemplary embodiment, a method for fabricating integrated circuits comprises providing a sacrificial gate structure over a semiconductor substrate. The sacrificial gate structure comprises two spacers and sacrificial gate material between the two spacers. In the method, a portion of the sacrificial gate material between the two spacers is recessed. The upper regions of the two spacers are etched using the sacrificial gate material as a mask. The method includes removing any remaining portion of the sacrificial gate material and exposing the lower regions of the two spacers. A first metal is deposited between the lower regions of the two spacers. A second metal is deposited between the upper regions of the two spacers.

[0005] From US 2017 / 0 288 031 A1 a method is known which includes forming a first gate over a substrate, wherein the first gate has first gate spacers on opposite side walls.The process further comprises forming a first hard mask layer over the first gate, forming a second hard mask layer over the first hard mask layer, wherein the second hard mask layer has a different material composition than the first hard mask layer, forming a first dielectric layer adjacent to and over the first gate, etching a first opening through the first dielectric layer to expose part of the substrate, wherein at least part of the second hard mask layer is exposed in the first opening, filling the first opening with a conductive material, and removing the second hard mask layer and the parts of the conductive material and the first dielectric layer over the first hard mask layer to form a first conductive contact in the remaining first dielectric layer.

[0006] DE 10 2015 114 904 A1 describes structures and methods for forming a semiconductor device structure. The semiconductor device structure comprises a gate stack over a semiconductor substrate and a protective element over the gate stack. One top side of the protective element is wider than one bottom side. The semiconductor device structure also includes a spacer element over a side face of the protective element and a side wall of the gate stack. The semiconductor device structure further comprises a conductive contact that is electrically connected to a conductive feature over the semiconductor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure is best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale and are for illustrative purposes only. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. 1A and Fig. Figure 1B represents a flowchart of an example method for manufacturing a semiconductor device according to various embodiments of the present disclosure. Fig. 2A is a three-dimensional perspective view of an example semiconductor device according to various embodiments of the present disclosure. Fig. 2B is a planar top view of the semiconductor device, which is located in Fig. 2A is shown, in accordance with various embodiments of the present disclosure. Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12A, Fig. 12B, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18A and Fig. 18B are cross-sectional views of sections of the or the entire semiconductor device along the path shown in the Fig. Line AA' shown in 2A and / or 2B during various intermediate stages of the process, which is described in the Fig. 1A and / or 1B is shown, in accordance with various embodiments of the present disclosure. DETAILED DESCRIPTION

[0008] The following disclosure provides many different embodiments, or examples, for implementing various features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of one feature on top of another feature, or connected and / or coupled with it, may in the present disclosure have embodiments in which the features are formed in direct contact with each other, and may also have embodiments in which additional features are formed between the features, so that the features cannot be in direct contact with each other. Furthermore, terms of spatial relationships, for example, "lower," "upper," "horizontal," "vertical," "above," "over," "below," "underneath," "upward," "downward," "above," "below," etc., as well as their derivatives (for example, adverbial forms thereof, etc.), are described below.), to simplify the present disclosure of the relationship between one feature and another feature. The terms spatial relationships are intended to cover different orientations of the device that has the features.

[0009] Furthermore, if a number or range of numbers is described herein by the use of “approximately”, “about”, and the like, the term shall include numbers within a reasonable range containing the described number, for example, within + / - 10% of the described number or other values ​​understandable to those skilled in the art. For example, the expression “approximately 5 nm” includes the dimensional range from 4.5 nm to 5.5 nm. In addition, the present disclosure may repeat reference numerals and / or symbols in the various examples. This repetition serves the purpose of simplification and clarity and does not in itself prescribe a relationship between the various embodiments and / or configurations discussed.

[0010] The present disclosure relates to semiconductor devices in general, and in particular to field-effect transistors (FETs), such as planar FETs, three-dimensional fin FETs (FinFETs), three-dimensional all-around gate FETs (GAA-FETs) and / or other types of FETs.

[0011] The ever-shrinking feature sizes in FETs present numerous challenges for the IC manufacturing process. For example, a reduced gate length, while maintaining desired functions of a metal-gate stack, can lead to a limited process window (e.g., the available space for deposition) for different material layers within the metal-gate stack. In some cases, this limited process window can result in insufficient and / or incomplete deposition of a material layer (e.g., a bulk-conducting layer), potentially leading to structural defects in the resulting FET. Although existing technologies are generally adequate to address this difficulty and other problems, they have not yet been entirely satisfactory in all aspects.

[0012] Now referring to the Fig. 1A and Fig. Figure 1B shows a flowchart of a method 100 and a method 300 for forming semiconductor devices 200 (hereinafter referred to simply as the device 200) in accordance with various aspects of the present disclosure. Additional operations may be provided before, during, and after methods 100 and 300, and some of the described operations may be substituted, omitted, or postponed for additional embodiments of the method. Methods 100 and 300 are described below in conjunction with the Fig. 3 - 18B described, which are cross-sectional views of the device 200 along the dashed line AA', which are in the Fig. 2A and Fig. Figure 2B shows intermediate steps of the process 100. The device 200 can be an intermediate device or a section thereof manufactured during the processing of an IC, which may include static random-access memory (SRAM) and / or other logic circuits, passive components such as resistors, capacitors, and inductors, and active components such as FinFETs, GAA-FETS, metal-oxide-semiconductor field-effect transistors (MOSFETS), complementary metal-oxide-semiconductor transistors (CMOS transistors), bipolar transistors, high-voltage transistors, high-frequency transistors, and / or other transistors. Although the device 200 is depicted as a three-dimensional device, the present disclosure may, for example, also provide embodiments for manufacturing planar devices.Additional features may be added to the device 200, and some of the features described below may be replaced, modified, or omitted in other embodiments of the device 200.

[0013] In process 102, procedure 100 refers to the Fig. 2A, Fig. 2B and Fig. 3 The device 200, which comprises one or more fins (or active areas) 204 projecting from a substrate 202 and separated by insulating structures 208, a dummy gate stack (or placeholder gate stack) 210 arranged above the fin 204, an interface layer 208 arranged between the dummy gate stack 210 and the fin 204, and gate spacer elements 212 arranged on side walls of the dummy gate stack 210. Although not shown, the device 200 may include further components, such as hard mask layers, barrier layers, other suitable layers, or combinations thereof, arranged above the dummy gate stack 210.

[0014] Substrate 202 can contain an elemental (single-element) semiconductor, such as silicon, germanium, and / or other suitable materials; a compound semiconductor, such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or other suitable materials. Substrate 202 can be a single-layer material with a uniform composition. Alternatively, substrate 202 can have multiple layers of material containing the same or other compositions suitable for IC device fabrication. For example, substrate 202 can be a silicon-on-insulator (SOI) substrate, which has a silicon layer formed on a silicon oxide layer.In another example, the substrate 202 can have a conductive layer, a semiconductor layer, a dielectric layer, other layers, or combinations thereof.

[0015] In some embodiments where the substrate 202 features FETs, various doped regions are arranged in or on the substrate 202. Depending on the design requirements, the doped regions can be doped with n-type dopants, such as phosphorus or arsenic, and / or p-type dopants, such as boron or BF₂. The doped regions can be formed directly on the substrate 202, in a p-well structure, an n-well structure, a double-well structure, or in a raised structure. Doped regions can be formed by implantation of dopant atoms, in-situ (on-site) doping epitaxial growth, and / or other suitable techniques. Each of the fins 204 can be suitable for providing an n-type FET or a p-type FET. In some embodiments, the fins 204, as shown herein, can be suitable for providing FETs of the same type, that is, both as type n or both as type p.Alternatively, they can be suitable for providing FETs of different types, i.e., one of type n and one of type p.

[0016] The fins 204 can be produced using suitable processes, such as photolithography and etching. The photolithography process can include forming a photoresist layer over the substrate 202, exposing the photoresist with a structure, performing post-exposure baking processes, and developing the photoresist to form a masking element (not shown) that incorporates the photoresist. The masking element is then used to etch depressions into the substrate 202, which the fins 204 leave behind. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes.

[0017] Numerous other embodiments of methods for forming the fins 204 may be suitable. For example, the fins 204 can be structured using dual or multiple structuring processes. Typically, dual and multiple structuring processes combine photolithography and self-aligning processes, thereby enabling the creation of structures that, for example, exhibit spacing dimensions smaller than those that could otherwise be achieved using a single, direct photolithography process. In one embodiment, for example, a sacrificial layer is formed over a substrate and structured using a photolithography process. Spacing elements are formed together with the structured sacrificial layer using a self-aligning process.Then the sacrificial layer is removed, and the remaining spacer elements, or mold cores, can then be used to structure the fins 204.

[0018] Referring to Fig. 2A The insulating structures 208 can contain silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a dielectric material with a low k-value, and / or other suitable materials. The insulating structures 208 can exhibit trench insulation features (STI features). In one embodiment, the insulating structures 208 are formed by etching trenches in the substrate 202 during the formation of the base fins 204c. The trenches can then be filled with one of the insulating materials described above by a deposition process, followed by a chemical-mechanical planarization (CMP) process.In another embodiment, the insulating structures 208 are formed by depositing a dielectric layer as a spacer layer over the fins 204 and subsequently recessing the dielectric layer such that an upper surface of the insulating structures 208 is arranged below an upper surface of the fins 204. Other insulating structures, such as field oxide, local oxidation of silicon (LOCOS), and / or other suitable structures, can also be implemented as the insulating structures 208. Alternatively, the insulating structures 208 can have a multilayer structure, which, for example, includes one or more thermal oxide lining layers. The insulating structures 208 can be applied by any suitable method, such as chemical vapor deposition (CVD), flowable CVD (FCVD), spin-on glass (SOG), other suitable methods, or combinations thereof.

[0019] Further referring to the Fig. 2A, Fig. 2B and Fig. In the present embodiments, the dummy gate stack 210 is arranged over the fins 204 and may contain polysilicon. Sections of the dummy gate stack 210 are replaced by a metal gate stack after the formation of other components of the device 200. The dummy gate stack 210 can be formed by a sequence of deposition and structuring processes. For example, the dummy gate stack 210 can be formed by depositing a polysilicon layer over the fins 204 and performing an anisotropic etching process (for example, a dry etching process) to remove sections of the polysilicon. In the present embodiments, the device 200 also includes the interface layer 209, which contains an oxide material, such as silicon dioxide.The interface layer 209 can be formed on the fin 204 before the polysilicon layer is applied by a suitable process, such as thermal oxidation, chemical oxidation, other suitable processes, or combinations thereof. Sections of the interface layer 209 that are not covered by the dummy gate stack 210 can then be removed by a suitable etching process. In some embodiments (not shown), the interface layer 209 is formed after the dummy gate stack 210 has been removed and before a metal gate stack (for example, a high k-value metal gate stack 230, which is discussed in detail below) is formed.

[0020] Further referring to Fig. 3. Gate spacers 212 can then be formed on the side walls of the dummy gate stack 210. The gate spacers 212 can be of a single-layer or multi-layer structure and can contain silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, other suitable materials, or combinations thereof. Each spacer layer of the gate spacers 212 can be formed by depositing a dielectric layer over the dummy gate stack 210 and subsequently removing sections of the dielectric layer in an anisotropic etching process (for example, a dry etching process), leaving sections of the dielectric layer on the side walls of the dummy gate stack 210 as the gate spacers 212.

[0021] Referring to Fig. In step 104, process 100 forms the epitaxial S / D features 214 in the fin 204 and adjacent to the dummy gate stack 210. The epitaxial S / D features 214 can be suitable for forming a p-FinFET device (which, for example, contains an epitaxial material of type p) or, alternatively, an n-FinFET device (which, for example, contains an epitaxial material of type n). The epitaxial material of type p can have one or more epitaxial layers of silicon germanium (epi-SiGe), wherein the silicon germanium is doped with a p-type dopant, such as boron, germanium, indium, and / or other p-type dopants. The epitaxial material of type n can have one or more epitaxial layers of silicon (epi-Si) or silicon-carbon (epi-SiC), wherein the silicon or silicon-carbon is doped with an n dopant, such as arsenic, phosphorus and / or other n dopants.In some embodiments, one or more epitaxy processes are performed to grow an epitaxial material in a S / D depression (not shown) formed in the fin 204 by a suitable etching process. The epitaxy process may include CVD techniques (for example, vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV CVD), low-pressure CVD (LP CVD), and / or plasma-enhanced CVD (PE CVD)), molecular beam epitaxy, other suitable SEG processes, or combinations thereof. The epitaxy process may utilize gaseous and / or liquid precursors that interact with the composition of the underlying substrate. In some embodiments, the epitaxial material is doped in situ by adding a dopant to a source material during the epitaxial growth process. In some embodiments, the epitaxial material is doped by an ion implantation process after the deposition process has been performed.In some embodiments, a tempering process is subsequently carried out to activate the dopants in the epitaxial S / D features 214.

[0022] Then, in operation 106, procedure 100 removes the dummy gate stack 210 to form a gate trench 220 between the gate spacer elements 212. Before removing the dummy gate stack 210, procedure 100 forms, with reference to Fig. 5. A dielectric intermediate layer (ILD layer) 218 ​​is deposited over the epitaxial S / D features 209 by CVD, FCVD, SOG, other suitable methods, or combinations thereof. The ILD layer 218 may contain silicon oxide, a dielectric material with a low k-value, TEOS, doped silicon oxide (for example, BPSG, FSG, PSG, BSG, etc.), other suitable dielectric materials, or combinations thereof. The process 100 may optionally form an etch stop layer (ESL) 216 over the epitaxial S / D features 214 prior to forming the ILD layer 218. The ESL 216 may contain silicon nitride, silicon oxynitride, oxygen- or carbon-doped silicon nitride, other suitable materials, or combinations thereof, and may be formed by CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), other suitable methods, or combinations thereof.The process 100 can then planarize the ILD layer 218 in one or more CMP processes to expose an upper surface of the dummy gate stack 210.

[0023] In the present embodiments, with reference to the Fig. 1B and 6-9, process 300 was carried out to remove the dummy gate stack 210 in a sequence of etching processes. In process 302, process 300 is implemented with reference to Fig. 6. An etching process 402 is used to remove an upper section of the dummy gate stack 210, thereby forming the gate trench 220. In the present embodiments, the etching process 402 removes the upper section of the dummy gate stack 210 without—or substantially without—removing the gate spacers 212, the ESL 216, and the ILD layer 218. In some embodiments, the etching process 402 opens the possibility for subsequent processing steps (for example, the trimming process 404) by creating free space for one or more etchants in which they can interact with the gate spacers 212, the ESL 216, and / or the ILD layer 218 (for example, removal by chemical reaction and / or by physical bombardment).

[0024] The etching process 402 can be any suitable etching process configured to remove the upper section of the dummy gate stack 210 anisotropically and selectively. In the present disclosure, the term "anisotropic" generally refers to an etching process that is essentially unidirectional. In the present embodiments, "anisotropic" refers to a direction of an etching process that runs essentially along a vertical height of the dummy gate stack 210, that is, along the Z-axis as shown in the present figure.In the present embodiments, a suitable etchant used during the etching process 402 includes, for example, a chlorine-containing gas (for example, Cl2, SiCl4, BCl3, other chlorine-containing gases or combinations thereof), a fluorine-containing etchant (for example, CF4, CHF3, CH3F, CH2F2, C4F8, C4F6, another fluorine-containing gas or combinations thereof), a bromine-containing etchant (for example, HBr), an oxygen-containing etchant (for example, O2), a hydrogen-containing etchant (for example, H2), an inert gas (for example, He, Ne, Ar, Kr, Xe, Rn or combinations thereof), other suitable etchants or combinations thereof. In the present embodiments, the etching agent used for the etching process 402 reacts chemically with the polysilicon material to remove the upper section of the dummy gate stack 210 (for example by oxidation).In some embodiments, etching parameters, such as power and / or bias, are controlled to ensure that the etching direction remains essentially anisotropic.

[0025] In some embodiments, the upper section removed by the etching process 402 is defined by a height H1 that is less than the total height H of the dummy gate stack 210. In other words, the present embodiments provide that the etching process 402 is tuned to partially etch the dummy gate stack 210 without completely removing it. In some embodiments, the height H1 is controlled by the duration of the etching process. In some examples, the ratio of H1 to H can be approximately 1:5 to approximately 1:2, or approximately 1:4 to approximately 1:3, and H1 can be approximately 80 angstroms. If the ratio H1 to H is less than approximately 1:5, the etching process 402 may, in some cases, fail to create enough space for the subsequent trimming process 404.On the other hand, if the ratio H1 to H is greater than approximately 1 : 2, subsequent etching processes, which include the trimming process 404 and the etching process 406, may unintentionally damage the underlying fin 204.

[0026] Referring to Fig. 7. In process 300, a trimming process 404 is performed during operation 304 to form a funnel-shaped opening 222 in the gate trench 220. In the present embodiments, the trimming process 404 is an isotropic etching process configured to remove upper sections of the gate spacers 212 (and the ESL 216), thereby widening the gate trench 220 laterally (i.e., along the X-axis) at its upper opening. In some embodiments, the trimming process 404 is configured to remove the upper sections of the gate spacers 212 (and the ESL 216) essentially without removing the remaining portion of the dummy gate stack 210. In other words, the height H1 of the gate trench 220 does not change substantially as a result of performing the trimming process 404. In some embodiments, the trimming process 404 also removes a section of the ILD layer 218, which is located near the opening of the gate trench 220.

[0027] The trimming process 404 differs from the etching process 402 in a number of aspects. For example, the term "isotropic," in contrast to the term "anisotropic" discussed above in relation to the etching process 402, generally refers to an etching process that is essentially multidirectional. In the present embodiments, the isotropic nature of the trimming process 404, in contrast to the etching process 402, allows upper sections of the gate spacer elements 212, which have been exposed by the gate trench 220, to be etched more intensely than an upper surface of the remaining section of the dummy gate stack 210. To minimize the removal of the remaining section of the dummy gate stack 210 by the trimming process 404, the method 300 further employs a dry etching agent containing one or more inert gases, such as He, Ne, Ar, Kr, Xe, Rn, or combinations thereof.In some embodiments, one or more noble gases constitute at least approximately 30% of the composition of the dry etchant used in the trimming process 404. In some embodiments, one or more noble gases constitute approximately 100% of the composition of the dry etchant, that is, the dry etchant contains no, or substantially no, non-noble gases. In the present embodiments, the dry etchant does not react, or substantially does not react, with the composition of the dummy gate stack 210; rather, the dry etchant provides high-energy ions to remove sections of the gate spacer elements 212 by particle bombardment. Thus, the dry etchant used for the trimming process 404 differs from that used for the etching process 402 (and, as discussed in detail below, for the etching process 406), which is designed to intentionally remove the dummy gate stack 210.Because the etching agent load is more concentrated near the opening of the gate trench 220, the trimming process 404 in some embodiments removes more from the gate spacer elements 212 than from the ESL 216 (and the ILD layer 218), thereby forming the funnel-shaped opening 222.

[0028] Further referring to Fig. 7 The funnel-shaped opening 222 can be characterized by an upper width W2 and a lower width W1, which is smaller than the upper width W2. The upper width W2 generally defines the lateral extent (i.e., a distance along the X-axis) of the etching resulting from the trimming process 404, and the lower width W1 defines a width of the gate trench 220 between the gate spacer elements 212. Due to the stress effect of the dry etching agent, the trimming process 404 creates an upper surface 224 of the trimmed gate spacer elements 212 and the ESL 216. In some embodiments, the upper surface 224 forms an angle α with a horizontal reference line LL' (for example, a reference line substantially parallel to the X-axis), as shown here. In other words, the upper surface 224 slopes downwards at an angle α towards the fin 204.In the present embodiments, the angle α is an acute angle and is negative due to the downward inclination of the upper surface 224 with respect to the horizontal reference line LL'. In some embodiments, the angle α is less than approximately 20°. For example, the angle α may be less than approximately 10°. In the present embodiments, the angle α is adjusted by controlling various parameters of the trimming process, such as etching preload, etching power, etching time, other suitable parameters, or combinations thereof. Increasing one or more of the aforementioned factors, for example, generally increases the angle α.

[0029] In some embodiments, the degree of inclination of the funnel-shaped opening 222 is generally proportional to the magnitude of the angle α, that is, the larger the angle α, the steeper the upper surface 224. As in Fig. As shown in Figure 7, a height difference of the funnel-shaped opening 222 can also be defined by a distance D, which, according to trigonometric relationships, is also proportional to the angle α; that is, the larger the angle α, the greater the distance D. Consequently, an increase in the angle α reduces the final gate height H' of the subsequently formed metal gate stack, which is the difference between the total height H of the dummy gate stack 210 and the distance D. Although the present embodiments do not limit the angle α to specific values, the magnitude of the angle α can be determined based on a number of factors, such as a desired steepness of the funnel-shaped opening and a desired final gate height of the metal gate stack.

[0030] Referring to Fig. In process 306, procedure 300 performs an etching process 406 to remove the remainder of the dummy gate stack 210, thereby extending the gate trench 220 downwards along the Z-axis. As shown here, in some embodiments, the etching process 406 completely removes the dummy gate stack 210 to expose the interface layer 209. In some embodiments, the etching process 406 is configured to remove the remainder of the dummy gate stack 210 anisotropically in a manner similar to etching process 402.Etching process 406 can, for example, implement a dry etching process which uses a dry etchant similar to that of etching process 402, which contains a chlorine-containing gas (for example, Cl₂, SiCl₄, BCl₃, another chlorine-containing gas, or combinations thereof), a fluorine-containing etchant (for example, CF₄, CHF₃, CH₃F, CH₂F₂, C₄F₈, C₄F₆, another fluorine-containing gas, or combinations thereof), a bromine-containing etchant (for example, HBr), an oxygen-containing etchant (for example, O₂), a hydrogen-containing etchant (for example, H₂), an inert gas (for example, He, Ne, Ar, Kr, Xe, Rn, or combinations thereof), other suitable etchants, or combinations thereof. In some embodiments, etching process 406 is carried out using etching parameters similar to those of etching process 402.In some embodiments, the etching process 406 is configured to remove a larger quantity of the dummy gate stack 210, defined by a height corresponding to the difference between H and H1, as discussed in detail above. For this purpose, the etching process 406 may employ etching parameters (for example, etching preload, etching power, etching time, etchant composition, other suitable parameters, or combinations thereof) that differ from those of the etching process 402. For example, the etching process 406 may employ a higher etching preload and / or a higher etching power than the etching process 402. Furthermore, or alternatively, the etching process 406 may employ a wet etching process using a suitable wet etchant, such as H₂O₂, NH₄OH, HCl, H₂O, other suitable wet etchants, or combinations thereof.In some embodiments, the wet etching process is designed to provide improved etch selectivity between the composition (i.e., polysilicon) of the dummy gate stack 210 and the surrounding components.

[0031] The procedure then lists 300 with reference to Fig. 9. In process 308, a cleaning process 406 of the gate trench 220 is carried out, by which any etching byproducts remaining in the gate trench are removed. In the present embodiments, the cleaning process 406 is a wet etching process configured to remove etching byproducts resulting from the etching process 402, the trimming process 404, and / or the negative etching process 406. In some embodiments, the cleaning process 406 uses a wet etching agent, such as H₂O₂, NH₄OH, HCl, H₂O, other suitable wet etching agents, or combinations thereof.

[0032] Now referring to Fig. 1A and the Fig. 10 and Fig. In process 108, method 100 subsequently forms a metal gate stack 230 in the gate trench 220. In the present embodiments, the metal gate stack 230 comprises at least one high k-value dielectric layer 232 and a metal gate electrode, which has an exit work metal layer 234 and a volume-conducting layer 236 and is arranged above the high k-value dielectric layer 232. As a result, the metal gate stack 230 is hereinafter referred to as the high k-value metal gate structure (HQM) 230.

[0033] Referring to Fig. 10. The high k-value dielectric layer 232 can contain any suitable high k-value dielectric material, such as hafnium oxide, lanthanum oxide, other suitable materials, or combinations thereof. The exit work metal layer 234 can contain any suitable metal-containing material, such as TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable exit work materials, or combinations thereof. Depending on the specific design requirements, the exit work metal layer 234 can contain a p-material or an n-material. Although not shown, additional exit work metal layers of the same and / or a different type can be formed over the exit work metal layer 234.The volume-conducting layer 236 can contain any suitable metal, such as Cu, W, Al, Co, Ru, other suitable metals, or combinations thereof. The HKMG 230 can further comprise other material layers (not shown), such as a cap layer, a barrier layer, other suitable layers, or combinations thereof. Various layers of the HKMG 230 can be deposited by any suitable process, such as ALD, CVD, PVD, plating, other suitable processes, or combinations thereof.

[0034] Further referring to Fig. 10. The high k-dielectric layer 232, the exit work metal layer 234, and the bulk conducting layer 236 (and other material layers not shown here) are formed in the gate trench 220 and above the upper surface of the ILD layer 218 and the upper surface 224 of the gate spacers 212 (and the ESL 216). The processes for forming at least the high k-dielectric layer 232 and the exit work metal layer 234 can cause material to accumulate on the upper sections of the gate spacers 212, thereby narrowing the opening of the gate trench 220 and unintentionally restricting the efficient deposition of an additional material layer in the gate trench 220.Consequently, a restricted opening can lead to incomplete deposition of the volume-conducting layer 236, which can result in the formation of defects, such as an air gap, in the volume-conducting layer and thus impair the performance of the resulting device. This defect can be particularly prevalent when the upper surface 224 of the gate spacer elements 212 is substantially aligned with the horizontal reference line LL' or slopes obliquely upwards from it (as shown in the dotted lines), such that the angle α becomes approximately 0 or positive, i.e., α ≥ 0. In such cases, a maximum width that can allow the opening of the gate trench 220 is the width W1 of the gate trench 220.Thus, any matter that accumulates at or near the opening of the gate trench will further narrow the width W2, thereby reducing the available space for the deposition of the volume-conducting layer 236. However, in the present embodiments, the trimming process 404, which is carried out in process 304, creates the funnel-shaped opening 222 (see figure 1). Fig. 7 - 9.), which is defined by the upper width W2, which is larger than the width W1 of the gate trench 220. In other words, the trimming process 404 widens the opening of the gate trench 220 laterally to accommodate several layers of material deposited in the gate trench 220 without significantly restricting the space available for the formation of the volume-conducting layer 236.

[0035] The procedure then lists 100 with reference to Fig. 11. One or more CMP processes 410 are carried out to remove any material layers that have formed on the upper surface of the ILD layer 218, thus completing the formation of the HKMG 230. As a result of the intended trimming of the gate spacers 212 (and the ESL 216), sections (indicated by the dotted circles) of the high k-dielectric layer 232 and the exit work metal layer 234, which have formed on the upper surface 224 (i.e., the upper surfaces of the gate spacers 212 and the ESL 216), remain after the execution of the CMP process 410. In other words, the high k-dielectric layer 232 and the exit work metal layer extend laterally away from the bulk conductive layer 236.

[0036] Now referring to the Fig. 12A and Fig. In process 110, method 100 removes an upper portion of the HKMG 230 in an etching process 412 to form a gate recess 240. In the present embodiments, the etching process 412 employs an etchant designed to selectively remove portions of the high k-dielectric layer 232, the exit work metal layer 234, and the bulk conducting layer 236 without, or substantially without, removing the gate spacer elements 212, the ESL 216, and the ILD layer 218. In some embodiments, the etching process 412 removes the high k-dielectric layer 232, the exit work metal layer 234, and the bulk conducting layer 236 at different rates, resulting in a gate recess 240 with an uneven bottom surface.In the present embodiments, the etching process 412 typically removes the exit work metal layer 234 at a higher rate than the high k-value dielectric layer 232 and / or the bulk conductive layer 236. Consequently, the lowest portions of the gate recess 240 are located between the high k-value dielectric layer 232 and the bulk conductive layer 236. In one embodiment, the etching process 412 is described in relation to... Fig. 12A is configured to remove the high k-value dielectric layer 232 at a similar rate to the bulk conductive layer 236, thereby creating an upper surface of the high k-value dielectric layer 232 that is substantially coplanar with an upper surface of the bulk conductive layer 236. In a further embodiment, the etching process 412 is configured with reference to Fig. 12B is configured to remove the high k-value dielectric layer 232 at a higher rate than the bulk conducting layer 236, resulting in the upper surface of the high k-value dielectric layer 232 being positioned lower than the upper surface of the bulk conducting layer 236. While both configurations are applicable to the present embodiments, the following operations of method 100 are described as an example with reference to the one described in Fig. Design shown in 12A is discussed.

[0037] Now referring to the Fig. 13 and Fig. In process 112, method 100 forms a dielectric layer 242 in the gate recess 240. Referring to Fig. In process 100, the dielectric layer 242 is formed in the gate recess 240 and above the upper surface of the ILD layer 218. The dielectric layer 242 can be deposited in the gate recess 240 by any suitable method, such as CVD, FCVD, ALD, PVD, other suitable methods, or combinations thereof. The dielectric layer 242 can contain silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, zirconium aluminum oxide, hafnium oxide, other suitable materials, or combinations thereof. In the present embodiments, the dielectric layer 242 exhibits etch selectivity with respect to the ILD layer 218, so that additional processing steps can be performed on the ILD layer 218 without significantly affecting the HKMG 230.For example, the dielectric layer 242 can be designed to provide space for the self-aligned formation of an S / D contact (not shown) in the ILD layer 218 in order to electrically couple it with the epitaxial S / D features 214.

[0038] Referring to Fig. 14 The process 100 subsequently planarizes the dielectric layer 242 in one or more CMP processes 414 to expose the upper surface of the ILD layer 218, thereby forming upper sections 242a (indicated by dotted lines) of the dielectric layer 242 on the upper surface 224. Due to the downward inclination of the upper surface 224, the upper sections 242a of the dielectric layer 242 have a substantially triangular shape, which extends laterally beyond the outermost sidewalls of the dielectric layer 242, which are defined by the gate spacer elements 212. Although not shown, in some embodiments the method 100 can continue with the formation of one or more S / D contacts in the ILD layer 218 to couple the epitaxial S / D features 214 with subsequently formed interconnect features, such as vias.

[0039] Referring to the Fig. In steps 15-18, method 100 forms a gate contact 262 during process 114 to couple the HKMG 230 with a subsequently formed interconnect feature, such as a via. Referring to Fig. In section 15, process 100 first forms an ILD layer 250 over the dielectric layer 242, wherein the ILD layer 250 can be similar to the ILD layer 218 with respect to its composition and manufacturing process, which have been discussed in detail above. Referring to Fig. In process 100, an opening 252 is formed in the ILD layer 250, wherein the opening 252 is designed to expose the HKMG 230, which is located beneath the dielectric layer 242. The opening 252 can be formed by performing a sequence of structuring and etching processes. For example, a masking element (not shown) having a photoresist layer can be formed over the ILD layer 250, wherein the masking element is exposed to radiation through a lithographic mask and subsequently developed to form a structure corresponding to the opening 252 in the masking element. Sections of the ILD layer 250 that have been exposed through the structured masking element are then removed by a suitable etching process, thereby forming the opening 252.Subsequently, the method 100 performs an etching process 416 to remove the exposed sections of the dielectric layer 242 using the structured ILD layer 250 as an etching mask. In the present embodiments, the outermost side walls of the opening 252 are defined by the gate spacer elements 212 such that the high k-value dielectric layer 232 is completely exposed. As a result, the upper sections 242a of the dielectric layer 242 remain in the device 200, since they are located outside the opening 252.

[0040] Now referring to Fig. 17. Method 100 deposits a conductive layer 260 in the opening 252 and above the ILD layer 250. The conductive layer 260 can contain any suitable metal, such as Cu, W, Al, Co, Ru, other suitable metals, or combinations thereof, and can be formed by any suitable method, such as CVD, PVD, plating, other suitable methods, or combinations thereof. Referring to Fig. In 18A, the method 100 subsequently performs one or more CMP processes 418 to planarize the conductive layer 260, thereby forming the gate contact 262. In the present embodiments, according to the invention, lower sections of the gate contact 262 extend such that they contact sidewalls of the high k-value dielectric layer 232 and the bulk conductive layer 236. As provided herein, sections of the sidewalls of the gate contact 262 further contact the ILD layer 250, the dielectric layer 242 (that is, the upper sections 242a), and the gate spacer elements 212. For comparison, Fig. 18B the device 200 in which the upper surface of the recessed dielectric layer with high k-value 232 is arranged lower than the upper surface of the recessed volume-conducting layer 236, an embodiment which corresponds to that described in Fig. 12B is shown.

[0041] Subsequently, in process 116, method 100 can perform additional processing steps on the device 200. For example, method 100 can form additional features, such as vertical interconnect features (e.g., vias), horizontal interconnect features (e.g., conductor tracks), dielectric layers (e.g., dielectric intermetal layers), other suitable features, or combinations thereof, on the device 200 to complete the manufacturing process.

[0042] For example, the present disclosure provides unclaimed methods for removing a dummy gate stack to form a gate trench, followed by the formation of a metal gate stack with improved gap-filling action within it. In some embodiments, a trimming process is performed during the removal of the dummy gate stack, in which sections of the gate spacers located on the side walls of the dummy gate stack are intentionally removed to form a downward-facing, funnel-shaped opening in the gate trench. In some embodiments, an etchant used for the trimming process is chemically inert to the dummy gate stack, so that the gate spacers are selectively removed. In some embodiments, such an etchant essentially comprises an inert gas.The funnel-shaped opening widens the gate trench opening laterally, thereby reducing unwanted material accumulation and enabling more efficient gap filling when forming different material layers of the metal gate stack. Embodiments of the disclosed methods can be readily integrated into existing processes and technologies for manufacturing FETs, such as planar FETs, FinFETs, GAA-FETs, and / or other suitable FETs.

[0043] According to the invention, the present embodiments provide a method comprising forming a dummy gate stack over a fin projecting from a semiconductor substrate, forming gate spacers on the side walls of the dummy gate stack, forming source / drain (S / D) features over sections of the fin, forming a gate trench between the gate spacers, and forming a metal gate structure in the gate trench. In the present embodiments according to the invention, forming the gate trench includes trimming upper sections of the gate spacers to form a funnel-shaped opening in the gate trench.

[0044] According to the invention, the present embodiments provide a semiconductor structure comprising a semiconductor fin projecting from a substrate, a metal gate structure arranged above the semiconductor fin, gate spacers arranged on side walls of the metal gate structure, wherein an upper surface of each of the gate spacers is inclined towards the semiconductor fin, a dielectric layer arranged above the upper surface of each of the gate spacers, and a conductive feature arranged between the gate spacers to contact the metal gate structure, wherein side walls of the conductive feature contact the dielectric layer.In some embodiments, the metal gate structure comprises a dielectric gate layer, an exit work metal layer arranged above the dielectric gate layer, and a volume conducting layer arranged above the exit work metal layer.

[0045] In yet another aspect, the present unclaimed embodiments provide a method comprising forming a placeholder gate stack over a semiconductor substrate, wherein the placeholder gate stack has spacer elements arranged on its side walls, replacing the placeholder gate stack with a metal gate stack, and forming a gate contact over the metal gate stack.In the present embodiments, replacing the placeholder gate stack comprises removing an upper section of the placeholder gate stack in a first etching process, trimming upper sections of the spacer elements at an angle in a second etching process, thereby giving the spacer elements an inclined upper surface, removing a lower section of the placeholder gate stack in a third etching process, thereby forming a gate trench between the trimmed spacer elements, and forming the metal gate stack in the gate trench.

Claims

[1] Procedure, encompassing: Forming a dummy gate stack (210) over a fin (204) which protrudes from a semiconductor substrate (202); Forming gate spacer elements (212) on side walls of the dummy gate stack (210); Formation of source / drain features (214) over sections of the fin (204); Forming a gate trench (220) between the gate spacer elements (212), wherein forming the gate trench (220) comprises trimming upper sections (242a) of the gate spacer elements (212) to form a funnel-shaped opening (222) in the gate trench (220); and Forming a metal gate structure (230) in the gate trench (220); further comprising: Removing an upper section of the metal gate structure (230) to form a gate recess (240); and Forming a dielectric layer (242) in the gate recess (240), wherein upper sections of the dielectric layer (242) extend laterally beyond side walls of the metal gate structure (230); furthermore comprehensive: Removing sections of the dielectric layer (242) to form a contact opening that exposes the metal gate structure (230); and Forming a gate contact (262) in the contact opening, wherein the formation of the metal gate structure (230) comprises the formation of a high k-value dielectric layer (232) over the gate spacer elements (212), the formation of an exit work metal layer (234) over the high k-value dielectric layer (232) and the formation of a bulk conductive layer (236) over the exit work metal layer (234), and wherein, to remove the upper section of the metal gate structure (230), the sections of the high k-value dielectric layer (232), the exit work metal layer (234) and the bulk conductive layer (236) are selectively removed, wherein the gate contact (262) is formed such that lower sections of the gate contact (262) extend in such a way that they contact side walls of the high k-value dielectric layer (232) and the bulk conductive layer (236). [2] Method according to claim 1, wherein forming the gate trench (220) comprises: Performing an initial etching process to remove an upper section of the dummy gate stack (210); Performing a trimming process to remove the upper sections of the gate spacer elements (212), thereby forming an inclined upper surface (224) in the gate spacer elements (212); and Performing a second etching process to remove a remaining section of the dummy gate stack (210), thereby forming the gate trench (220) between the trimmed gate spacer elements (212). [3] Method according to claim 2, wherein the trimming process removes the upper sections of the gate spacer elements (212), essentially without removing the dummy gate stack (210). [4] Method according to claim 3, wherein the trimming process uses an etching agent which is chemically inert towards a composition of the dummy gate stack (210). [5] Method according to claim 2, wherein the first etching process and the second etching process are carried out anisotropically, and wherein the trimming process is carried out isotropically. [6] Method according to claim 2, wherein the upper section of the dummy gate stack (210) which is removed by the first etching process has a first height (H1), and the remaining section of the dummy gate stack which is removed by the second etching process has a second height (H2), and wherein the first height (H1) is less than the second height (H2). [7] Semiconductor structure (200), comprising: a semiconductor fin (204) which protrudes from a substrate (202); a metal gate structure (230) arranged over the semiconductor fin (204), wherein the metal gate structure (230) comprises a dielectric gate layer (232), an exit work metal layer (234) arranged over the dielectric gate layer (232), and a volume conducting layer (236) arranged over the exit work metal layer (234); Gate spacer elements (212) which are arranged on side walls of the metal gate structure (230), wherein an upper surface (224) of each of the gate spacer elements (212) is inclined towards the semiconductor fin; a dielectric layer (242) which is arranged above the upper surface (224) of each of the gate spacer elements (212); and a conductive feature (262) which is arranged between the gate spacer elements (212) to contact the metal gate structure (230), wherein side walls of the conductive feature (262) contact the dielectric layer (242), wherein lower sections of the conductive feature (262) contact side walls of the dielectric gate layer (232) and the volume conductive layer (236). [8] Semiconductor structure (200) according to claim 7, wherein a lower surface of the conductive feature (262) is arranged below an upper surface of the volume conductive layer (236).

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