Semiconductor structure, semiconductor device and tempering method for its manufacture

Abstract

comprising a semiconductor structure: a fin structure (214B) over a substrate (202); vertically stacked silicon nanostructures (2080) arranged over the fin structure (214B); an insulating structure (216) arranged around the fin structure (214B); a germanium-containing interface layer (242) wound around each of the vertically stacked silicon nanostructures (2080); a gate dielectric layer (244) wound around the germanium-containing interface layer (242); a gate electrode layer (246) wound around the gate dielectric layer (244); and internal spacer features nesting the vertically stacked silicon nanostructures (2080), the germanium-containing interface layer (242) being in contact with the internal spacer features.

Description

BACKGROUND The integrated semiconductor (IC) circuit industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each generation featuring smaller and more complex circuitry than the previous one. Throughout IC evolution, functional density (i.e., the number of interconnected devices per unit area of ​​the chip) has generally increased, while geometric size (i.e., the smallest device (or trace) that can be produced by a manufacturing process) has decreased. This miniaturization process generally offers advantages by increasing production efficiency and reducing associated costs. However, this miniaturization has also led to increased complexity in the processing and manufacturing of ICs. With the advancement of integrated circuit (IC) technologies toward smaller technology nodes, multigate devices, for example, have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and mitigating short-channel effects (SCEs). A multigate device generally refers to a device with a gate structure, or a portion thereof, that extends across more than one side of a channel region. Fin-like field-effect transistors (FinFETs) and multi-bridge-channel (MBC) transistors are examples of multigate devices that have become popular and promising candidates for high-power, low-leakage-current applications.A FinFET has a raised channel that is wrapped on more than one side by a gate (the gate wraps, for example, the top and side walls of a fin made of semiconductor material that extends from a substrate). An MBC transistor has a gate structure that can partially or completely surround a channel region to allow access to the channel region on two or more sides. Because its gate structure surrounds the channel regions, an MBC transistor can also be called a surround-gate transistor (SGT) or gate-all-around transistor (GAA). The channel region of an MBC transistor can be formed from nanowires, nanosheets, or other nanostructures, and thus an MBC transistor can also be called a nanowire or nanosheet transistor. Several methods have been proposed to achieve the desired threshold voltages of P-type field-effect transistors (PFETs). In one technology, more than one P-type output metal layer can be stacked over silicon channels to achieve the desired threshold voltages. In another technology, silicon channels in P-type devices are replaced by silicon-germanium channels. However, these methods face different challenges. For the first, identifying P-type output metals to achieve the satisfactory band gap is a challenge. For the second technology, integrating silicon-germanium channels has proven difficult. Therefore, while conventional technologies for forming P-type MBC devices are generally suitable for their intended purposes, they are not satisfactory in all aspects. Prior art relating to the subject matter of the invention can be found, for example, in publications US 2019 / 0280107A1 and US 2019 / 0097023A1. The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure is best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale and are used for illustrative purposes only. In fact, the dimensions of the various features may have been enlarged or reduced as desired for the sake of clarity. Fig. 1 shows a flowchart of a method for manufacturing a semiconductor device according to one or more aspects of the present disclosure. Figs. 2-21 show fragmentary perspective views or cross-sectional views of a workpiece during a manufacturing process according to the method of Fig. 1 according to one or more aspects of the present disclosure. Fig. 22A and Fig.Figure 22B shows enlarged cross-sectional views of a nanostructure surrounded by a gate structure according to one or more aspects of the present disclosure. Figures 23 and 24 show exemplary embodiments in which a germanium sheath layer according to one or more aspects of the present disclosure is selectively implemented in one of the device regions. DETAILED DESCRIPTION The following disclosure provides many different embodiments or examples of the implementation of various features of the provided subject matter. To simplify the present disclosure, specific examples of components and arrangements are described below. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, but may also include embodiments in which additional features can be formed between the first and second features, so that the first and second features may not be in direct contact. Furthermore, reference numerals may be repeated in the various examples of the present disclosure.This repetition serves the purpose of simplicity and clarity and does not, in principle, prescribe any relationship between the various embodiments and / or configurations discussed herein. When a number or range of numbers is described with "about," "approximately," and the like, the term is further intended to include numbers that lie within a reasonable range, taking into account the variations that are inherent / intrinsic during manufacturing, as understood in the prior art. For example, the number or range of numbers includes a reasonable range including the described number, for instance, within ±10% of the described number, based on known manufacturing tolerances associated with the production of a feature that has a characteristic related to the number. For example, a material layer with a thickness of "about 5 nm" may encompass a dimensional range from 4.25 nm to 5.75 nm, where the manufacturing tolerances known to those skilled in the art in the deposition of the material layer may be ±15%.Furthermore, reference numerals may be repeated in the various examples of this disclosure. This repetition serves the purpose of simplicity and clarity and does not, in principle, prescribe any relationship between the various embodiments and / or configurations discussed. The present disclosure relates generally to multigate transistors and manufacturing processes and in particular to interface layers introducing dipoles or fixed charges. MBC transistors can be N-type or P-type. Since different types of MBC transistors require different threshold voltages, several methods for threshold voltage modulation have been proposed. For example, different output metal stacks can be implemented in gate structures for N-type and P-type MBC transistors. When the channel portion is formed from silicon, the search for a satisfactory P-type output metal is still ongoing. As another example, different channel materials are implemented in different device regions. In the first method, multiple layers of output metal must be stacked around and between closely spaced channel portions. The second method involves integrating fabrication processes for channel portions of different semiconductor compositions.In both of the example processes, the process window may be small, the performance may be less than ideal, and the manufacturing costs may be high. The present disclosure provides a method for forming a semiconductor device according to embodiments, comprising a silicon channel and a germanium cladding layer arranged on the silicon channel. In one exemplary embodiment, a germanium-containing cladding layer is deposited on the surfaces of the channel segments after channel segments are released in a channel region. A first annealing process is carried out to drive the germanium into the germanium-containing cladding layer. Consequently, at least a portion of the germanium-containing cladding is converted into a silicon-germanium layer. The annealed cladding layer is then subjected to a pre-cleaning process. The pre-cleaning process removes the germanium-rich portion of the cladding layer and oxidizes the silicon-rich portion of the cladding layer to form a germanium-containing interface layer.A gate dielectric layer is then deposited over the germanium-containing interface layer. After deposition of the gate dielectric layer, a second annealing process can be performed. It was found that when implemented in a P-type device region, the germanium-containing interface layer can provide dipoles or solid charges that result in a low threshold voltage for P-type MBC transistors. In other words, the silicon channel portions in a P-type device region can be "annealed" to achieve the desired threshold voltage. Several aspects of the present disclosure will now be described in more detail with reference to the drawings. Fig. 1 shows a flowchart of a method 100 for manufacturing a semiconductor device from a workpiece according to one or more aspects of the present disclosure. The method 100 is merely exemplary and is not intended to limit the present disclosure to what is expressly shown with reference to the method 100. Additional steps may be provided before, during, and after the method 100, and some of the described steps may be replaced, eliminated, or postponed to obtain additional embodiments of the method. For the sake of simplicity, not all steps are described in detail herein. The method 100 is described below in conjunction with Fig.2-21 described, which are fragmentary perspective views or cross-sectional views of the workpiece in various stages of manufacture according to embodiments of method 100. With reference to Fig. 1 and Fig. 2, the method 100 comprises a block 102 in which a workpiece 200 is provided. It should be noted that, depending on the context, the workpiece 200 may also be referred to as a semiconductor device 200, since the workpiece 200 is processed into a semiconductor device. The workpiece 200 may have a substrate 202. Although not explicitly shown in the drawings, the substrate 202 may have an N-type well area and a P-type well area for fabricating transistors of different conductivity types. In one embodiment, the substrate 202 may be a silicon substrate (Si substrate). In some other embodiments, the substrate 202 may contain other semiconductors such as germanium (Ge), silicon germanium (SiGe), or a III-V semiconductor material.Examples of III-V semiconductor materials include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The substrate 202 may also incorporate an insulating layer, such as a silicon oxide layer, to form a silicon-on-insulator (SOI) structure. If present, both the N-type and P-type wells are formed in the substrate 202 and exhibit a doping profile. An N-type well may have a doping profile of an N-type dopant such as phosphorus (P) or arsenic (As). A P-type tank can have a doping profile of a P-type dopant such as boron (B).The doping in the N-type and P-type wells can be formed by ion implantation or thermal diffusion and can be considered as sections of substrate 202. To avoid any doubt, the X, Y, and Z directions are perpendicular to each other. As shown in Fig. 2, the workpiece 200 further comprises a stack 204 arranged above the substrate 202. The stack 204 has several channel layers 208 nested by several sacrificial layers 206. The channel layers 208 and the sacrificial layers 206 can have different semiconductor compositions. In some implementations, the channel layers 208 are formed from silicon (Si) and the sacrificial layers 206 are formed from silicon germanium (SiGe). In these implementations, the additional germanium content in the sacrificial layers 206 allows the selective removal or recession of the sacrificial layers 206 without significant damage to the channel layers 208. In some embodiments, the sacrificial layers 206 and the channel layers 208 are epitaxial layers and can be deposited by an epitaxial process.Suitable epitaxy processes include vapor-phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. As shown in Fig. 2, the sacrificial layers 206 and the channel layers 208 are deposited alternately, one after the other, to form the stack 204. It should be noted that five (5) layers of sacrificial layers 206 and five (5) layers of channel layers 208 are arranged alternately and vertically, as shown in Fig. 2, which is for illustrative purposes only and is not intended to exceed what is expressly stated in the claims. It is conceivable that any number of sacrificial layers 206 and channel layers 208 can be formed in the stack 204. The number of layers depends on the desired number of channel parts for the device 200. In some embodiments, the number of channel layers 208 is between 2 and 10. With reference to Fig. 1 and Fig. 3, the method 100 comprises a block 104 in which a fin-shaped structure 214 is formed from the stack 204. In some embodiments, the stack 204 and a section of the substrate 202 are structured to form the fin-shaped structure 214. For the purpose of structuring, a hard mask layer 210 can be deposited over the stack 204. The hard mask layer 210 can be a single layer or a multilayer layer. In one example, the hard mask layer 210 has a silicon oxide layer 211 and a silicon nitride layer 212 over the silicon oxide layer 211. As shown in Fig. 3, the fin-shaped structure 214 extends vertically along the Z-direction from the substrate 202 and longitudinally along the Y-direction. The fin-shaped structure 214 comprises a base section 214B formed from the substrate 202 and a stack section 214S formed from the stack 204.The fin-shaped structure 214 can be structured by suitable processes, including dual or multiple structuring processes. Generally, dual or multiple structuring processes combine photolithography and self-aligning processes, enabling the creation of structures with, for example, smaller pitches than those obtainable by a single, direct photolithography process. In one embodiment, for instance, a material layer is formed over a substrate and structured by a photolithography process. Spacers are formed adjacent to the structured material layer by a self-aligning process. The material layer is then removed, and the remaining spacers or mandrels can then be used to structure the fin-shaped structure 214 by etching the stack 204 and the substrate 202.The etching process may include dry etching, wet etching, reactive ion etching (RIE) and / or other suitable processes. With reference to Fig. 1, Fig. 4, Fig. 5, and Fig. 6, the method 100 comprises a block 106 in which a dummy gate stack 224 is formed over the fin-shaped structure 214. In some embodiments, as shown in Fig. 4, following operations in block 104, an isolation feature 216 can be formed adjacent to and around the base section 214B of the fin-shaped structure 214. The isolation feature 216 is located between the fin-shaped structure 214 and another fin-shaped structure 214 (not shown). The isolation feature 216 can also be referred to as a shallow trench isolation feature (STI feature). In an exemplary process, a dielectric layer is first deposited over the workpiece 200, which fills the grooves between the fin-shaped structure 214 and an adjacent fin-shaped structure 214 with the dielectric material.In some embodiments, the dielectric layer can comprise silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and / or other suitable materials. In various examples, the dielectric layer can be deposited by a CVD process, a subatmospheric CVD process (SACVD), a flowable CVD process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, spin coating, and / or other suitable processes. The deposited dielectric material is then thinned and planarized, for example, by a chemical-mechanical polishing (CMP) process. The planarized dielectric layer is further recessed by a dry etching process, a wet etching process, and / or a combination thereof to form the insulating feature 216. As shown in Fig.As shown in Fig. 4, the stacking section 214S of the fin-shaped structure 214 extends upwards over the insulation feature 216. As shown in Fig. 4, the hard mask layer 210 can also be removed during the formation of the insulation feature 216. In some embodiments, a gate replacement process (or gate-load process) is used, in which the dummy gate stack 224 (shown in Fig. 5) serves as a placeholder for a functional gate structure. Other processes and configurations are conceivable. To form the dummy gate stack 224, a dummy dielectric layer 218, a dummy gate electrode layer 220, and an upper gate top hard mask layer 222 are deposited over the workpiece 200, as shown in Fig. 4. The deposition of these layers can involve the use of low-pressure CVD (LPCVD), CVD, plasma-enhanced CVD (PECVD), PVD, ALD, thermal oxidation, electron beam evaporation, or other suitable deposition techniques, or combinations thereof. The dummy dielectric layer 218 may contain silicon oxide, the dummy gate electrode layer 220 may contain polysilicon, and the gate top hard mask layer 222 may be a multilayer containing silicon oxide and silicon nitride.The gate-top hard mask layer 222 is structured by photolithography and etching processes. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. The etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods. Subsequently, the dielectric dummy layer 218 and the dummy gate electrode layer 220 are etched using the structured gate-top hard mask 222 as an etching mask to form the dummy gate stack 224. As shown in Fig. 5, the dummy gate stack 224 is formed above the isolation feature 216 and is arranged at least partially above the fin-shaped structures 214. As shown in Fig.As shown in Figure 5, the dummy gate stack 224 extends lengthwise along the X-direction to wrap around the fin-shaped structure 214. The section of the fin-shaped structure 214 that lies beneath the dummy gate stack 224 is a channel region 214C. The channel region 214C and the dummy gate stack 224 further define source / drain regions 214SD that are not vertically overlapped by the dummy gate stack 224. The channel region 214C is positioned between two source / drain regions 214SD. With reference to Fig. 6, operations in block 106 can include forming a gate spacer layer 226 over the top surface and sidewalls of the dummy gate stack 224. In some embodiments, forming the gate spacer layer 226 includes conformal deposition of one or more dielectric layers over the workpiece 200. In one example process, the one or more dielectric layers are deposited by CVD, SACVD, or ALD. The one or more dielectric layers can include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, and / or combinations thereof. With reference to Fig. 1 and Fig. 7, the method 100 comprises a block 108 where source / drain grooves 228 are formed in the fin-shaped structure 214. In embodiments as shown in Fig. 7, after deposition of the gate spacer layer 226, the workpiece 200 is etched by an etching process. As shown in Fig. 7, the etching process removes the gate spacer layer 226 on upward-facing surfaces of the gate-top hard mask layer 222 and leaves the source / drain regions 214SD of the fin-shaped structure 214 unmasked by the gate-top hard mask layer 222 and the gate spacer layer 226 unmasked. Removing the source / drain areas 214SD results in the source / drain grooves 228, which are defined by the gate spacer layer 226. The etching process in block 108 can be a dry etching process or a suitable etching process.A dry etching process can involve, for example, an oxygen-containing gas, hydrogen, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBR3), an iodine-containing gas, other suitable gases and / or plasmas and / or combinations thereof. As shown in Fig. 7, the sidewalls of the sacrificial layers 206 and the channel layers 208 in channel area 214C are exposed in the source / drain trenches 228. With reference to Fig. 1 and Fig. 8, the method 100 comprises a block 110 where the internal spacer features 230 are formed. In the block 110, the sacrificial layers 206, which are exposed in the source / drain channels 228, are selectively and partially recessed to form internal spacer recesses, while the exposed channel layers 208 are moderately etched. In an embodiment in which the channel layers 208 are formed substantially of silicon (Si) and the sacrificial layers 206 are formed substantially of silicon germanium (SiGe), the selective and partial recession of the sacrificial layers 206 may include a SiGe oxidation process followed by SiGe oxide removal. In these embodiments, the SiGe oxidation process may include the use of ozone (O3).In some other embodiments, the selective etching can be a selective isotropic etching process (for example, a selective dry etching process or a selective wet etching process), and the extent to which the sacrificial layers 206 are etched out is controlled by the duration of the etching process. The selective dry etching process can involve the use of one or more fluorine-based etchants, such as fluorine gas or fluorocarbons. The selective wet etching process can involve an etchant based on hydrogen fluoride (HF) or NH4OH. After the formation of the inner spacer recesses, an inner spacer material layer is deposited over the workpiece 200, including within the inner spacer recesses. The inner spacer material layer can comprise silicon oxide, silicon nitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, metal nitride, or a suitable dielectric material.The deposited inner spacer material layer is then back-etched to remove excess inner spacer material layer above the gate spacer layer 226 and the sidewalls of the channel layers 208, thereby forming the inner spacer features 230, as shown in Fig. 8. In some embodiments, the back-etching process in block 110 can be a dry etching process, which may involve the use of an oxygen-containing gas, hydrogen, nitrogen, a fluorine-containing gas (for example, CF4, SF6, CH2F2, CHF3 and / or C2F6), a chlorine-containing gas (for example, Cl2, CHCl3, CCl4 and / or BCl3), a bromine-containing gas (for example, HBr and / or CHBR3), an iodine-containing gas (for example, CF3I), other suitable gases and / or plasmas and / or combinations thereof. With reference to Fig. 1 and Fig. 9, the method 100 comprises a block 112 where the source / drain features 232 are formed in the source / drain trenches 228 (shown in Fig. 8) above the source / drain regions 214SD. In some embodiments, the source / drain features 232 can be formed by an epitaxial process such as VPE, UHV-CVD, MBE, and / or other suitable processes. The epitaxial growth process can utilize gaseous and / or liquid precursors that interact with the composition of the substrate 202 and the channel layers 208. The source / drain features 232 are thus coupled to the channel layers 208 or the released channel portions 2080 (described below). Depending on the conductivity type of the MBC transistor to be formed, the source / drain characteristics can be N-type source / drain characteristics or P-type source / drain characteristics.Examples of N-type source / drain features can be Si, GaAs, GaAsP, SiP, or another suitable material and can be doped in situ during the epitaxy process by introducing an N-type dopant such as phosphorus (P) or arsenic (As), or ex situ by using an implantation process (i.e., a transition implantation process). Examples of P-type source / drain features can be Si, Ge, AlGaAs, SiGe, boron-doped SiGe, or another suitable material, which can be doped in situ during the epitaxy process by introducing a p-type dopant such as boron (B) or ex situ by using an implantation process (i.e., a transition implantation process). In the illustrated embodiment, the source / drain features are P-type source / drain features and contain boron-doped silicon germanium (SiGe). With reference to Fig. 1, Fig. 10, and Fig. 11, the method 100 comprises a block 114 in which a contact etch stop layer (CESL) 234 and an interlayer dielectric layer (ILD layer) 236 are deposited over the workpiece 200. Fig. 10 shows a fragmentary perspective view of the workpiece 200, showing the relative position of the CESL 234 with respect to the source / drain feature 232, the gate spacer layer 226. Fig. 11 shows a fragmentary cross-sectional view of the workpiece 200 in the X-direction, along which the dummy gate stack 224 extends longitudinally. CESL 234 can contain silicon nitride, silicon oxide, silicon oxynitride, and / or other materials known in the art and can be formed by ALD, plasma-enhanced chemical vapor deposition (PECVD), and / or other suitable deposition or oxidation processes. As shown in Fig. 10 and Fig.As shown in Figure 11, CESL 234 can be deposited on the upper surfaces of the source / drain features 232 and along the sidewalls of the gate spacer layer 226. Although CESL 234 is also deposited on the upper surface of the gate spacer layer 226 and the gate top hard mask layer 222, Figures 10 and 11 only show perspective and cross-sectional views of the workpiece 200 after the gate top hard mask layer 222 has been removed by a planarization process (as described below). Block 114 further comprises the deposition of the ILD layer 236 over the CESL 234. In some embodiments, the ILD layer 236 comprises materials such as tetraethyl orthosilicate oxide (TEOS), undoped silicate glass or doped silicon oxide such as boron phosphosilicate glass (BPSG), fused silica (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG) and / or other suitable dielectric materials.The ILD layer 236 can be deposited by a PECVD process or another suitable deposition technique. In some embodiments, the workpiece 200 can be annealed after the formation of the ILD layer 236 to improve its integrity. To remove excess material and expose the top surfaces of the dummy gate stacks 224, a planarization process, such as a chemical-mechanical polishing (CMP) process, can be performed, as shown in Figures 10 and 11. The top gate hard mask layer 222 is also removed by the planarization process. With reference to Fig. 1, Fig. 12, and Fig. 13, the method 100 comprises a block 116 where the dummy gate stack 224 is removed. With reference to Fig. 12, the removal of the dummy gate stack 224 results in a gate trench 238 over the channel regions 214C. A gate structure 250 (as described below) is to be formed in a gate trench 238, as described below. The removal of the dummy gate stack 224 may include one or more etching processes that are selective for the material in the dummy gate stack 224. For example, the removal of the dummy gate stack 224 may be carried out using selective wet etching, selective dry etching, or a combination thereof. Fig. 13 shows a fragmentary cross-sectional view corresponding to Section II' in Fig. 12. Fig. 13 thus shows a cross-sectional view along the Y-direction, which is the longitudinal direction of the fin-shaped structure 214. As in Fig.As shown in Figure 13, the side walls of the channel layers 208 and sacrificial layers 206 in the channel areas 214C are exposed after the removal of the dummy gate stack 224 in the gate trench 238. Referring to Fig. 1 and Fig. 14, the method 100 comprises a block 118 where the sacrificial layers 206 in channel region 202C are selectively removed to expose the channel parts 2080. After removal of the dummy gate stack 224, block 118 of the method 100 may include operations for the selective removal of the sacrificial layers 206 between the channel layers 208 in channel regions 214C. The selective removal of the sacrificial layers 206 exposes the channel layers 208 to form channel parts 2080. Since the dimensions of the channel parts 2080 are less than 100 nm, the channel parts 2080 may also be referred to here as nanostructures. The selective removal of the sacrificial layers 206 may be carried out by selective dry etching, selective wet etching, or other selective etching processes. In some embodiments, the selective wet etching includes an APM etch (for example, an ammonia hydroxide-hydrogen peroxide-water mixture).In some embodiments, the selective removal includes SiGe oxidation followed by removal of silicon germanium oxide. For example, the oxidation can be carried out by ozone purification and subsequent removal of silicon germanium oxide by an etchant such as NH4OH. With reference to Fig. 1 and Fig. 15, the process 100 comprises a block 120 in which a cover layer 240 is formed on the channel portions 2080. In some embodiments, the cover layer 240 may contain germanium (Ge) and be deposited by CVD, ALD, or epitaxy. An example of a CVD process for forming the cover layer 240 may include precursors such as germanium (GeH₄) or digermanium (Ge₂H₆). An example of an ALD process for forming the cover layer 240 may include precursors such as dimethylgermanium dichloride (GeH₂Cl₂) and hydrogen (H₂). Examples of epitaxy processes may include VPE, UHV-CVD, and MBE. In some other embodiments, the cover layer 240 may contain not only germanium but also silicon. Similarly, such a silicon-germanium cover layer 240 may be deposited by CVD, ALD, or epitaxy.In the deposition of such a silicon-germanium shell layer 240, both germanium-containing and silicon-containing precursors can be used. Examples of germanium-containing precursors include germanium (GeH₄), digerman (Ge₂H₆), or dimethylgermanium dichloride (GeH₂Cl₂). Examples of silicon-containing precursors include silane (SiH₄), disilane (Si₂H₆), chlorosilane (SiHCl₃), or dimethylsilicon dichloride (SiH₂Cl₂). As shown in Fig. 15, the formation of the shell layer 240 can be selective for the substrate 202 and the channel portions 2080 due to the lattice mismatch. That is, the shell layer 240 can be essentially absent on the surfaces of the insulating feature 216. In some implementations, the shell layer 240 can be formed with a thickness between about 0.5 angstroms (Å) and about 5 Å. With reference to Fig. 1 and Fig. 16, the method 100 comprises a block 122 where a first annealing process 300 is carried out. The first annealing process 300 can be rapid thermal annealing (RTA), laser spike annealing, or flash annealing. The first annealing process 300 causes germanium in the cladding layer 240 to diffuse into the silicon lattice (Si lattice) of the channel parts 2080, or it causes interdiffusion between silicon (Si) in the channel parts 2080 and germanium (Ge) in the cladding layer 240. The interdiffusion of silicon and germanium can lead to an alloy of silicon and germanium, thereby forming silicon-germanium. The first annealing process 300 can therefore also be referred to as a germanium drive-in process. It should be noted that the first tempering process 300 can take place in-situ with the formation of the shell layer 240 or ex-situ after the formation of the shell layer 240.In the first case, the formation of the shell layer 240 and the first annealing process 300 take place in the same process chamber without interrupting the vacuum. In some applications, the first annealing process 300 can even alternate with the formation of the shell layer 240, and such alternating cycles gradually pump germanium into the channel sections 2080. In the latter case, the first annealing process 300 and the formation of the shell layer 240 can take place in the same process chamber or in two different process chambers. In some implementations, the first annealing process 300 may have a first annealing temperature between approximately 600°C and approximately 950°C. If the first annealing temperature is below 600°C, the diffusion of germanium may be insignificant. In this case, the first annealing temperature may refer to the peak temperature of the first annealing process 300. The first annealing process 300 may result in a germanium concentration gradient from the surface of the sheath layer 240 to the channel portions 2080. In other words, the germanium concentration is highest at the surface of the sheath layer 240 and gradually decreases with depth. Since the germanium concentration is generally inversely proportional to the etch rate in etchants or cleaning solutions, the surface portion of the sheath layer 240 with the higher germanium concentration is more susceptible to etching and cleaning.In some examples, where the sheath layer 240 is formed from germanium, the outermost section of the sheath layer 240 may remain essentially silicon-free after the first annealing process 300. The germanium concentration gradient can vary with the duration and temperature of the first annealing process 300. If the annealing temperature is low or the annealing duration is short, the germanium concentration gradient may be steep, and less germanium may diffuse into the channel portions 2080. If the annealing temperature is high or the annealing duration is long, the germanium concentration gradient may be shallower, and more germanium may diffuse deeper into the channel portions 2080. Without the first annealing process 300 for driving in the germanium, the sheath layer 240 may be substantially, if not completely, removed in the subsequent cleaning process. With reference to Fig. 1, Fig. 17, Fig. 18, Fig. 19, and Fig. 20, the method 100 comprises a block 124 in which a gate structure 250 is formed over and around the channel portions 2080. In the illustrated embodiment, the gate structure 250 is deposited in the gate grooves 238 (as shown in Fig. 12) and has an interface layer 242, a gate dielectric layer 244, and a gate electrode layer 246. In some embodiments, the channel portions 2080, together with the deposited sheath layer 240, can be subjected to a pre-cleaning process, which may include the use of RCA SC-1 (ammonia, hydrogen peroxide, and water) and / or RCA SC-2 (hydrochloric acid, hydrogen peroxide, and water). The pre-cleaning process forms an interface layer 242 from the sheath layer 240, as shown in Fig. 17.As described above, the first tempering process 300 may have transformed the shell layer 240 into a single silicon-germanium layer (SiGe layer) or an inner silicon-germanium layer (SiGe layer) and an outer germanium layer (Ge layer). It was found that pure germanium layers or germanium-rich silicon-germanium layers can be removed during the pre-cleaning process. The oxidizing agents in the pre-cleaning process can oxidize the silicon-rich silicon-germanium layer to form the interface layer 242, which may therefore contain germanium oxide, silicon-germanium oxide, or germanium-doped silicon oxide. Due to the removal of the germanium-rich layers in the shell layer 240, the silicon content in the interface layer 242 may be greater than the germanium content in the interface layer 242. Referring to Fig. 18, a gate dielectric layer 244 can be deposited over the interface layer 242 by ALD, PVD, CVD, oxidation, and / or other suitable methods. The gate dielectric layer 244 can be formed from high-k dielectric materials. As used and described herein, high-k dielectric materials include dielectric materials with a high dielectric constant, for example, greater than that of thermal silicon dioxide (about 3.9). The gate dielectric layer 244 can contain hafnium oxide.Alternatively, the gate dielectric layer 244 can contain other high-k dielectrics, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or another suitable material. As shown in Fig. 19, the operations in Block 124 may include a second annealing process 400. The second annealing process 400 may be a rapid thermal anneal (RTA), a laser spike annealing process, or a flash annealing process, and may involve an annealing temperature between about 700°C and about 1000°C.The second annealing process 400 serves to remove defects and charge carrier traps at the interface between the gate dielectric layer 244 and the interface layer 242. In some examples, the second annealing process 400 can form hafnium silicate at the interface between the gate dielectric layer 244 and the interface layer 242. As shown in Fig. 20, the gate electrode layer 246 is then deposited over the gate dielectric layer 244 by ALD, PVD, CVD, electron beam evaporation, or other suitable methods. The gate electrode layer 246 can be a single layer or, alternatively, a multilayer structure, such as various combinations of a metal layer with a selected work function to improve device performance (work function metal layer), a lining layer, a wetting layer, an adhesion layer, a metal alloy, or a metal silicide.For example, the gate electrode layer 246 may contain titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals or other suitable metallic materials or a combination thereof. If the semiconductor device has 200 N-type transistors and P-type transistors, furthermore, different gate electrode layers can be formed separately for N-type transistors and P-type transistors, which may have different metal layers (for example, to provide different N-type and P-type exit working metal layers). In block 124, the gate structure 250 (comprising the interface layer 242, the gate dielectric layer 244, and the gate electrode layer 246) is formed and deposited within the gate groove 248 (as shown in Fig. 14) over the workpiece 200 to wrap around each of the channel parts 2080. In this respect, the gate structure 250 is wrapped around each of the channel parts 2080 on the XZ plane. With reference to Fig. 1 and Fig. 21, the method 100 comprises a block 126 where further processes are carried out. Such further processes can include planarizing the workpiece 200, forming source / drain contacts, forming gate contacts, forming back-side source / drain contacts, and forming interconnect structures. Fig. 12 shows the workpiece 200 after a planarization process, e.g., after a CMP process. The planarization process can be carried out to remove excess material from both the gate dielectric layer 244 and the gate electrode layer 246, thereby providing a substantially planar top surface of the gate structure 250. To illustrate the structure of the gate 250 after operations of the process 100, the dashed area around one of the channel parts 2080 in Fig. 21 is enlarged and shown in the fragmentary cross-sectional view in Fig. 22A or Fig. 22B. The fragmentary cross-sectional views in Fig. 22A and Fig. 22B are not cross-sectional views along the Y-direction and not along the X-direction. As described above, after the first tempering process 300, the cladding layer 240 can be converted or alloyed into a silicon-germanium layer or a silicon-germanium layer lined with a germanium layer. Simultaneously, a germanium concentration gradient can be generated along the depth of the cladding layer 240. The pre-purification in block 124 can remove the germanium-rich outer part of the converted cladding layer 240 and oxidize the silicon-rich inner part of the converted cladding layer 240.Depending on how deeply the germanium penetrates into the channel parts 2080, part of the mantle layer 240 may remain behind. Referring initially to Fig. 22A, if not the entire converted cladding layer 240 is oxidized to form the interface layer 242, a portion of the cladding layer 240 may remain on the channel portion 2080. In these embodiments, the converted cladding layer 240 is wrapped around the channel portion 2080, the interface layer 242 is arranged on the remaining cladding layer 240, the gate dielectric layer 244 is arranged on the interface layer 242, and the gate electrode layer 246 is arranged on the gate dielectric layer 244. In some examples, the germanium concentration in the cladding layer 240 and the interface layer 242 may be between about 1% and about 10%, e.g., between about 3% and about 4%. It should be noted that if the portion of the cladding layer 240 has a germanium concentration greater than about 10%, it is likely to be removed.In these embodiments, the cladding layer 240 can contain silicon germanium, and the interface layer 242 can contain germanium oxide, silicon germanium oxide, or germanium-doped silicon oxide. Since the interface layer 242 contains germanium, it can be described as a germanium-containing oxide layer. Referring initially to Fig. 22B, if the entire converted cladding layer 240 is oxidized to form the interface layer 242, substantially the entire cladding layer 240 can be removed from the channel portion 2080. In these embodiments, the interface layer 242 is wound around the channel portion 2080, the gate dielectric layer 244 is wound around the interface layer 242, and the gate electrode layer 246 is wound around the gate dielectric layer 244. In some examples, the germanium concentration in the interface layer 242 can be between about 1% and about 10%, e.g., between about 3% and about 4%. It should be noted that if the portion of the cladding layer 240 has a germanium concentration greater than about 10%, it is likely to be removed during the pre-purification process. In these embodiments, the interface layer 242 can contain silicon oxide, germanium oxide, silicon germanium oxide or germanium-doped silicon oxide.Since the interface layer 242 contains germanium, the interface layer 242 can be described as a germanium-containing oxide layer. In some embodiments, as shown in Fig. 23, the cladding layer 240 is selectively implemented in P-type MBC transistors and not implemented in N-type MBC transistors. Reference is first made to Fig. 23. Fig. 23 shows a workpiece 200 having a P-type fixture area 1000 and an N-type fixture area 2000. Although not explicitly shown, the substrate 202 may have an N-type well in the P-type fixture area 1000, and the substrate 202 may have a P-type well in the N-type fixture area 2000. To perform a selective implementation of the cladding layer 240 according to method 100, a mask layer 241 may be formed in the N-type fixture area 2000 to mask the channel parts 2080 in the N-type fixture area 2000. In some embodiments, the mask layer 241 can be a photoresist layer or a bottom antireflective coating (BARC).In some examples, the BARC layer can contain silicon oxynitride, silicon oxide, a polymer, or a combination thereof, and can be deposited by CVD or ALD. If the N-type fixture area 2000 is covered by the masking layer 241, the sheathing layer 240 can be selectively deposited on the substrate 202 and the channel parts 2080 in the P-type fixture area 1000. By using method 100 and the process modification shown in Fig. 23, a P-type transistor 260 can be formed in the P-type device area 1000, and an N-type transistor 270 can be formed in the N-type device area 2000, as shown in Fig. 24. Both the P-type transistor 260 and the N-type transistor 270 are MBC transistors, each having a stack of channel parts 2080 in the channel area. The P-type transistor 260 has the P-type source / drain features 232 and the gate structure 250, which is wound around each of the channel parts 2080. The N-type transistor 270 features the N-type source / drain characteristics 2320 and a germanium-free gate structure 252 wound around each of the channel parts 2080.As described above, the P-type source / drain features 232 can contain silicon germanium (SiGe) doped with a P-type dopant such as boron (B), and the N-type source / drain features 2320 can contain silicon (Si) doped with an N-type dopant such as phosphorus (P) or arsenic (As). The formation of the P-type source / drain feature 232 and the N-type source / drain feature 2320 is omitted for brevity. As shown in Fig. 22A and Fig. 22B, the gate structure 250 can include the germanium-containing interface layer 242 and even a remnant of the cladding layer 240. Due to the absence of the mantle layer 240 during its formation process, germanium is missing in the germanium-free gate structure 252 and the germanium-free gate structure 252 has a germanium-free interface layer 243, which is essentially formed from silicon oxide.Experiments showed that the implementation of the cladding layer 240 or the formation of the germanium-containing interface layer 242 in the P-type device region 1000 can cause a shift in the work function between approximately 100 mV and approximately 250 mV, leading to a reduction in the threshold voltage of the P-type transistor 260. It is suggested that the shift in the work function is caused by dipole or fixed charge formation at or around the germanium-containing interface layer 242. Without intending any limitation, one or more embodiments of the present disclosure provide many advantages for a semiconductor device or its fabrication. For example, the present disclosure provides an embodiment comprising a P-type MBC transistor in a P-type device region and an N-type MBC transistor in an N-type device region. Both the P-type MBC transistor and the N-type MBC transistor have silicon channel portions. To provide desired threshold voltages for the P-type MBC transistor and the N-type MBC transistor, a germanium-containing cladding layer is selectively deposited over the silicon channel portions in the P-type device region, while the N-type device region is masked. The germanium in the cladding layer is driven in by an annealing process, and the cladding layer is at least partially converted into a germanium-containing interface layer.Without the cladding layer, a germanium-free interface layer is deposited in the N-type device region. The germanium-containing interface layer generates dipoles or solid charges to lower the threshold voltage of the P-type MBC transistor. In one exemplary aspect, the present disclosure relates to a semiconductor structure. The semiconductor structure comprises a fin structure over a substrate, a vertical stack of silicon nanostructures (vertically stacked silicon nanostructures) arranged over the fin structure, an insulating structure arranged around the fin structure, a germanium-containing interface layer wound around each of the vertical stacks of silicon nanostructures, a gate dielectric layer wound around the germanium-containing interface layer, and a gate electrode layer wound around the dielectric gate layer. In some embodiments, the semiconductor structure may further include a silicon-germanium layer between the germanium-containing interface layer and each of the vertical stacks of silicon nanostructures. In some embodiments, the germanium-containing interface layer comprises silicon-germanium oxide, germanium oxide, or germanium-doped silicon oxide. In some embodiments, the germanium-containing interface layer is arranged on the fin structure. In some examples, the semiconductor structure may additionally include a silicon-germanium layer between the germanium-containing interface layer and the fin structure. In some examples, the semiconductor structure may also include internal spacer features that nest the vertical stack of silicon nanostructures. The germanium-containing interface layer is in contact with the internal spacer features. In another exemplary aspect, the present disclosure relates to a semiconductor device. The semiconductor device comprises a P-type transistor and an N-type transistor. The P-type transistor comprises a first fin structure over a substrate, several first silicon nanostructures arranged over the first fin structure, a first interface layer wound around each of the several first silicon nanostructures, a gate dielectric layer wound around the first interface layer, and a gate electrode layer wound around the gate dielectric layer.The N-type transistor comprises a second fin structure above the substrate, multiple second silicon nanostructures arranged above the second fin structure, and a second interface layer wound around and in contact with each of the multiple second silicon nanostructures. The dielectric gate layer is wound around the second interface layer, and the gate electrode layer is wound around the dielectric gate layer. The composition of the first interface layer differs from the composition of the second interface layer. In some embodiments, the first interface layer contains germanium, and the second interface layer is germanium-free. In some embodiments, the semiconductor device may further include a silicon-germanium layer between the first interface layer and the multiple first silicon nanostructures. In some embodiments, the first interface layer is arranged on the first fin structure. In some examples, the multiple silicon nanostructures are composed essentially of silicon. In some embodiments, the first interface layer contains silicon-germanium oxide, germanium oxide, or germanium-doped silicon oxide, and the second interface layer contains silicon oxide. In some embodiments, the semiconductor device may further include internal spacer features that nest the multiple first silicon nanostructures. The first interface layer is in contact with the internal spacer features.In some examples, the P-type transistor also includes a P-type source / drain feature coupled to the multiple first silicon nanostructures. The P-type source / drain feature comprises silicon germanium and a P-type dopant. The N-type transistor further includes an N-type source / drain feature coupled to the multiple second silicon nanostructures, and the N-type source / drain feature contains silicon and an N-type dopant. In another exemplary aspect, the present disclosure relates to a method. The method comprises the alternating stacking of first epitaxial layers and second epitaxial layers to form a semiconductor stack over a substrate, the structuring of the semiconductor stack to form a fin, the removal of the first epitaxial layers of the fin to form nanostructures from the second epitaxial layers, the formation of a germanium-containing cladding layer wrapped around the nanostructures, the performance of a pre-purification process to convert at least a section of the germanium-containing cladding layer into a germanium-containing interface layer, the deposition of a gate dielectric layer wrapped around the germanium-containing interface layer, and the formation of a gate electrode layer over the gate dielectric layer. In some embodiments, the first epitaxial layers are formed essentially of silicon germanium, and the second epitaxial layers are formed essentially of silicon. In some embodiments, forming the germanium-containing cladding layer includes depositing the germanium-containing cladding layer onto the substrate and the nanostructure by chemical vapor deposition (CVD), atomic layer deposition (ALD), or epitaxy. In some implementations, the method may further include forming the germanium-containing cladding layer and performing a first annealing process prior to the pre-cleaning process. In some examples, the pre-cleaning process includes the use of ammonia hydroxide, hydrogen peroxide, water, or hydrochloric acid. In some embodiments, the method may further include performing a second annealing process after depositing the gate dielectric layer and prior to forming the gate electrode layer.

Claims

comprising a semiconductor structure: a fin structure (214B) over a substrate (202); vertically stacked silicon nanostructures (2080) arranged over the fin structure (214B); an insulating structure (216) arranged around the fin structure (214B); a germanium-containing interface layer (242) wound around each of the vertically stacked silicon nanostructures (2080); a gate dielectric layer (244) wound around the germanium-containing interface layer (242); a gate electrode layer (246) wound around the gate dielectric layer (244); and internal spacer features nesting the vertically stacked silicon nanostructures (2080), the germanium-containing interface layer (242) being in contact with the internal spacer features. Semiconductor structure according to claim 1, further comprising: a silicon germanium layer between the germanium-containing interface layer (242) and each of the vertical stacks of silicon nanostructures (2080). Semiconductor structure according to claim 1 or 2, wherein the germanium-containing interface layer (242) comprises silicon germanium oxide, germanium oxide or germanium-doped silicon oxide. Semiconductor structure according to one of the preceding claims, wherein the germanium-containing interface layer (242) is arranged on the fin structure (214B). Semiconductor structure according to claim 4, further comprising: a silicon germanium layer between the germanium-containing interface layer (242) and the fin structure (214B). Semiconductor device comprising: a P-type transistor comprising: - a first fin structure (214) over a substrate (202); - several first silicon nanostructures (2080) arranged over the first fin structure (214); - a first interface layer (242) wound around each of the several first silicon nanostructures (2080); - a gate dielectric layer (244) wound around the first interface layer (242); and - a gate electrode layer (246) wound around the gate dielectric layer (244); an N-type transistor comprising: - a second fin structure (214) over the substrate (202); - several second silicon nanostructures (2080) arranged over the second fin structure (214);- a second interface layer (242) that is wound around and in contact with each of the multiple second silicon nanostructures (2080), - wherein the gate dielectric layer (244) is wound around the second interface layer (242), and - wherein the gate electrode layer (246) is wound around the gate dielectric layer (244), wherein a composition of the first interface layer (242) is different from a composition of the second interface layer (242); and internal spacer features that nest the multiple first silicon nanostructures (2080), wherein the first interface layer (242) is in contact with the internal spacer features.; Semiconductor device according to claim 6, wherein the first interface layer (242) contains germanium and the second interface layer is free of germanium. Semiconductor device according to claim 6 or 7, further comprising: a silicon germanium layer between the first interface layer (242) and the several first silicon nanostructures (2080). Semiconductor device according to one of claims 6 to 8, wherein the first interface layer (242) is arranged on the first fin structure (214). Semiconductor device according to one of claims 6 to 9, wherein the multiple first silicon nanostructures (2080) are substantially formed of silicon. Semiconductor device according to one of claims 6 to 10, wherein the first interface layer (242) contains silicon germanium oxide, germanium oxide or germanium-doped silicon oxide, wherein the second interface layer (242) contains silicon oxide. Semiconductor device according to any one of claims 6 to 11, wherein the P-type transistor further comprises a P-type source / drain feature coupled to the multiple first silicon nanostructures (2080), wherein the P-type source / drain feature comprises silicon germanium and a P-type dopant, wherein the N-type transistor further comprises an N-type source / drain feature coupled to the multiple second silicon nanostructures (2080), wherein the N-type source / drain feature comprises silicon and an N-type dopant. The process comprises: alternating stacking of first epitaxial layers (206) and second epitaxial layers (208) to form a semiconductor stack (214S) over a substrate (202); structuring the semiconductor stack (214S) to form a fin (214); removing the first epitaxial layers (206) of the fin (214) to form nanostructures (2080) from the second epitaxial layers (208); forming a germanium-containing cladding layer (240) wrapped around the nanostructures (2080); performing a pre-purification process to convert at least a portion of the germanium-containing cladding layer (240) into a germanium-containing interface layer (242); depositing a gate dielectric layer (244) wrapped around the germanium-containing interface layer (242); and forming a gate electrode layer (246) over the gate dielectric layer. (244);and performing a second tempering process after the deposition of the gate dielectric layer (244) and before the formation of the gate electrode layer (246). Method according to claim 13, wherein the first epitaxial layers (206) are formed substantially from silicon germanium and the second epitaxial layers (208) are formed substantially from silicon. Method according to claim 13 or 14, wherein forming the germanium-containing mantle layer (240) comprises depositing the germanium-containing mantle layer (240) onto the substrate (202) and the nanostructure (2080) by chemical vapor deposition, CVD, atomic layer deposition, ALD, or epitaxy. Method according to one of claims 13 to 15, further comprising: carrying out a first tempering process after forming the germanium-containing jacket layer (240) and prior to the pre-cleaning process. Method according to any one of claims 13 to 16, wherein the pre-cleaning process comprises the use of ammonia hydroxide, hydrogen peroxide, water or hydrochloric acid.

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