High-voltage edge termination structure for power semiconductor devices and methods for manufacturing the same

Abstract

High-voltage edge termination structure for a power semiconductor device, comprising: a semiconductor body (110) of a first conductivity type; a JTE region (120) of a second conductivity type formed in the semiconductor body (110), wherein the JTE region (120) is adjacent to an active region (150) of the power semiconductor device; a heavily doped channel stop region (140) of the first conductivity type formed in the semiconductor body (110), wherein the heavily doped channel stop region (140) is spaced apart from the JTE region (120); and a plurality of field plates (260) designed with direct contact in the JTE area (120); wherein a field-stop extension region is adjacent to a conductive well region of the active region (150) of the power semiconductor device, and the conductive well region is electronically connected to an electrode through a heavily doped region therein; and wherein a depletable protective ring is between adjacent field plates (260) without an ohmic contact field plate.

Description

[0001] The invention relates to a semiconductor device, in particular a high-voltage edge termination structure for power semiconductor devices and a method for manufacturing the same.

[0002] Reliable power semiconductor devices require a high-voltage edge termination structure. High-voltage edge termination structures are currently presented in various forms, including field plates, floating-potential guard rings, JTE (junction termination extension), and combinations of floating-potential guard rings with field plate structures. Furthermore, combinations of these basic termination techniques are applied to the latest wide-bandgap semiconductors, such as the variably side-doped zone with decreasing concentration termination, disclosed in US Patent No. 8,564,088 B2, and the double-guard ring edge termination for SiC, disclosed in US Patent No. 9,640,609 B2.

[0003] The selection of the high-voltage edge termination structure depends on the required blocking voltage. Existing research indicates that power devices rated at 100 V and below prefer the use of a field-plate termination structure. Power devices up to 1200 V mostly use a floating-potential guard ring with a field-plate termination structure, as shown in Fig. Figure 1A shows that for all devices rated above 1200 V, such as power diodes, metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), and thyristor devices, a JTE structure or a combination of a JTE structure, a floating-potential guard ring structure, and a field-plate structure is preferred. For even higher voltages, such as 5000 V and above, chamfered termination structures are used. Fig. Figure 1A is a schematic representation showing a conventional high-voltage edge termination structure with field plates and protective rings at floating potential.

[0004] The three critical concerns regarding the implementation of a high-voltage edge termination structure include: (1) the process steps required to implement the high-voltage edge termination structure; (2) the area required to implement the high-voltage edge termination structure; and (3) the reliability against surface charge (Qss) variations. When the surface charge changes (primarily when the positive charge fluctuates), the surface charge in the termination area broadly affects the depletion region for a given blocking bias. For example, if the surface charge is high, the depletion thickness in the termination area shrinks, which can lead to an increase in the electric field to critical values, causing device failure at a lower applied voltage.

[0005] Among the various conventional high-voltage junction termination structures, the JTE high-voltage junction termination structure requires the smallest area for implementation. However, the JTE structure is significantly sensitive to surface charge variations. To improve the surface charge tolerance of the JTE structure, Temple and colleagues proposed a multi-zone junction termination extension (MZ-JTE) structure, as described in Fig. Figure 1B shows that the MZ-JTE structure, however, requires a larger or additional area for implementation.

[0006] Known structures are described in US 2006 / 0 113 613 A1, in CN 106 409 884 B, in US 2014 / 0 353 678 A1, in DE 10 2018 123 596 A1, and in DE 11 2018 002 359 T5.

[0007] The invention is based on the objective of creating a high-voltage edge termination structure that increases the tolerance to surface charge with minimal area enlargement in order to implement new HV termination structures.

[0008] The invention provides a high-voltage edge termination structure for a power semiconductor device, comprising a semiconductor body of a first conductivity type, a JTE region of a second conductivity type, a heavily doped channel stop region of the first conductivity type, and multiple field plates. The JTE region is formed within the semiconductor body and is adjacent to an active region of the power semiconductor device. The heavily doped channel stop region is formed within the semiconductor body and is spaced apart from the JTE region. The plurality of field plates is formed within the JTE region.

[0009] According to the invention, the first conductivity type is n-conductivity, while the second conductivity type is p-conductivity.

[0010] According to the invention, the field plates are made of a metal material.

[0011] According to the invention, the field plates are made of p-conducting polysilicon.

[0012] According to the invention, the field plates are made of n-conducting polysilicon.

[0013] According to the invention, a high-voltage edge termination structure for a power semiconductor device is provided, comprising a semiconductor body of a first conductive conductivity type, a JTE region of a second conductive conductivity type, a heavily doped channel stop region of the first conductive conductivity type, and multiple depletable guard rings of the second conductive conductivity type. The JTE region is formed within the semiconductor body, being adjacent to an active region of the power semiconductor device. The heavily doped channel stop region is formed within the semiconductor body, being spaced apart from the JTE region. The plurality of depletable guard rings of the second conductive conductivity type is formed within the semiconductor body, being located between the JTE region and the heavily doped channel stop region.

[0014] According to the invention, the first conductivity type is n-conductivity, while the second conductivity type is p-conductivity.

[0015] According to the invention, a high-voltage edge termination structure for a power semiconductor device is provided, comprising a semiconductor body of a first conductivity type, a JTE region of a second conductivity type, multiple lightly doped regions of the second conductivity type, and a heavily doped channel stop region of the first conductivity type. The JTE region is formed within the semiconductor body, being adjacent to an active region of the power semiconductor device. The plurality of lightly doped regions are formed within the JTE region adjacent to an upper surface of the JTE region. The heavily doped channel stop region is formed within the semiconductor body, being spaced apart from the JTE region.

[0016] According to the invention, the first conductivity type is n-conductivity, while the second conductivity type is p-conductivity.

[0017] According to the invention, the lateral width of the p-conducting, weakly doped regions increases in the direction of the n-conducting, heavily doped channel stop region.

[0018] According to the invention, the distance between the weakly doped area near the active area and the active area is greater than the distance between any two adjacent weakly doped areas.

[0019] According to the invention, the high-voltage edge termination structure further comprises a plurality of field plates formed in the p-type JTE region. According to the invention, the field plates are made of a metallic material. According to the invention, the field plates (260) are made of p-type polysilicon. According to the invention, the field plates are made of n-type polysilicon.

[0020] According to the invention, a high-voltage edge termination structure for a power semiconductor device is provided, comprising a semiconductor body of a first conductivity type, a JTE region of a second conductivity type, a heavily doped channel stop region of the first conductivity type, multiple depletable guard rings of the second conductivity type, and a plurality of lightly doped regions of the second conductivity type. The JTE region is formed within the semiconductor body, being adjacent to an active region of the power semiconductor device. The heavily doped channel stop region is formed within the semiconductor body, being spaced apart from the JTE region. The plurality of depletable guard rings is formed within the semiconductor body, being located between the JTE region and the heavily doped channel stop region.The multitude of weakly doped areas is formed in an upper section of the JTE area and at least one of the depletable protective rings.

[0021] According to the invention, the first conductivity type is n-conductivity, while the second conductivity type is p-conductivity.

[0022] According to the invention, the lateral width of the p-conducting, weakly doped regions increases in the direction of the n-conducting, heavily doped channel stop region.

[0023] According to the invention, the distance between the weakly doped region near the active region and the active region is greater than the distance between any two adjacent, p-conducting, weakly doped regions.

[0024] According to the invention, the gap between the depletable protective rings increases in the direction of the heavily doped channel stop area.

[0025] According to the invention, the high-voltage edge termination structure further comprises a plurality of field plates formed in the JTE region. According to the invention, the field plates are made of a metallic material. According to the invention, the field plates are made of p-type polysilicon. According to the invention, the field plates are made of n-type polysilicon.

[0026] According to the invention, a method for manufacturing a high-voltage edge termination structure for a power semiconductor device is provided, comprising the following steps: Formation of a heavily doped channel stop region of a first conductivity type in a semiconductor body of the first conductivity type by ion implantation of the first conductivity type; Forming a JTE region of a second conductivity type in the semiconductor body by ion implantation of the second conductivity type, wherein the JTE region is adjacent to an active region of the power semiconductor device and spaced apart from the heavily doped channel stop region; and Forming a plurality of field plates in the JTE range.

[0027] According to the invention, a method for manufacturing a high-voltage edge termination structure for a power semiconductor device is provided, comprising the following steps: Formation of a heavily doped channel stop region of a first conductivity type in a semiconductor body of the first conductivity type by ion implantation of the first conductivity type; Forming a JTE region of a second conductivity type in the semiconductor body by ion implantation of the second conductivity type, wherein the JTE region is adjacent to an active region of the power semiconductor device and spaced apart from the heavily doped channel stop region; and Forming a plurality of depletable guarding rings of the second conductivity type in the semiconductor body by ion implantation of the second conductivity type, wherein the depletable guarding rings are formed between the JTE region and the heavily doped channel stop region.

[0028] According to the invention, the JTE area and the depletable protective rings are formed simultaneously in the semiconductor body.

[0029] According to the invention, a method for manufacturing a high-voltage edge termination structure for a power semiconductor device is provided, comprising the following steps: Formation of a heavily doped channel stop region of a first conductivity type in a semiconductor body of the first conductivity type by ion implantation of the first conductivity type; Forming a JTE region of a second conductivity type in the semiconductor body by ion implantation of the second conductivity type, wherein the JTE region is adjacent to an active region of the power semiconductor device and spaced apart from the heavily doped channel stop region; and Formation of a plurality of weakly doped areas of the second conductivity type in the JTE region next to an upper surface of the JTE region by ion implantation of the first conductivity type.

[0030] According to the invention, the method further comprises the formation of a plurality of field plates in the JTE range.

[0031] According to the invention, a method for manufacturing a high-voltage edge termination structure for a power semiconductor device is provided, comprising the following steps: Formation of a heavily doped channel stop region of a first conductivity type in a semiconductor body of the first conductivity type by ion implantation of the first conductivity type; Forming a JTE region of a second conductivity type and a plurality of depletable guard rings of the second conductivity type in the semiconductor body by ion implantation of the second conductivity type, wherein the JTE region is adjacent to an active region of the power semiconductor device and spaced apart from the heavily doped channel stop region, and wherein the depletable guard rings are formed between the JTE region and the heavily doped channel stop region; and Formation of a plurality of weakly doped areas of the second conductivity type in an upper section of the JTE region and the depletable protective rings by ion implantation of the first conductivity type.

[0032] According to the invention, the method further comprises the formation of a plurality of field plates in the JTE range.

[0033] The invention and its embodiments are explained in more detail below with reference to the drawing. The drawing shows: Fig. 1A a schematic representation of a conventional high-voltage edge termination structure with a field plate and floating protective rings; Fig. 1B a perspective view of a conventional high-voltage edge termination structure with MZ-JTE (Multi-Zone Junction Termination Extension) structure; Fig. 2 a schematic representation of a high-voltage edge termination structure with a laterally modulated JTE structure provided according to a first embodiment of the present invention; Fig. 2A a simulated potential distribution contour of a silicon-based high-voltage edge termination structure, which is a laterally modulated JTE structure at a bias voltage of 1300 V with a surface charge of 5e 10 Cm -2 exhibits; Fig. 2B a simulated potential distribution contour of a silicon-based high-voltage edge termination structure, which is a laterally modulated JTE structure at a bias voltage of 1250 V with a surface charge of 5e 11 Cm -2 exhibits; Fig. 2C a diagram of the surface potential of a silicon-based high-voltage edge termination structure, which is a laterally modulated JTE structure at a bias of 1300 V with a surface charge of 5e10 Cm -2 exhibits; Fig. 2D a diagram of the surface potential of a silicon-based high-voltage edge termination structure, which is a laterally modulated JTE structure at a bias of 1250 V with a surface charge of 5e 11 Cm -2 exhibits; Fig. 3 a schematic representation of a high-voltage edge termination structure comprising a JTE structure with field plates provided according to a second embodiment of the present invention; Fig. 4 a schematic representation of a high-voltage edge termination structure comprising a JTE structure with depletable protective rings provided according to a third embodiment of the present invention; Fig. 4A a simulated potential distribution contour of a silicon-based high-voltage edge termination structure, which is a JTE structure with depletable guard rings and field plates at a bias voltage of 630 V with a surface charge of 5e 10 Cm -2 exhibits; Fig. 4B a simulated potential distribution contour of a silicon-based high-voltage edge termination structure, which is a JTE structure with depletable guard rings and field plates at a bias voltage of 630 V with a surface charge of 5e 11 Cm -2 exhibits; Fig. 4C a diagram of the surface potential of a silicon-based high-voltage edge termination structure, which is a JTE structure with depletable guard rings and the field plates at a bias voltage of 630 V with a surface charge of 5e 10 Cm -2 exhibits; Fig. 4D a diagram of the surface potential of a silicon-based high-voltage edge termination structure, which is a JTE structure with depletable guard rings and the field plates at a bias voltage of 630 V with a surface charge of 5e 11 Cm -2 exhibits; Fig. 5 a schematic representation of a high-voltage edge termination structure comprising a JTE structure with depletable protective rings and the field plates provided according to a fourth embodiment of the present invention; Fig. 6 a schematic representation of a high-voltage edge termination structure comprising a JTE structure with depletable protective rings and the field plates provided according to a fifth embodiment of the present invention; Fig. Figures 7A to 7G are schematic representations of a method for manufacturing a high-voltage edge termination structure comprising a JTE structure with depletable protective rings and the field plates provided according to an embodiment of the present invention; and Fig. Figures 8A to 8G are schematic representations of a method for manufacturing a high-voltage edge termination structure having a laterally modulated JTE structure, provided according to an embodiment of the present invention.

[0034] Although the following detailed description contains many specific details for illustrative purposes, any person skilled in the art will recognize that many variations and modifications of the following details are within the scope of the invention. Accordingly, the exemplary embodiments of the invention described below are set forth without loss of generality for the claims and without limitation thereto. For illustrative purposes, an n-type device is described below. A p-type device can be fabricated using a similar method, but with opposite conductivity types.

[0035] It should be noted that the surface charges Qss in the termination region can influence the depletion region for the given blocking bias. To avoid the aforementioned problem, a high-voltage edge termination structure according to the embodiments of the present invention is provided, in which the shrinkage of the depletion propagation and reduced peak electric field fluctuations in the termination region can be minimized for cases with low and high surface charge, thereby improving the tolerance to surface charge fluctuations.

[0036] With reference to Fig. 2 describes a high-voltage edge termination structure with a laterally modulated JTE structure provided according to a first embodiment of the present invention.

[0037] As in Fig. As shown in Figure 2, the high-voltage edge termination structure 100 has an n-type semiconductor body 110, a p-type JTE region 120, several p-type, lightly doped regions 130a to 130h and an n-type, heavily doped channel stop region 140.

[0038] There is an n-type semiconductor layer 112 with a doping concentration higher than that of the n-type semiconductor body 110. The n-type semiconductor layer 112 is formed on a base surface of the n-type semiconductor body 110. The n-type semiconductor layer 112 is used to reduce the contact resistance between the n-type semiconductor body 110 and a cathode electrode 114 of the power semiconductor device.

[0039] The p-type JTE region 120 is formed in the upper section of the n-type semiconductor body 110. The p-type JTE region 120 borders an active region 150 of the power semiconductor device and extends from the active region 150 to the edge. More precisely, the p-type JTE region 120 extends from a p-type well 151 of the active region 150 to the edge of the power semiconductor device. The p-type well 151 is electrically connected to an anode electrode 154 via a p-type, heavily doped region 152.

[0040] According to an embodiment of the present invention, the p-conducting JTE region 120 can have a constant depth, wherein the depth of the p-conducting JTE region 120 can be equal to or greater than the depth of the p-conducting trough 151.

[0041] The p-type, weakly doped regions 130a to 130h are formed in the upper section of the p-type JTE region 120, i.e., in the section near the upper surface of the p-type JTE region 120. These p-type, weakly doped regions 130a to 130h are spaced apart from each other.

[0042] The n-type, heavily doped channel stop region 140 is formed in the upper portion of the n-type semiconductor body 110. The n-type, heavily doped channel stop region 140 is located outside the p-type JTE region 120, which is used to limit the depletion region at the outer edge of the power semiconductor device when the power semiconductor device is reverse biased. In the present embodiment, a metal layer is formed on the n-type, heavily doped channel stop region 140. However, the metal layer on the n-type, heavily doped channel stop region 140 can be omitted in some embodiments.

[0043] The p-type JTE region 120 and the p-type, lightly doped regions 130a to 130h located within it form a p-type, laterally modulated JTE region. The n-type, heavily doped channel stop region 140 is separated from the p-type JTE region 120 by an n-type region or a surface section of the n-type semiconductor body 110. That is, a lateral termination structure extending from the active region 150 to the edge is formed, comprising the p-type, laterally modulated JTE region, the n-type region, and the n-type, heavily doped channel stop region 140. The p-type, laterally modulated JTE region exhibits the structure with the alternating "P" and "P-" regions near the upper surface of the semiconductor body.

[0044] The p-type, laterally modulated JTE region features a p-type JTE region of uniform depth and several alternating "P" and "P-" regions in its upper part to propagate depletion. This allows the p-type, laterally modulated JTE region to control the tip surface electric field without significantly affecting the breakdown voltage. In other words, the p-type, laterally modulated JTE region can minimize the reduction in the reverse-biased breakdown voltage due to surface charge fluctuations.

[0045] The number, lateral width, and spacing of the p-type, lightly doped regions 130a to 130h within the p-type JTE region 120 are adjustable to optimize the trade-off between blocking capability and surface charge tolerance. As shown in Fig. As further shown in Figure 2, according to a preferred embodiment of the present invention, the lateral width of the p-type, lightly doped regions 130a to 130h increases in the direction of the n-type, heavily doped channel stop region 140. The distance between the p-type, lightly doped region 130a near the active region 150 and the active region 150 is greater than the distance between any two adjacent p-type, lightly doped regions 130b to 130h. With doping modulation in the p-type JTE region 120, a reduction in the depletion extent in the direction of the n-type, heavily doped channel stop region 140 can lead to a deeper depletion extent in the p-type JTE region 120 in the direction of the active region 150. Embodiments of the present invention are not limited to the present configuration.The variation of the lateral width of the p-conducting, lightly doped regions 130a to 130h and the arrangement of the p-conducting, lightly doped regions 130a to 130h in the p-conducting JTE region 120 can be adjusted according to the actual state and should not be considered as deviating from the scope of the present invention.

[0046] To better understand the effect of the laterally modulated JTE structure described above, reference is made to the Fig. References are 2A to 2D. Fig. Figure 2A shows a simulated potential distribution contour of a silicon-based high-voltage edge termination structure, which features a laterally modulated JTE structure at a bias voltage of 1300 V with a surface charge of 5e 10 Cm -2 exhibits. Fig. Figure 2B shows a simulated potential distribution contour of a silicon-based high-voltage edge termination structure, which features a laterally modulated JTE structure at a bias voltage of 1250 V with a surface charge of 5e 11 Cm -2 exhibits. Fig. Figure 2C shows a diagram of the surface potential of a silicon-based high-voltage edge termination structure, which is a laterally modulated JTE structure at a bias of 1300 V with a surface charge of 5e 10 Cm -2 exhibits. Fig. Figure 2D shows a diagram of the surface potential of a silicon-based high-voltage edge termination structure, which features a laterally modulated JTE structure at a bias of 1250 V with a surface charge of 5e 11 Cm -2 exhibits.

[0047] In the high-voltage edge termination structure with a laterally modulated JTE structure, it has been shown that a constant depth of the p-type JTE region is used for simulation. This region is modulated by phosphorus implanted via mask windows of varying sizes. The size of the phosphorus implant windows increases, and the distance between them decreases, to enhance the doping modulation along the direction from the active region to the n-type, heavily doped channel stop region, i.e., the chip edge. The phosphorus compensation implant modulates the doping concentration of the p-type JTE region to form the laterally modulated JTE region.

[0048] As in Fig. As shown in 2A, this leads to the following in the case of a small positive surface charge, i.e., Qss of 5e 10 Cm -2 , leading to a depletion extension from the n-conducting, heavily doped channel stop region to the surface region of the p-conducting JTE region. As in Fig. 2A shows that in the case of a high positive surface charge, i.e., Qss of 5e 11 Cm -2 The depletion extent from the p-type JTE region towards the n-type channel stop region has shrunk. However, due to the doping modulation in the p-type JTE region, a shrinkage of the depletion extent towards the n-type channel stop region leads to the depletion extending deeper into the p-type JTE region towards the active region.

[0049] As from the Fig. 2C and Fig. As can be seen in the 2D simulation, the results show a uniform surface potential distribution at bias voltages of 1300 V and 1250 V, respectively, for both low and high surface charge cases. Therefore, the laterally modulated JTE structure provided according to the embodiment of the present invention can effectively prevent the power component from failing at lower voltages. In practice, the high-voltage edge termination structure with a laterally modulated JTE structure can achieve a breakdown voltage exceeding 1200 V for both low and high surface charge cases.

[0050] With reference to Fig. 3 describes a high-voltage edge termination structure with a JTE structure with field plates provided according to a second embodiment of the present invention.

[0051] As in Fig. As shown in Figure 3, the high-voltage edge termination structure 200 comprises an n-type semiconductor body 210, a p-type JTE region 220, an n-type, heavily doped channel stop region 240, and a plurality of field plates 260. Three field plates 260 are shown in the drawing.

[0052] There is an n-type semiconductor layer 212 with a doping concentration higher than that of the n-type semiconductor body 210. The n-type semiconductor layer 212 is formed on a base surface of the n-type semiconductor body 210. The n-type semiconductor layer 212 is used to reduce the contact resistance between the n-type semiconductor body 210 and a cathode electrode 214 of the power semiconductor device.

[0053] The p-type JTE region 220 is located in the upper section of the n-type semiconductor body 210, or in a section near its upper surface. The p-type JTE region 220 borders an active region 250 of the power semiconductor device and extends from the active region 150 to the edge. More precisely, the p-type JTE region 220 extends from a p-type well 251 of the active region 250 to the edge of the power semiconductor device. The p-type well 251 is electrically connected to an anode electrode 254 via a p-type, heavily doped region 252.

[0054] The n-type, heavily doped channel stop region 240 is formed in the upper portion of the n-type semiconductor body 210. The n-type, heavily doped channel stop region 240 is located outside the p-type JTE region 220, which is used to limit the depletion region at the outer edge of the power semiconductor device when the power semiconductor device is reverse biased. The n-type, heavily doped channel stop region 240 is spaced from the p-type JTE region 220 by an n-type region or surface section of the n-type semiconductor body 210. That is, a lateral termination structure is formed comprising the p-type JTE region 220, the n-type region, and the n-type, heavily doped channel stop region 240. In the present embodiment, a metal layer is formed on the n-conducting, heavily doped channel stop region 240.However, the metal layer on the n-conducting, heavily doped channel stop region 240 can be omitted in some embodiments.

[0055] The field plates 260 are formed in the p-type JTE region 220. The field plates 260 in the p-type JTE region 220 can distribute the electric field generated by the surface charge, so that the reduction of the reverse breakdown voltage due to fluctuations in the surface charge is minimized.

[0056] In one embodiment of the present invention, the field plates 260 can be made of a metallic material to form a Schottky contact with the p-type JTE region 220. In another embodiment of the present invention, the field plates 260 can be made of a p-type polysilicon material to form an ohmic contact with the p-type JTE region 220. In yet another embodiment of the present invention, the field plates 260 can be made of an n-type polysilicon material to form a pn junction with the p-type JTE region 220.

[0057] With reference to Fig. 4 describes a high-voltage edge termination structure with a JTE structure with depletable protective rings and field plates, which are provided according to a third embodiment of the present invention.

[0058] As in Fig. Figure 4 shows that the high-voltage edge termination structure 300 according to the invention comprises an n-type semiconductor body 310, a p-type JTE region 320, an n-type, heavily doped channel stop region 340, a plurality of field plates 360, and a plurality of p-type depletable guard rings 370. Three field plates 360 and four p-type depletable guard rings 370 are shown in the drawing.

[0059] There is an n-type semiconductor layer 312 with a doping concentration higher than that of the n-type semiconductor body 310. The n-type semiconductor layer 312 is formed on a base surface of the n-type semiconductor body 310. The n-type semiconductor layer 312 is used to reduce the contact resistance between the n-type semiconductor body 310 and a cathode electrode 314 of the power semiconductor device.

[0060] The p-type JTE region 320 is formed in the upper section of the n-type semiconductor body 310. The p-type JTE region 320 borders an active region 350 of the power semiconductor device. More precisely, the p-type JTE region 320 borders a p-type well 351 of the active region 350 of the power semiconductor device. The p-type well 351 is electrically connected to an anode electrode 354 via a p-type, heavily doped region 352.

[0061] The n-type, heavily doped channel stop region 340 is formed in the upper portion of the n-type semiconductor body 310. The n-type, heavily doped channel stop region 340 is located outside the p-type JTE region 320, which is used to limit the depletion region at the outer edge of the power semiconductor device when the power semiconductor device is reverse biased. The n-type, heavily doped channel stop region 340 is spaced from the p-type JTE region 320 by an n-type region or surface portion of the n-type semiconductor body 310. In the present embodiment, a metal layer is formed on the n-type, heavily doped channel stop region 340. However, the metal layer on the n-type, heavily doped channel stop region 340 can be omitted in some embodiments.

[0062] The p-type depletable guard rings 370 are formed in the upper section of the n-type semiconductor body 310. Furthermore, the p-type depletable guard rings 370 are located between the p-type JTE region 320 and the n-type, heavily doped channel stop region 340. The p-type depletable guard rings 370 are electrically floating. When a high bias voltage is applied, the p-type depletable guard ring 370 depletes to create a charge-balanced region for depletion expansion in the n-type area between the p-type JTE region 320 and the n-type, heavily doped channel stop region 340. This is beneficial for the expansion of the electric field generated by surface charge, minimizing the reduction of the reverse breakdown voltage due to surface charge fluctuations.

[0063] The field plates 360 are formed in the p-conducting JTE area 320 and the p-conducting depletable protective rings 370. The field plates 360 ensure the expansion of the electric field generated by surface charge in order to minimize the reduction of the reverse breakdown voltage due to fluctuations in surface charge.

[0064] To better understand the effect of the above-depletable protective rings 370, the field plates 360 and the JTE structure, reference is made to the Fig. 4A to 4D referred. Fig. Figure 4A shows a simulated potential distribution contour of a silicon-based high-voltage edge termination structure, which is a JTE structure with depletable guard rings and field plates at a bias voltage of 630 V with a surface charge of 5e 10 Cm -2 exhibits. Fig. Figure 4B shows a simulated potential distribution contour of a silicon-based high-voltage edge termination structure, which is a JTE structure with depletable guard rings and field plates at a bias voltage of 630 V with a surface charge of 5e 11 Cm -2 exhibits. Fig. Figure 4C shows a diagram of the surface potential of a silicon-based high-voltage edge termination structure, which is a JTE structure with depletable guard rings (370) and the field plates (360) at a bias voltage of 630 V with a surface charge of 5e 10 Cm -2 exhibits. Fig. Figure 4D shows a diagram of the surface potential of a silicon-based high-voltage edge termination structure, which is a JTE structure with depletable guard rings (370) and the field plates (360) at a bias voltage of 630 V with a surface charge of 5e 11 Cm -2 exhibits.

[0065] The high-voltage edge termination structure with a p-type JTE region exhibits a constant depth, five p-type depletable guard rings 370 arranged between the p-type JTE region and the n-type channel stop region, and two field plates 360 used for simulation.

[0066] It will be on Fig. 4A and Fig. 4B is referenced. In the case of a high surface charge Qss of 5e 11 Cm -2 compared to a low surface charge Qss of 5e 10 Cm -2The depletion spreads more into the p-type JTE region and less into the n-type region between the p-type depletable guard ring and the n-type, heavily doped channel stop region 340. The field plates on the p-type depletable guard rings 370 ensure that the depletion region in the n-type region between the p-type depletable guard ring 370 and the n-type, heavily doped channel stop region 340 extends towards the chip edge to prevent a deterioration of the breakdown voltage.

[0067] As from the Fig. 4C and Fig. As can be seen in the 4D model, the simulation results show a uniform surface potential distribution at a bias voltage of 630 V for both low and high surface charge cases. Therefore, the high-voltage edge termination structure provided according to the embodiment of the present invention, with a JTE structure featuring depletable protective rings and field plates, can effectively prevent the power device from failing at lower voltages. In practice, the high-voltage edge termination structure with a JTE structure featuring depletable protective rings and field plates can achieve a breakdown voltage exceeding 600 V for both low and high surface charge cases.

[0068] Both the in Fig. 3 High-voltage edge termination structures shown with a JTE structure with depletable protective rings and field plates, as well as those in Fig. The four high-voltage edge termination structures shown, comprising a JTE structure with depletable guard rings and field plates, operate on the same principle by counteracting the shrinkage of the depletion region in cases with high surface charge, in order to achieve the required breakdown voltage through the termination structure of a power device. The field plate can assume the potential of the p-type region. The field plate is in contact with, for example, the p-type JTE region or the p-type depletable guard ring, regardless of the type of electrical contact formed between the field plate and the p-type region. These field plates, with a potential determined by the p-type region in contact with them, reduce the increase in the electric surface field as the surface charge increases by distributing the surface potential over a longer depletion region.

[0069] The field plates and the depletable protective rings in conjunction with the in the Fig. 3 and Fig. The JTE structures shown in the four diagrams can be used for power components up to 600 V. The use of the field plates and the depletable protective rings in conjunction with the [unclear] Fig. 5 and Fig. The laterally modulated JTE structure shown in Figure 6 can provide additional capability to minimize breakdown reduction with increasing surface charge for power devices with a breakdown voltage of approximately 1200 V or higher.

[0070] With reference to Fig. 5 describes a high-voltage edge termination structure with a laterally modulated JTE structure with depletable protective rings and field plates, which is provided according to a fourth embodiment of the present invention.

[0071] As in Fig. As shown in Figure 5, the high-voltage edge termination structure 400 comprises an n-type semiconductor body 410, a p-type JTE region 420, several p-type, lightly doped regions 430a to 430e, an n-type, heavily doped channel stop region 440, several field plates 460, and several p-type depletable guard rings 470. The drawing shows three field plates 460 and four p-type depletable guard rings 470.

[0072] There is an n-type semiconductor layer 412 with a doping concentration higher than that of the n-type semiconductor body 410. The n-type semiconductor layer 412 is formed on a base surface of the n-type semiconductor body 410. The n-type semiconductor layer 412 is used to reduce the contact resistance between the n-type semiconductor body 410 and a cathode electrode 414 of the power semiconductor device.

[0073] The p-type JTE region 420 is formed in the upper section of the n-type semiconductor body 410. The p-type JTE region 420 borders an active region 450 of the power semiconductor device. More precisely, the p-type JTE region 420 borders a p-type well 451 of the active region 450 of the power semiconductor device. The p-type well 451 is electrically connected to an anode electrode 454 via a p-type, heavily doped region 452.

[0074] The n-type, heavily doped channel stop region 440 is formed in the upper portion of the n-type semiconductor body 410. The n-type, heavily doped channel stop region 440 is located outside the p-type JTE region 420, which is used to limit the depletion region at the outer edge of the power semiconductor device when the power semiconductor device is reverse biased. In the present embodiment, a metal layer is formed on the n-type, heavily doped channel stop region 440. However, the metal layer on the n-type, heavily doped channel stop region 440 can be omitted in some embodiments.

[0075] Some of the p-type, lightly doped regions, i.e., the p-type, lightly doped region 430a, are formed in the upper part of the p-type JTE region 420. The p-type JTE region 420 and the p-type, lightly doped region 430a within it form a p-type, laterally modulated JTE region.

[0076] The p-type depletable guard rings 470 are formed in the upper section of the n-type semiconductor body 410. Furthermore, the p-type depletable guard rings 470 are located between the p-type JTE region 420 and the n-type, heavily doped channel stop region 440. The p-type depletable guard rings 470 are electrically floating. When a high bias voltage is applied, the p-type depletable guard ring 470 depletes to create a charge-balanced region for depletion expansion in the n-type area between the p-type JTE region 420 and the n-type, heavily doped channel stop region 440. This is beneficial for the expansion of the electric field generated by surface charge, minimizing the reduction of the reverse breakdown voltage due to surface charge fluctuations.

[0077] The p-type, lightly doped regions 430a to 430e are located in the upper section of the p-type JTE region 420 and the p-type depletable guard rings 470 for modulating the p-type JTE region 420 and the p-type depletable guard rings 470. As shown, the p-type, lightly doped region 430a is located in the upper section of the p-type JTE region 420, with the p-type, lightly doped regions 430b to 430e being located in the respective p-type depletable guard rings 470. These p-type, lightly doped regions 430a to 430e are spaced apart from each other.As shown, a lateral termination structure is formed with the p-conducting, laterally modulated JTE region, the p-conducting depletable guard rings 470, the n-conducting region part of the upper section of the n-conducting semiconductor body and the n-conducting, heavily doped channel stop region 440 extending from the active region 450 to the edge.

[0078] The field plates 460 are formed on the p-type JTE region 420 and the p-type depletable guard rings 470. The field plates 460 can propagate the electric field generated by the surface charge in order to minimize the reduction of the reverse breakdown voltage due to surface charge fluctuations. In one embodiment of the present invention, the field plates 460 can be made of a metallic material to form a Schottky contact with the p-type region, i.e., the p-type JTE region 420 or the p-type depletable guard ring 470. In another embodiment of the present invention, the field plates 460 can be made of a p-type polysilicon material to form an ohmic contact with the p-type region.In one embodiment of the present invention, the field plates 460 can be made of an n-conducting polysilicon material to form a pn junction with the p-conducting region.

[0079] As mentioned above, the p-type, laterally modulated JTE region exhibits a structure with multiple "P" and "P-" regions, which mitigate the reverse breakdown voltage due to surface charge variations. The field plates and depletable guard rings counteract the shrinkage of the depletion region in cases of high surface charge, ensuring the required breakdown voltage through the termination structure of a power device.

[0080] With reference to Fig. Section 6 describes a high-voltage edge termination structure with a laterally modulated JTE structure with field plates, which is provided according to a fifth embodiment of the present invention.

[0081] As in Fig. Figure 6 shows that the high-voltage edge termination structure 500 according to the invention comprises an n-type semiconductor body 510, a p-type JTE region 520, a plurality of p-type, lightly doped regions 530a to 530h, an n-type, heavily doped channel stop region 540, and a plurality of field plates 560. Three field plates 560 are shown in the drawing.

[0082] There is an n-type semiconductor layer 512 with a doping concentration higher than that of the n-type semiconductor body 510. The n-type semiconductor layer 512 is formed on a base surface of the n-type semiconductor body 510. The n-type semiconductor layer 512 is used to reduce the contact resistance between the n-type semiconductor body 510 and a cathode electrode 514 of the power semiconductor device.

[0083] The p-type JTE region 520 is formed in the upper section of the n-type semiconductor body 510. The p-type JTE region 520 borders an active region 550 of the power semiconductor device and extends from the active region 550 to the edge. More precisely, the p-type JTE region 520 borders a p-type well 551 of the active region 550 of the power semiconductor device. The p-type well 551 is electrically connected to an anode electrode 554 via a p-type, heavily doped region 552.

[0084] The p-type, lightly doped regions 530a to 530h are formed in the upper section of the p-type JTE region 520, i.e., in the section near the upper surface of the p-type JTE region 520. These p-type, lightly doped regions 530a to 530h are spaced apart from each other.

[0085] The n-type, heavily doped channel stop region 540 is formed in the upper portion of the n-type semiconductor body 510. The n-type, heavily doped channel stop region 540 is located outside the p-type JTE region 520, which is used to limit the depletion region at the outer edge of the power semiconductor device when the power semiconductor device is reverse biased. In the present embodiment, a metal layer is formed on the n-type, heavily doped channel stop region 540. However, the metal layer on the n-type, heavily doped channel stop region 540 can be omitted in some embodiments.

[0086] The p-type JTE region 520 and the p-type, lightly doped regions 530a to 530h located within it form a p-type, laterally modulated JTE region. The n-type, heavily doped channel stop region 540 is separated from the p-type JTE region 520 by an n-type region or a surface section of the n-type semiconductor body 510. This means that a lateral termination structure is formed with the p-type, laterally modulated JTE region, the n-type region, and the n-type, heavily doped channel stop region 140. The p-type, laterally modulated JTE region exhibits the structure with the alternating "P" and "P-" regions near the upper surface of the semiconductor body to spread the depletion. Thus, the p-type, laterally modulated JTE region can minimize the reduction of the reverse breakdown voltage due to surface charge fluctuations.

[0087] Similar to the one in Fig. In the embodiment shown in Figure 2, according to a preferred embodiment of the present invention, the lateral width of the p-type, lightly doped regions 530a to 530h is increased in the direction of the n-type, heavily doped channel stop region 540. The distance between the p-type, lightly doped region 530a near the active region 550 and the active region 550 itself is greater than the distance between any two adjacent p-type, lightly doped regions 530b to 530h. With doping modulation in the p-type JTE region 520, a reduction in the depletion extent in the direction of the n-type, heavily doped channel stop region 540 can lead to a deeper depletion extent in the p-type JTE region 520 in the direction of the active region 550. Embodiments of the present invention are not limited to the present configuration.The variation of the lateral width of the p-conducting, lightly doped regions 530a to 530h and the arrangement of the p-conducting, lightly doped regions 530a to 530h in the p-conducting JTE region 520 can be adjusted according to the actual state and should not be considered as deviating from the scope of the present invention.

[0088] The field plates 560 are designed in the p-type JTE region 520. The field plates 560 can counteract the shrinkage of the depletion region in cases with high surface charge, in order to achieve the required breakdown voltage through the termination structure of a power device. That is, the field plates 560 are also helpful in minimizing the reduction of the reverse-biased breakdown voltage due to surface charge fluctuations.

[0089] The field plates 560 in the p-type JTE region 220 can distribute the electric field generated by the surface charge, thus minimizing the reduction of the reverse breakdown voltage due to fluctuations in the surface charge. In one embodiment of the present invention, the field plates 560 can be made of a metallic material to form a Schottky contact with the p-type JTE region 520. In another embodiment of the present invention, the field plates 260 can be made of a p-type polysilicon material to form an ohmic contact with the p-type JTE region 220. In yet another embodiment of the present invention, the field plates 560 can be made of an n-type polysilicon material to form a pn junction with the p-type JTE region 520.

[0090] Fig. Figures 7A to 7G are a schematic representation showing a manufacturing process for a high-voltage edge termination structure comprising a JTE structure with depletable protective rings and field plates provided according to an embodiment of the present invention.

[0091] Six masks are used in the manufacturing process. The first mask serves to define the channel stop area. The second mask is used to perform the JTE implantation. The third mask forms the anode of the active area.

[0092] The fourth mask is used for contact formation. The fifth mask is used for forming the metal layer. The sixth mask is used for forming the passivation / polyimide layer.

[0093] With reference to Fig. 7A First, an n-type semiconductor body 610 is provided. Then, the first mask is used to delimit a channel stop window for forming the channel stop region. Subsequently, an n-type, heavily doped channel stop region 640 is formed in the n-type semiconductor body 610 by ion implantation or diffusion. For example, but not limited to, phosphorus ions with a doping concentration in the range of 1e 15 Cm -2 up to 1e 16 Cm -2 The POCl3 molecules can be implanted into the n-type semiconductor body 610 to form the n-type, heavily doped channel stop region 640. Alternatively, a POCl3 diffusion process can be used to form the n-type, heavily doped channel stop region 640 in the n-type semiconductor body 610.

[0094] Then, with reference to Fig. 7B uses the second mask to constrain the position of the p-type JTE region and the p-type depletable guard rings. An ion implantation step is then performed to simultaneously form the p-type JTE region 620 and the p-type depletable guard rings 670. The p-type JTE region 620 is adjacent to the active region of the power semiconductor device and is spaced from the n-type heavily doped channel stop region 640. The p-type depletable guard rings 670 are formed between the p-type JTE region 620 and the n-type heavily doped channel stop region 640. For example, but not limited to, boron ions with a doping concentration in the range of 5e 12 Cm -2 up to 2e 13 Cm -2 implanted into the n-type semiconductor body 610 to form the p-type JTE region 620 and the p-type depletable guard rings 670.

[0095] Then, with reference to Fig. 7C after the ion implantation step in Fig. 7B A high-temperature diffusion step was performed to drive the p-conducting JTE region 620 and the p-conducting depletable guard rings 670 deeper. For example, but not limited to, the high-temperature diffusion step can achieve a transition depth in the range of 5 to 10 µm for the p-conducting JTE region 620.

[0096] Then, with reference to Fig. 7D uses the third mask to limit the position of the anode region within the active region, after which an ion implantation step can be performed to form the anode region 652 within the active region. For example, but not limited to, boron ions with a doping concentration in the range of 1e 14 Cm -2 up to 5e 15 Cm -2into the p-conducting well 651 in the active area to form the p-conducting anode area 652.

[0097] Then, with reference to Fig. 7E A dielectric layer 680 is applied to the semiconductor body 610. For example, but not limited to, the dielectric layer 680 can be an oxide layer, a phosphosilicate glass layer [PSG], or a borophosphosilicate glass layer [BPSG]. Then the fourth mask is used to form the contact windows 682 in the dielectric layer 680.

[0098] Then, with reference to Fig. In step 7F, a metal layer is applied to the dielectric layer 680 and fills the contact window 682. The fifth mask is then used to delimit the anode electrode and the field plates, after which an etching step is performed to form the anode electrode 654 and the field plates 660. For example, but not limited to, the metal layer can be an AlCu layer or an AlSiCu layer, with or without the Ti / TiN buffer layer, depending on the transition depths.

[0099] Referring to Fig. 7G: After the formation of the anode electrode 654 and the field plates 660, a passivation layer 690 is applied. For example, but not limited to, the passivation layer 690 can be a SiO2 passivation layer or a Si3N4 passivation layer. For example, but not limited to, a polyimide layer can be used to replace the passivation layer. Then, after the application of the passivation layer 690, the sixth mask is used to delimit bond pad areas (not shown).

[0100] It should be noted that in the manufacturing process mentioned above, a single mask or the second mask is used to limit the p-conducting JTE area 620 and the p-conducting depletable protective rings 670, as well as a single mask to limit the anode electrode 654 and the field plates 660, in order to reduce the number of masking steps.

[0101] Fig. Figures 8A to 8G are a schematic representation showing a manufacturing process for a high-voltage edge termination structure having a laterally modulated JTE structure provided according to an embodiment of the present invention.

[0102] The manufacturing process uses seven masks. The first mask serves to define the channel stop area. The second mask is used to perform the JTE implantation. The third mask forms the lightly doped areas within the JTE region to create the lateral modulated JTE area. The fourth mask forms the anode of the active region. The fifth mask forms the contact. The sixth mask forms the metal layer. The seventh mask forms the passivation / polyimide layer.

[0103] With reference to Fig. In step 8A, an n-type semiconductor body 710 is first provided. Then, the first mask is used to delimit a channel stop window for forming the channel stop region. Subsequently, an n-type, heavily doped channel stop region 740 is formed in the n-type semiconductor body 710 by ion implantation or diffusion. For example, but not limited to, phosphorus ions with a doping concentration in the range of 1e 15 Cm -2 up to 1e 16 Cm -2 The POCl3 can be implanted into the n-type semiconductor body 710 to form the n-type, heavily doped channel stop region 740. Alternatively, a POCl3 diffusion process can be used to form the n-type, heavily doped channel stop region 740 in the n-type semiconductor body 710.

[0104] Then, with reference to Fig. 8B uses the second mask to constrain the position of the p-type JTE region. An ion implantation step is then performed to form the p-type JTE region 720. The p-type JTE region 720 is adjacent to the active region of the power semiconductor device and is separated from the n-type, heavily doped channel stop region 740. For example, but not limited to, boron ions with a doping concentration in the range of 5e 12 Cm -2 up to 2e 13 Cm -2 implanted into the n-type semiconductor body 710 to form the p-type JTE region 720.

[0105] Then, with reference to Fig. 8C uses the third mask to confine several lightly doped regions within the p-type JTE region 720. An ion implantation step is then performed to create the multitude of lightly doped regions 730a to 730f within the p-type JTE region 720. For example, but not limited to, these p-type, lightly doped regions 730a to 730f can be created by implanting n-type impurities across the third mask with varying open areas into the p-type JTE region 720 to counter-dope the p-type JTE region 720.

[0106] The p-type, lightly doped regions 730a to 730f can be used to modulate the doping concentration of the p-type JTE region 720 from the active region to the edge. For example, but not limited to, the lateral width of the p-type, lightly doped regions 730a to 730f increases along a direction from the active region to the n-type, heavily doped channel stop region 740. A distance between the p-type, lightly doped region 730a near the active region and the active region is greater than a distance between any two adjacent lightly doped regions 730b to 730h.

[0107] Following the ion implantation step, a high-temperature diffusion step is performed to drive the p-type JTE region 720 deeper. For example, but not limited to, the high-temperature diffusion step can achieve a transition depth of 5 to 10 µm for the p-type JTE region 720.

[0108] Then, with reference to Fig. 8D uses the fourth mask to limit the position of the anode region within the active region, after which an ion implantation step can be performed to form an anode region 752. For example, but not limited to, boron ions with a doping concentration in the range of 1e 14 Cm -2 up to 5e 15 Cm -2 implanted into the p-conducting well 751 in the active area to form the p-conducting anode area 752.

[0109] Then, with reference to Fig. 8E A dielectric layer 780 is applied to the semiconductor body 710. For example, but not limited to, the dielectric layer 780 can be an oxide layer, a phosphosilicate glass layer [PSG], or a borophosphosilicate glass layer [BPSG]. Then the fifth mask is used to form the contact windows 682 in the dielectric layer 680.

[0110] Then, with reference to Fig. In step 8F, a metal layer is applied to the dielectric layer 780 and fills the contact window 782. The sixth mask is then used to delimit the anode electrode and the field plates, after which an etching step is performed to form the anode electrode 754 and the field plates 760. For example, but not limited to, the metal layer can be an AlCu layer or an AlSiCu layer, with or without the Ti / TiN buffer layer, depending on the transition depths.

[0111] Referring to Fig. 8G: After the formation of the anode electrode 754 and the field plates 760, a passivation layer 790 is applied. For example, but not limited to, the passivation layer 790 can be a SiO2 passivation layer or a Si3N4 passivation layer. For example, but not limited to, a polyimide layer can be used to replace the passivation layer 790. Then, after the application of the passivation layer 790, the sixth mask is used to delimit bond pad areas (not shown).

[0112] It should be noted that in the aforementioned manufacturing process, a single mask, or second mask, is used to delimit the p-type JTE region 720 and to create uniformity in the lower part of this region. A modulation mask, or third mask, with varying implant window openings, is used to counter-dope the p-type JTE region 720. The varying implant window openings allow for compensation of the upper portion of the p-type JTE region 720. The opening area of ​​the modulation mask, or third mask, can be enlarged along the direction towards the device edge to create more p-type, lightly doped regions 730a to 730f for depletion expansion.

[0113] In the event of an Fig.The laterally modulated JTE structure shown in Figure 1B requires a finer lithography capability for the p-type multi-zone JTE regions, which many power device fabricators may not possess. Therefore, the JTE structure with the p-type multi-zone JTE regions may require a larger or additional area for implementation. In contrast, according to the invention, a single p-type JTE mask is used to create uniformity in the deeper part of the p-type JTE region, and a modulation mask with varying implant window openings is used to counter-dope the p-type JTE region. The varying window openings allow for compensation of the upper part of the p-type JTE region to extend the depletion across the surface area and thus improve the surface charge tolerance of the JTE structure.The high-voltage edge termination structure provided according to the embodiment of the present invention can increase the tolerance to surface charge fluctuations with minimal area increase for implementation.

[0114] Although the embodiments of the present invention mentioned above are mainly described with regard to silicon semiconductor devices, they are not limited thereto. For example, the high-voltage edge termination structure according to some embodiments of the present invention can be formed on the semiconductor body made of silicon carbide (SiC), gallium nitride (GaN), or gallium arsenide (GaAs) without deviating from the scope of the present invention.

[0115] Although the embodiments of the present invention mentioned above are mainly described in relation to a power diode, they are not limited thereto. For example, the high-voltage edge termination structure according to some embodiments of the present invention can be applied to the semiconductor device with a MOSFET structure, the semiconductor device with an IGBT structure, or the semiconductor device with a thyristor structure without departing from the scope of the present invention.

Claims

[1] High-voltage edge termination structure for a power semiconductor device, comprising: a semiconductor body (110) of a first conductivity type; a JTE region (120) of a second conductivity type formed in the semiconductor body (110), wherein the JTE region (120) is adjacent to an active region (150) of the power semiconductor device; a heavily doped channel stop region (140) of the first conductivity type formed in the semiconductor body (110), wherein the heavily doped channel stop region (140) is spaced apart from the JTE region (120); and a plurality of field plates (260) designed with direct contact in the JTE area (120); wherein a field-stop extension region is adjacent to a conductive well region of the active region (150) of the power semiconductor device, and the conductive well region is electronically connected to an electrode through a heavily doped region therein; and wherein a depletable protective ring is between adjacent field plates (260) without an ohmic contact field plate. [2] High-voltage edge termination structure for a power semiconductor device according to claim 1, characterized by , that the first conductivity type is n-conductivity, while the second conductivity type is p-conductivity. [3] High-voltage edge termination structure for a power semiconductor device according to claim 1 or 2, characterized by that the field plates (260) are made of a metal material. [4] High-voltage edge termination structure for a power semiconductor device according to one of claims 1 to 3, characterized by, that the field plates (260) are made of p-conducting polysilicon. [5] High-voltage edge termination structure for a power semiconductor device according to one of claims 1 to 4, characterized by , that the field plates (260) are made of n-conducting polysilicon. [6] High-voltage edge termination structure for a power semiconductor device, comprising: a semiconductor body (310) of a first conductivity type; a JTE region (320) of a second conductivity type formed in the semiconductor body (310), wherein the JTE region (320) is adjacent to an active region (350) of the power semiconductor device; a heavily doped channel stop region (340) of the first conductivity type formed in the semiconductor body (310), wherein the heavily doped channel stop region (340) is spaced apart from the JTE region (320); a plurality of depletable protective rings (370) of the second conductivity type, formed between the JTE region (320) and the heavily doped channel stop region (340), and a plurality of field plates (360) formed individually in the JTE area (320) and on the plurality of depletable protective rings (370) with direct contact; wherein a field-stop extension region is adjacent to a conductive well region of the active region (350) of the power semiconductor device, and the conductive well region is electronically connected to an electrode through a heavily doped region therein; and wherein a depletable protective ring (370) is between adjacent field plates (360) without an ohmic contact field plate. [7] High-voltage edge termination structure for a power semiconductor device according to claim 6, characterized by, that the first conductivity type is n-conductivity, while the second conductivity type is p-conductivity. [8] High-voltage edge termination structure for a power semiconductor device, comprising: a semiconductor body (110) of a first conductivity type; a JTE region (120) of a second conductivity type formed in the semiconductor body (110), wherein the JTE region (120) is adjacent to an active region (150) of the power semiconductor device; a plurality of weakly doped regions (130a to 130h) of the second conductivity type, which are formed in the JTE region (120) next to an upper surface of the JTE region (120); and a heavily doped channel stop region (340) of the first conductivity type formed in the semiconductor body (110), wherein the heavily doped channel stop region (340) is spaced apart from the JTE region (120); wherein a field-stop extension region is adjacent to a conductive well region of the active region (150) of the power semiconductor device, and the conductive well region is electronically connected to an electrode through a heavily doped region therein; and wherein a depletable protective ring (370) is between adjacent field plates (360) without an ohmic contact field plate. [9] High-voltage edge termination structure for a power semiconductor device according to claim 8, characterized by , that the first conductivity type is n-conductivity, while the second conductivity type is p-conductivity. [10] High-voltage edge termination structure for a power semiconductor device according to claim 8 or 9, characterized by , that the lateral width of the p-conducting, weakly doped regions (130a to 130h) increases in the direction of the n-conducting, heavily doped channel stop region (140). [11] High-voltage edge termination structure for a power semiconductor device according to one of claims 8 to 10, characterized by , that the distance between the weakly doped region (130a) near the active region (150) and the active region (150) is greater than the distance between any two adjacent weakly doped regions (130b to 130h). [12] High-voltage edge termination structure for a power semiconductor device according to one of claims 8 to 11, further comprising a plurality of field plates (260) formed in the p-conducting JTE region (120). [13] High-voltage edge termination structure for a power semiconductor device according to claim 12, characterized bythat the field plates (260) are made of a metal material. [14] High-voltage edge termination structure for a power semiconductor device according to claim 12, characterized by , that the field plates (260) are made of p-conducting polysilicon. [15] High-voltage edge termination structure for a power semiconductor device according to claim 12, characterized by , that the field plates (260) are made of n-conducting polysilicon. [16] High-voltage edge termination structure for a power semiconductor device, comprising: a semiconductor body (410) of a first conductivity type; a JTE region (420) of a second conductivity type formed in the semiconductor body (410), wherein the JTE region (420) is adjacent to an active region (450) of the power semiconductor device; a heavily doped channel stop region (440) of the first conductivity type formed in the semiconductor body (410), wherein the heavily doped channel stop region (440) is spaced apart from the JTE region (420); a plurality of depletable guard rings (470) of the second conductivity type formed in the semiconductor body (410), wherein the depletable guard rings (470) are formed between the JTE region (420) and the heavily doped channel stop region (440), and a plurality of weakly doped areas (430a to 430e) of the second conductivity type formed in an upper section of the JTE area (420) and at least one of the depletable guard rings (470); wherein a field-stop extension region is adjacent to a conductive well region of the active region (450) of the power semiconductor device, and the conductive well region is electronically connected to an electrode through a heavily doped region therein; and wherein a depletable protective ring (470) is between adjacent field plates (460) without an ohmic contact field plate. [17] High-voltage edge termination structure for a power semiconductor device according to claim 16, characterized by , that the first conductivity type is n-conductivity, while the second conductivity type is p-conductivity. [18] High-voltage edge termination structure for a power semiconductor device according to claim 16 or 17, characterized by , that the lateral width of the p-conducting, weakly doped regions (430a to 430h) increases in the direction of the n-conducting, heavily doped channel stop region (440). [19] High-voltage edge termination structure for a power semiconductor device according to one of claims 16 to 18, characterized by , that a distance between the weakly doped region (430a) near the active region (450) and the active region (450) is greater than a distance between any two adjacent, p-conducting, weakly doped regions (430b to 430e). [20] High-voltage edge termination structure for a power semiconductor device according to one of claims 16 to 19, characterized by , that a gap between the depletable protective rings (470) increases in the direction of the heavily doped channel stop area (440). [21] High-voltage edge termination structure for a power semiconductor device according to one of claims 16 to 20, further comprising a plurality of field plates (460) formed in the JTE area (420). [22] High-voltage edge termination structure for a power semiconductor device according to claim 21, characterized by, that the field plates (460) are made of a metal material. [23] High-voltage edge termination structure for a power semiconductor device according to claim 21, characterized by , that the field plates (460) are made of p-conducting polysilicon. [24] High-voltage edge termination structure for a power semiconductor device according to claim 21, characterized by , that the field plates (460) are made of n-conducting polysilicon. [25] Method for manufacturing a high-voltage edge termination structure for a power semiconductor device, comprising: Forming a heavily doped channel stop region (640) of a first conductivity type in a semiconductor body (610) of the first conductivity type by ion implantation of the first conductivity type; Forming a JTE region (620) of a second conductivity type in the semiconductor body (610) by ion implantation of the second conductivity type, wherein the JTE region (620) is located adjacent to an active region of the power semiconductor device and spaced apart from the heavily doped channel stop region (640); and Forming a plurality of field plates (660) with direct contact in the JTE area (620); wherein a field-stop extension region is adjacent to a conductive well region of the active region of the power semiconductor device, and the conductive well region is electronically connected to an electrode through a heavily doped region therein; and wherein a depletable protective ring (670) is between adjacent field plates (660) without an ohmic contact field plate. [26] Method for manufacturing a high-voltage edge termination structure for a power semiconductor device, comprising: Forming a heavily doped channel stop region (640) of a first conductivity type in a semiconductor body (610) of the first conductivity type by ion implantation of the first conductivity type; Forming a JTE region (620) of a second conductivity type in the semiconductor body (610) by ion implantation of the second conductivity type, wherein the JTE region (620) is located adjacent to an active region of the power semiconductor device and spaced apart from the heavily doped channel stop region (640); and Forming a plurality of depletable guard rings (670) of the second conductivity type in the semiconductor body (610) by ion implantation of the second conductivity type, wherein the depletable guard rings (670) are formed between the JTE region (620) and the heavily doped channel stop region (640), and Forming a plurality of field plates (360) individually in the JTE area (320) and on the plurality of depletable protective rings (370) with direct contact; wherein a field-stop extension region is adjacent to a conductive well region of the active region of the power semiconductor device, and the conductive well region is electronically connected to an electrode through a heavily doped region therein; and wherein a depletable protective ring (670) is between adjacent field plates (660) without an ohmic contact field plate. [27] Method for manufacturing a high-voltage edge termination structure for a power semiconductor device according to claim 26, characterized by , that the JTE area (620) and the depletable guard rings (670) are formed simultaneously in the semiconductor body (610). [28] Method for manufacturing a high-voltage edge termination structure for a power semiconductor device, comprising: Forming a heavily doped channel stop region (740) of a first conductivity type in a semiconductor body (710) of the first conductivity type by ion implantation of the first conductivity type; Forming a JTE region (720) of a second conductivity type in the semiconductor body (710) by ion implantation of the second conductivity type, wherein the JTE region (720) is located adjacent to an active region of the power semiconductor device and spaced apart from the heavily doped channel stop region (740); and Formation of a plurality of weakly doped areas (730a to 730f) of the second conductivity type in the JTE region (720) next to an upper surface of the JTE region (720) by ion implantation of the first conductivity type; wherein a field-stop extension region is adjacent to a conductive well region of the active region of the power semiconductor device, and the conductive well region is electronically connected to an electrode through a heavily doped region therein; wherein a depletable protective ring (770) is between adjacent field plates (760) without an ohmic contact field plate. [29] Method for producing a high-voltage edge termination structure for a power semiconductor device according to claim 28, further comprising forming a plurality of field plates (760) in the JTE area (720). [30] Method for manufacturing a high-voltage edge termination structure for a power semiconductor device, comprising: Forming a heavily doped channel stop region (640) of a first conductivity type in a semiconductor body (610) of the first conductivity type by ion implantation of the first conductivity type; Forming a JTE region (620) of a second conductivity type and a plurality of depletable guard rings (670) of the second conductivity type in the semiconductor body (610) by ion implantation of the second conductivity type, wherein the JTE region (620) is adjacent to an active region of the power semiconductor device and spaced apart from the heavily doped channel stop region (640), and wherein the depletable guard rings (670) are formed between the JTE region (620) and the heavily doped channel stop region (640); and Formation of a plurality of weakly doped areas (730a to 730f) of the second conductivity type in an upper section of the JTE area (620) and the depletable guarding rings (670) by ion implantation of the first conductivity type; wherein a field-stop extension region is adjacent to a conductive well region of the active region of the power semiconductor device, and the conductive well region is electronically connected to an electrode through a heavily doped region therein; and wherein a depletable protective ring (670) is between adjacent field plates (660) without an ohmic contact field plate. [31] Method for producing a high-voltage edge termination structure for a power semiconductor device according to claim 30, further comprising forming a plurality of field plates (660) in the JTE area (620).

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