Non-planar electrical fuse based on siliciated semiconductor

Abstract

E-Fuse (100), including: a fuse insert (140) with a siliciated semiconductor layer (142) over a dielectric layer (120) covering a gate conductor (116), wherein the siliciated semiconductor layer (142) is not planar; a first connection (150) which is electrically coupled to a first end (152) of the fuse link (140); and a second terminal (154) which is electrically coupled to a second end (156) of the fuse insert (140), wherein the siliciated semiconductor layer (142) comprises a semiconductor layer (122) and a silicide layer (144) formed thereon, wherein an intrinsic basis and / or an extrinsic basis of a bipolar transistor (158) is formed in the semiconductor layer (122).

Description

background

[0001] The present invention relates to integrated circuits and in particular a non-planar electrical fuse based on a silicided semiconductor.

[0002] Various components of an integrated circuit (IC) can be coupled to an electrical fuse (e-fuse). E-fuses can be "programmed" to change connections within the IC. Specifically, a metal within the fuse element can be made to migrate by applying a prescribed current controlled by a transistor. Once enough metal has migrated, the fuse element opens or blows, preventing current from flowing through the fuse. One challenge with electrical fuses is that they occupy a large footprint within ICs due to the size of the fuse itself and the associated power source required for programming. Electrical fuses also contain a planar fuse element, which occupies a significant area.Typically, the size of an e-fuse is limited by the size of the gate traces within a given technology node. Accordingly, an approach to reducing the size of e-fuses involves reducing the fuse link size to the minimum gate trace length permitted by a technology node.

[0003] Document US 6,667,537 B1 discloses a semiconductor device. This semiconductor device comprises a first insulating layer, a locking element in direct contact with the top surface of the first insulating layer, wherein the locking element is made of a material consisting of titanium nitride containing oxygen atoms, a second insulating layer covering at least a portion of the locking element, a first electrode extending through a first portion of the second insulating layer and electrically connected to the locking element, a second electrode extending through a second portion of the second insulating layer and electrically connected to the locking element, and wherein the first electrode is spaced apart from the second electrode.

[0004] According to US patent 2011 / 0127637A1, an electronic fuse structure (E-fuse) is known. This E-fuse consists of a first electrode, a dielectric layer on the first electrode with a plurality of nanochannels therein, an array of metal silicide nanopillars filling the nanochannels in the dielectric layer, each nanopillar in the array serving as an electronic fuse element, and a second electrode in contact with the array of metal silicide nanopillars opposite the first electrode.

[0005] Document US 5,472,901 A describes a method for manufacturing an integrated circuit structure consisting of one or more metal fuses on an insulating layer formed over other parts of the integrated circuit structure, while one or more vias or contact openings in the insulating layer are filled with the same metal.The method comprises the following steps: a) forming one or more rectangular depressions in the insulating layer, b) forming one or more vias or contact openings through the insulating layer to the underlying integrated circuit structure, c) subsequently filling the rectangular depressions and the vias or contact openings with metal by depositing a metal layer over the insulating layer, d) subsequently planarizing the deposited metal layer up to the vias or contact openings to remove the portions of the metal layer deposited over the insulating layer, leaving metal strands on the sidewalls of the rectangular depressions, and e) subsequently forming one or more metal conductors on the insulating layer in electrical contact with at least one end of one or more of these metal strands.The metal strands that come into contact with the metal traces are formed when the vias or contact holes are filled with metal. These metal strands act as a connector between the metal traces and other parts of the integrated circuit structure that are in electrical contact with the opposite end of the metal strands.

[0006] Patent application US 2008 / 0237786A1 discloses a locking structure consisting of a non-planar locking material layer over a substrate. The non-planar locking material layer exhibits an angular bend.

[0007] According to US patent 2007 / 0 052 063 A1, a semiconductor device is known comprising: a semiconductor substrate and an electrical fuse formed on said semiconductor substrate, comprising a first and a second connecting line. The electrical fuse has a region in which several straight sections are arranged side by side by folding the first connection, and the second connecting line is narrower than the first connecting line. The second connecting line is connected to the first outside of said region.

[0008] Document US 2016 / 0056162A1 shows a semiconductor structure. This semiconductor structure comprises a substrate, a polycidal fuse structure arranged over the substrate and comprising silicon and a metal, and a metal oxide semiconductor (MOS) transistor structure arranged over the substrate and comprising a metal gate electrode.

[0009] US Patent 8,268,679 B2 describes a method for manufacturing an electronic fuse for an integrated circuit, comprising: forming an electrode material over an insulating material formed over a substrate of the integrated circuit; forming a first contact area, a second contact area, and a melting area of ​​the electronic fuse from the electrode material; and forming contact elements on a contact plane of the integrated circuit. The melting area is connected to the first and second contact areas and has at least two nonlinear sections for generating a zone of increased current density, with two of these at least two nonlinear sections forming a fork. Furthermore, the contact elements are connected to the first and second contact areas of the electronic fuse. Summary

[0010] In one aspect of the invention, an electrical fuse (e-fuse) is provided according to independent claim 1. Advantageous embodiments thereof are defined in dependent claims 2 to 10.

[0011] In another aspect of the invention, an integrated circuit is provided according to independent claim 11. Advantageous embodiments thereof are defined in dependent claims 12 to 18.

[0012] In another aspect of the invention, a method according to independent claim 19 is provided.

[0013] The above and other features of the invention are evident from the following more specific description of embodiments of the invention. Brief description of the drawings

[0014] The embodiments of this invention are described in detail with reference to the following figures, where identical designations denote identical elements and where: Fig. Figures 1-2 show cross-sectional views of an electrical fuse (e-fuse) formation according to embodiments of the invention. Fig. Figure 3 shows an enlarged cross-sectional view of an e-fuse with a non-planar fuse insert made of a silicided semiconductor according to embodiments of the invention. Fig. 4 a top view of the e-fuse of Fig. 3 shows. Fig. Figure 5 shows a cross-sectional view of an e-fuse with a non-planar fuse insert made of silicided semiconductor according to other embodiments of the invention. Fig. 6 a top view of the e-fuse of Fig. 5 shows. Fig. Figure 7 shows a cross-sectional view of an e-fuse with a non-planar fuse insert made of silicided semiconductor according to further embodiments of the invention. Fig. 8 a top view of the e-fuse of Fig. 7 shows. Fig. Figure 9 shows a top view of an e-fuse with a non-planar fuse insert having one or more curves according to embodiments of the invention. Fig. Figure 10 shows a top view of an e-fuse with a non-planar fuse insert having one or more curves according to other embodiments of the invention. Fig. Figure 11 shows a top view of an e-fuse with a non-planar fuse insert having one or more curves according to other embodiments of the invention. Fig. Figure 12 shows a top view of an e-fuse with a non-planar fuse insert according to embodiments of the invention. Fig. Figure 13 shows a top view of an e-fuse with a non-planar fuse insert and a control transistor according to embodiments of the invention. Fig. Figure 14 shows a top view of an e-fuse with a non-planar fuse insert and a control transistor according to other embodiments of the invention. Fig. Figure 15 shows a cross-sectional view of an integrated circuit comprising an e-fuse with a non-planar fuse insert made of silicided semiconductor, according to embodiments of the invention.

[0015] It should be noted that the drawings of the invention are not necessarily to scale. The drawings are intended to illustrate only typical aspects of the invention and should therefore not be considered to limit its scope. Reference numerals in the drawings represent identical elements. Detailed description

[0016] The following description refers to the accompanying drawings, which form part thereof and illustrate specific embodiments in which the present invention can be applied. These embodiments are described in sufficient detail to enable a person skilled in the art to apply the present invention, and it is understood that other embodiments can also be used and modifications made without departing from the scope of the present teaching. The following description is therefore for illustrative purposes only.

[0017] It is understood that when an element, such as a layer, area, or substrate, is described as being "on" or "above" another element, it may be located directly on top of the other element, or there may be intermediate elements. Conversely, an element described as being "directly on" or "directly above" another element may not have any intermediate elements. When an element is described as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intermediate elements. Conversely, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intermediate elements.

[0018] A reference in the description to "an embodiment" of the present invention, as well as other variations thereof, means that a particular feature, structure, property, etc., described in connection with the embodiment, is included in at least one embodiment of the present invention. Therefore, the expressions "in an embodiment," as well as any other variations appearing at different points in the description, do not necessarily all refer to the same embodiment. It should be understood that the use of " / ," "and / or," and "at least one of," e.g., in the cases of "A / B," "A and / or B," and "at least one of A and B," is intended to include the selection of only the first listed option (a), the selection of only the second listed option (B), or the selection of both options (A and B).According to another example, in the cases "A, B and / or C" and "at least one of A, B and C", this wording is intended to include only the first listed option (A), or only the selection of the second listed option (B), or only the selection of the third listed option (C), or the selection of the first and second listed options (A and B), or the selection of the first and third listed options (A and C), or the selection of the second and third listed options (B and C), or the selection of all three options (A, B and C). As is readily apparent to a person skilled in the art, this can be extended to include any number of listed options.

[0019] Embodiments of the invention provide an electrical fuse (e-fuse) comprising a fuse element with a silicided semiconductor layer over a dielectric layer covering a gate conductor. Thus, the fuse element is electrically isolated from the underlying gate conductor. The silicided semiconductor layer is non-planar and extends orthogonally across the gate conductor. The non-planar fuse element offers greater length with a smaller footprint compared to conventional planar e-fuses. Furthermore, the length of the fuse element can be customized, for example, based on the height of the gate conductor and the dielectric layer, the number of gate conductors it spans, and the number of transitions across the gate conductor(s).A first terminal is electrically connected to a first end of the fuse element, and a second terminal is electrically connected to a second end of the fuse element. The semiconductor fuse connection can conveniently be formed in the same layer as an intrinsic and / or extrinsic base of a bipolar transistor during the fabrication of a bipolar complementary metal-oxide semiconductor (BiCMOS), thus eliminating the need for additional fabrication steps. The gate conductor can be part of a transistor that controls a current source for programming the e-fuse, further reducing the footprint compared to conventional e-fuses by placing the control transistor at least partially beneath the fuse element. The e-fuse also requires less energy for programming compared to conventional e-fuses.

[0020] Fig. 1 and Fig. Figure 2 shows enlarged cross-sectional views of a method for forming parts of an integrated circuit (IC) 102, including an electrical fuse (e-fuse) 100, according to embodiments of the invention. In one embodiment, the IC 102 comprises a bipolar transistor section 110 and a complementary metal-oxide semiconductor (CMOS) transistor section 112. The e-fuse 100 is formed in the CMOS transistor section 112 but can be formed simultaneously with parts of the bipolar transistor section 110. Alternatively, the e-fuse 100 can be formed exclusively in a CMOS transistor section 112 if the IC 102 does not include a bipolar transistor section 110. A substrate 114 on which the sections are built can comprise any semiconductor substrate known today or developed later, e.g., a bulk substrate or a semiconductor-on-insulator (SOI) substrate.

[0021] At this stage, the bipolar transistor region 110 includes an implantation region 115 of n-type or p-type to form the various parts of a bipolar transistor, such as a collector in this example. Since this structure and the methods for its formation are well known in engineering, further description is unnecessary. The CMOS transistor region 112 can include source / drain regions 118 formed in the substrate 114 in any known manner, e.g., by implanting suitable dopants. In one example, the source regions 118S for the gate conductors 116 have a drain region 118D separated from them by corresponding channel regions (not numbered for clarity—located below the gate conductors 116). Any necessary trench insulation 119 can also be provided and formed in any manner now known or subsequently developed, e.g.,by etching holes into the substrate 114 prior to the formation of the gate conductors 116 and filling with a dielectric such as an oxide.

[0022] Etching generally refers to the removal of material from a substrate (or from structures formed on the substrate) and is often performed with a mask so that material can be selectively removed from certain areas of the substrate while leaving the material in other areas unaffected. Etching is generally performed in two categories: (i) wet etching and (ii) dry etching. Wet etching is performed with a solvent (e.g., an acid) that can be chosen for its ability to selectively dissolve a particular material (e.g., oxide) while leaving another material (e.g., polysilicon) relatively intact. This ability to selectively etch certain materials is fundamental to many semiconductor fabrication processes. Wet etching generally etches a homogeneous material (e.g., oxide) isotropically, but wet etching can also anisotropically etch single-crystal materials (e.g., silicon wafers).Dry etching can be performed using a plasma. Plasma systems can operate in different modes by adjusting the plasma parameters. Conventional plasma etching generates energetic free radicals that are neutrally charged and react at the surface of the wafer. Because neutral particles attack the wafer from all angles, this process is isotropic. In ion etching, or sputter etching, the wafer is bombarded with high-energy ions from noble gases that approach the wafer from approximately one direction, making this process highly anisotropic. Reactive ion etching (RIE) operates under conditions intermediate between sputter and plasma etching and can be used to fabricate deep, narrow structures, such as trench insulation trenches.

[0023] The CMOS transistor area 112 comprises a number of gate conductors 116 formed on it. In the Fig. In the example shown in Figures 1-4, two gate conductors 116 are depicted. According to the description herein, more or fewer gate conductors 116 are also possible. In the example shown in Fig. In the example shown in Figures 1-2, the gate conductors 116 are located in an active region of the CMOS transistor region 112 and are thus used as active gates. In this case, in a non-restrictive example, the gate conductor(s) 116 may be made of polysilicon. In another example, the gate conductor(s) 116 may comprise a metal gate. Although shown as a single material for clarity, metal gates may include one or more conductive components to provide a gate terminal for a transistor. For example, metal gates may include a high-k dielectric constant layer, an exit-work metal layer, and a conductive layer (not all shown for clarity). The high-k layer may include any high-k material now known or subsequently developed that is typically used for metal gates, such as…Without restriction: Metal oxides such as tantalum oxide (Ta2O5), barium titanium oxide (BaTiO3), hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3) or metal silicates such as hafnium silicate oxide (Hf. A1 Si A2 O A3 ) or hafnium silicate oxynitride (Hf A1 Si A2 O A3 N A4), where A1, A2, A3, and A4 represent relative fractions, each greater than or equal to zero, and A1+A2+A3+A4 (where 1 is the total relative molar quantity). The exit work metal layer can comprise various metals, depending on whether it is an NFET or PFET device, but can include, for example, aluminum (Al), zinc (Zn), indium (In), copper (Cu), indium copper (InCu), tin (Sn), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), titanium (Ti), titanium (Ti), titanium nitride (TiN), titanium carbide (TiC), TiAlC, TiAl, tungsten (W), tungsten nitride (WN), tungsten carbide (WC), polycrystalline silicon (poly-Si), and / or combinations thereof. The conductor layer can comprise any gate conductor known today or subsequently developed, such as copper (Cu). A gate cap (not shown), e.g. made of a nitride, can also be formed over the gate area. The gate conductor 116 can also have a spacer (not shown), e.g.made of silicon nitride, surrounding itself. The gate conductor 116 can be formed over the substrate 114 using any IC fabrication technique known today or developed later, e.g., by material deposition, photolithographic structuring with masks and etching, etc. In other embodiments, as will be described later, the gate conductor(s) 116 may not be an active gate and may comprise materials other than those listed above.

[0024] Fig. Figure 1 also shows the formation of a semiconductor layer 122 over one or more gate conductors 116 for the CMOS transistor area 112 and, if a bipolar transistor area 110 is present, for generating at least one of an intrinsic base and an extrinsic base (within the dashed box 124) for the bipolar transistor area 110. Fig. Figure 1 also shows the formation of a dielectric layer 120 over the gate conductor(s) 116. The semiconductor layer 122 and the dielectric layer 120 can be formed by any suitable deposition technique. "Deposition" can include any technique known today or developed later that is suitable for the material to be deposited, including, but not limited to, e.g.B: Chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD) and high-density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), reaction-limited CVD (LRPCVD), metal-organic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser-assisted deposition, thermal oxidation, thermal nitriding, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), electroplating, evaporation. The semiconductor layer 122 and the dielectric layer 120 can, for example, be formed by ALD. A mask can be used to block the deposition of the dielectric layer 120 over the bipolar transistor area 110, or the dielectric layer 120 can be etched away from the area 110.It is acknowledged that the processing shown for the CMOS transistor area 112 can be carried out without the processing shown with respect to the bipolar transistor area 110, i.e., when there are no bipolar transistors in the IC 102.

[0025] The semiconductor layer 122 can, for example, comprise silicon (Si) or silicon-germanium (SiGe). The semiconductor layer 122 is the same layer used to form an intrinsic basis and / or an extrinsic basis (in the dashed box 124) of the bipolar transistor region 110. In this case, the semiconductor layer 122 can have a dopant concentration of more than 5 × 10¹⁸ atoms / cm². 3 exhibit. The dopant can be any suitable element for the polarity type of the base or bases of a bipolar transistor 158 ( Fig. 2) represent, which is to be formed in region 110. N-type dopants are elements introduced into the semiconductor to create a free electron (by "donating" an electron to the semiconductor) and must have one more valence electron than the semiconductor; common donors in silicon (Si): phosphorus (P), arsenic (As), antimony (Sb) and in gallium arsenic (GaAs): sulfur (S), selenium (Se), tin (Sn), silicon (Si) and carbon (C). P-type dopants are elements introduced into the semiconductor to create a free hole (by "accepting" an electron from the semiconductor atom and simultaneously "donating" a hole); the acceptor atom must have one fewer valence electron than the host semiconductor. P-type dopants can include, without restriction: boron (B), indium (In), and gallium (Ga).

[0026] The dielectric layer 120 can comprise any suitable dielectric material, including but not limited to: carbon-doped silicon dioxide materials; fluorinated silicate glass (FSG); organic, polymeric, thermosetting materials; silicon oxycarbide; SiCOH dielectrics; fluorinated silicon oxide; spin-on glasses; silsesquioxanes, including hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ) and mixtures or copolymers of HSQ and MSQ; benzocyclobutene (BCB)-based polymer dielectrics and any silicon-containing low-k dielectric. Examples of spin-applied low-k films with SiCOH-like composition using silsesquioxane chemistry include HOSP™ (available from Honeywell), JSR 5109 and 5108 (available from Japan Synthetic Rubber), Zircon™ (available from Shipley Microelectricals, a division of Rohm and Haas), and porous low-k (ELk) materials (available from Applied Materials).Examples of carbon-doped silicon dioxide materials or organosilanes are Black Diamond™ (available from Applied Materials) and Coral™ (available from Lam Research). An example of an HSQ material is FOx™ (available from Dow Corning). Here, the dielectric layer 120 can, for example, comprise a high-temperature oxide (HTO). It should be noted that the gate conductor 116, regardless of its shape, is covered by the dielectric layer 120 and is therefore generally electrically insulated from the structure above it.

[0027] Fig. Figure 2 shows the structure of the semiconductor layer 122, which extends orthogonally across the gate conductor(s) 116 - see also the top view of Fig. 4. This step is shown following a series of intermediate steps for the formation of the emitter 128 in the bipolar transistor region 110. These intermediate steps can include any techniques now known or developed later and are therefore not described further. As shown, a mask 130 can be formed and structured to enable the structuring of the semiconductor layer 122. If a bipolar transistor region 110 is provided, the mask 130 can also be used to structure parts of the intrinsic and / or extrinsic base (within the dashed box 124). Any suitable masking and etching technique can be used to structure the semiconductor layer 122, e.g., a silicon nitride hard mask and etching. Fig. Figure 4 shows an embodiment of the fuse insert 140 with the semiconductor layer (after silicide coating) extending orthogonally across the gate conductor(s) 116. For example, a RIE can be used to structure the semiconductor layer.

[0028] Fig. Figure 3 shows a cross-sectional view of a forming of a fuse insert 140 for the e-Fuse 100 by silicideizing the semiconductor layer 122 over the dielectric layer 120 over the gate conductor(s) 116. Fig. Figure 4 shows a schematic top view of the e-Fuse 100 with a view line 3-3, which is shown in Fig. Figure 3 shows the cross-sectional view. Fig. 3 and Fig. For clarity, 4 is the bipolar transistor area 110 ( Fig. 1-2) omitted. The silicideation process forms a silicided semiconductor layer 142, which comprises a semiconductor layer 122 made of silicon (Si) or silicon germanium (SiGe) with a silicide layer 144 on top of it. Therefore, the fuse insert 140 includes the silicided semiconductor layer 142 with the semiconductor layer 122 and the silicide layer 144. The silicide layer 144 can be formed by any technique known today or developed later, e.g., by performing in-situ pre-cleaning, depositing a metal such as titanium, nickel, cobalt, etc., annealing to react the metal with the semiconductor layer 122, and removing the unreacted metal. Although the silicide layer 144 is shown over the entire length of the fuse insert 140, it can also extend over only a portion of the fuse insert 140. Fig. Figure 3 also shows that the silicided semiconductor layer 142 (fuse insert 140) is not planar over the gate conductor(s) 116. That is, it has peaks and troughs as it extends over the gate conductor(s) 116.

[0029] Fig. 3 and Fig. Figure 4 also shows the formation (completion) of the e-fuse 100 by forming a first terminal 150, which is electrically coupled to a first end 152 of the fuse connection 140, and a second terminal 154, which is electrically coupled to a second end 156 of the fuse connection 140. The terminals 150, 154 are located on opposite sides of the gate conductor(s) 116. The terminals 150, 154 can be formed by any method of making electrical connections known today or developed later. In a non-limiting example, an interlayer dielectric (ILD) 148 ( Fig. 3) be deposited (e.g., with ALD). The ILD 148 can comprise any dielectric previously listed here for the dielectric layer 120. The terminals 150, 154 can be formed by structuring a mask and etching the terminal openings at the respective ends 152, 156 of the fuse insert 140, e.g., using a RIE. As shown in Fig. 4. During the structuring of the semiconductor layer 122 as described herein, the ends 152, 156 can be structured such that they are enlarged compared to the rest of the fuse insert 140 to provide a landing area for the terminals 150, 154. A conductor can then be formed in the terminal openings. The conductor can comprise a coating of a high-melting-point metal and a terminal metal. The high-melting-point metal coating (not labeled for clarity) can, for example, comprise ruthenium (Ru), tantalum (Ta), titanium (Ti), tungsten (W), iridium (Ir), rhodium (Rh), and platinum (Pt), etc., or mixtures thereof. The terminal metal can comprise any conductor known today or subsequently developed, such as, but not limited to, copper (Cu) or tungsten (W).

[0030] The e-Fuse 100 comprises a fuse insert 140 with a silicided semiconductor layer 142 over a dielectric layer 120 covering the gate conductor 116. The e-Fuse 100 also includes a first terminal 150, which is electrically connected to the first end 152 of the fuse insert 140, and a second terminal 154, which is electrically connected to the second end 156 of the fuse insert 140. As already mentioned, the semiconductor layer 122 contains an intrinsic base and / or an extrinsic base (dashed box 124 ( Fig. 2)) of the bipolar transistor 158 ( Fig. 2) The gate conductor(s) 116 is covered by the dielectric layer 120 and lies silicide-free beneath the dielectric layer 120 under the silicided semiconductor layer 122.

[0031] The fuse link 140 is configured, i.e., shaped and / or dimensioned, such that when the appropriate current is applied, supplied via terminals 150 and 154, a metal or metal alloy can migrate to open the fuse link 140, in particular to control energy for programming the opening or blowing of the fuse. For example, the fuse link 140 can be shaped to accommodate any length WL ( Fig. 4) has, e.g. during the structuring of the semiconductor layer 122 ( Fig. 2).

[0032] The length of the fuse link 140 can also be controlled in various ways during manufacturing to produce the e-Fuse 100 with a desired energy for programming. Since the silicided semiconductor layer 142 of the fuse link 140 extends orthogonally across the gate conductor(s) 116, the silicided semiconductor layer 142 and the fuse link 140 are not planar, and their length can be controlled by controlling the length and / or height of the gate conductor(s) 116 and / or the dielectric layer 120. For example, the height of the gate conductor(s) 116 and the thickness of the dielectric layer 120 can be controlled to adjust the length of the fuse link 140 required to extend across them. Alternatively, a length Lg ( Fig. 3) of the gate conductor(s) 116 are controlled to change the length of the fuse insert 140.

[0033] The number of gate conductors (116) can also be selected to adjust the length of the fuse link (140). Fig. 3 and Fig. Figure 4 shows two gate conductors 116. However, any number of gate conductors 116 can be provided. For example, the fuse link 140 can contain a silicided semiconductor layer 142 over a dielectric layer 120 covering a plurality of gate conductors 116, so that the non-planar fuse link has any number of peaks and troughs. One gate conductor 116 or more than two gate conductors 116 can be used. Fig. Figure 5 shows a cross-sectional view and Fig. Figure 6 shows a schematic top view (where line 5-5 is the cross-sectional view line of Fig. 5 represents) the e-Fuse 100 with a gate conductor 116. Here, for example, a length Lg and / or a height of the gate conductor 116 and the dielectric layer 120 can be produced to control a length of the fuse insert 140. Fig. 7 shows a cross-sectional view and Fig. Figure 8 shows a schematic top view (where line 7-7 represents the cross-sectional view of Fig. (Figure 7 shows) the e-Fuse 100 with more than two gate conductors 116. A length Lg and / or a height of each gate conductor 116 and / or each dielectric layer 120 can also be selected to control the length of the fuse link 140. In this way, any number of peaks and troughs can be formed in the fuse link 140.

[0034] According to the view in Fig. 9-11 The length of the fuse link 140 can also be controlled by providing the fuse link 140 with at least one lateral curve 160. In this way, the length of the fuse link 140 can be selected by the number of times the fuse link 140 passes over the gate conductor(s) 116 and the additional length provided by the curve(s) 160. In this case, the fuse link 140 generally extends orthogonally over the gate conductor(s) 116 more than once, but can also have a non-orthogonal extent. For example, Fig. 9 a top view of the safety insert 140, which extends twice orthogonally over the gate ladder(s) 116, e.g. with one or two curves 160 in it. Fig. 10 and Fig. Figure 11 shows top views of two other alternative embodiments with different curves 160 therein. Fig. Figure 10 shows the e-Fuse 100 with a non-planar fuse insert 140, which has a laterally sinusoidal configuration, and Fig. Figure 11 shows the e-Fuse 100 with a non-planar fuse link 140, which has a curved central section. The curves 160 can be present in any number and / or assume any conceivable shape(s) to achieve the desired programming energy. As shown in Fig. 10 and Fig. In certain embodiments, the fuse element 140 can extend at a non-orthogonal angle over the gate conductor(s) 116. The curve(s) 160 make it possible to minimize the area of ​​the fuse element 140.

[0035] With regard to the Fig. 7, Fig. 8 and Fig. Figure 12 shows top views of alternative embodiments. In certain embodiments, the gate conductor(s) 116 cannot function as part of the active device(s). According to the illustration in the Fig. 7, Fig. 8 and Fig. 12. The gate conductor 116 may, for example, be non-functional, i.e., it has no source / drain regions and no connections to active components. In this case, the gate conductor 116 may, in addition to the materials listed above, contain any dummy gate material, e.g., amorphous silicon or another suitable dummy gate material. In other embodiments, the gate conductor 116 may be a resistor 162 (see, e.g., Fig. 12) In this case, the gate conductor(s) 116 can be used to heat the e-Fuse 100 in order to control the programming energy. When connected to a power supply, the gate conductor(s) 116 generate heat depending on the resistance value, which can reduce the programming energy required for the fuse.

[0036] With reference to Fig. Figures 13-14 show schematic top views of other embodiments of the e-Fuse 100. The position of the fuse element 140 relative to the gate conductor(s) 116 can also be varied to control the programming energy.

[0037] For example, the position of the fuse link 140 above the gate conductor(s) 116 can be chosen to achieve the lowest programming energy. The chosen location does not necessarily have to be in the middle of the gate conductor(s) 116. Fig. In diagram 13, the safety element 140 is located, for example, next to an active transistor 168A and not in the middle of the gate conductor(s) 116. In the Fig. 4, Fig. 9 and Fig. In 14, the safety element 140 is located between active transistors 168B and C, which share the gate conductors 116, and is generally centered along the gate conductor(s) 116. In another embodiment, where another structure does not prohibit this, e.g., as in Fig. 8, the safety element 140 can be located at any point along the length of the gate conductor 116.

[0038] With regard to the Fig. In certain embodiments, the gate conductor 116 can be part of a control transistor 170 configured to electrically couple a current source 172 to the first terminal 150 for programming the e-fuse 100, with the second terminal 154 electrically connected to ground. In one embodiment, the gate conductor 116 can be part of a CMOS control transistor 170, and the CMOS transistor can be configured to electrically couple the current source 172 to the non-planar fuse insert 140 for programming the e-fuse 100. Fig. In the examples shown in Figures 13-14, the drain region 118D of the control transistor 170 is coupled to the first (cathode) terminal 150 of the e-fuse 100 via any form of IC connection 180, and the second terminal 154 is coupled to the current source 172. A source region 118S of the control transistor 170 is coupled to ground. In this way, when the control transistor 170 is activated, a current flows from the current source 172 through the e-fuse 100 to ground, thereby programming the e-fuse 100, i.e., opening the fuse 140. A bipolar transistor 158 ( Fig. 2) can be arranged similarly as a control transistor 170. In other embodiments, a bipolar transistor 158 ( Fig. 2) can be used as a programming source for the e-Fuse 100 instead of a CMOS transistor in the CMOS area 112.

[0039] Fig. Figure 15 shows a cross-sectional view of IC 102 with bipolar transistor area 110 and CMOS transistor area 112. Here, IC 102 comprises a bipolar transistor 158 with an intrinsic base and / or an extrinsic base (dashed box 124) and a CMOS transistor 168. IC 102 also includes an e-fuse 100 with a non-planar fuse insert 140, which comprises a silicided semiconductor layer 142 over a dielectric layer 120 covering the gate conductor(s) 116. As shown in the illustration in the Fig. At 4, 6, 8, 9 and 12-14, the silicided semiconductor layer 142 extends orthogonally across the gate conductor(s) 116. The e-fuse 100 also includes a first terminal 150, which is electrically connected to the first end 152 of the non-planar fuse insert 140, and a second terminal 154, which is electrically connected to the second end 156 of the non-planar fuse insert 140. The silicided semiconductor layer 142 includes at least one intrinsic base and one extrinsic base (dashed box 124) of the bipolar transistor 158. In this case, the silicided semiconductor layer 142 may contain a dopant with a dopant concentration of more than 5 × 10⁸ atoms / cm². 3 may have to accommodate the bases of the bipolar transistor 158. The silicided semiconductor layer 142 may contain, for example, silicon (Si) or silicon-germanium (SiGe). In certain embodiments, e.g., Fig. 13-14, the gate conductor 116 is part of the CMOS control transistor 170, which is configured to electrically couple the current source 172 with the non-planar fuse insert 140 for programming the e-fuse 100. In other embodiments, e.g., in Fig. 12, the gate conductor(s) is a resistor 162 capable of heating the fuse link 140 to control a programming energy. In other embodiments, the non-planar fuse link 140 may contain at least one curve 160, as shown in Fig. 9-11. The non-planar safety device 140 can extend orthogonally across the gate ladder(s) 116 more than once, as shown in Fig.9. The non-planar fuse insert 140, including the silicided semiconductor layer 122 over the dielectric layer 120, can cover a plurality of gate conductors 116, so that the non-planar fuse insert 140 has a plurality of peaks and troughs. Each of the embodiments described here can be mixed and adapted to control the characteristics of the e-fuse 100.

[0040] Embodiments of the invention provide an e-fuse that can reduce the energy required for programming by, for example, 25-30%. The e-fuse also reduces the size of a programming current source 172, thereby reducing the footprint of the entire circuit by, for example, approximately 10-25% compared to conventional planar e-fuses. As described, no additional masks are required for the implementation of the e-fuse 100, and the minimum size is not dependent on the gate length. If the gate traces are used as part of the control transistor, the heat from the transistor can also lead to a lower current for the e-fuse, resulting in a further reduction in area.

[0041] The process described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., a single wafer containing multiple unpackaged chips), as bare chips, or in packaged form. In the latter case, the chip is mounted in a single-chip package (e.g., a plastic substrate with traces attached to a motherboard or other higher-level carrier) or in a multi-chip package (e.g., a ceramic substrate with surface and / or buried interconnects). In each case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) a final product.The end product can be any product that incorporates integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with a display, keyboard or other input device, and a central processing unit.

[0042] The terminology used herein serves only to describe certain embodiments and is not to be considered as limiting the invention. The singular forms "a", "an", "one", and "the" used herein also include the plural forms unless the context clearly indicates otherwise. Furthermore, it is understood that the terms "comprises" and / or "comprehensive," when used in this description, specify the presence of the indicated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.“Optional” or “possible” means that the event or circumstance described below may or may not occur, and that the description includes instances in which the event occurs and instances in which it does not occur.

[0043] An imprecise language, such as that used throughout this description and the claims, may be used to modify any quantitative representation that could permissibly vary without altering the fundamental function to which it refers. Accordingly, a value modified by one or more terms such as "approximately," "approximately," and "essentially" is not limited to the exact value stated. At least in some cases, the imprecise language may correspond to the accuracy of an instrument used to measure the value. Here, and throughout this specification and the claims, range boundaries may be combined and / or interchanged; such ranges are identified and include all subranges contained therein unless the context or language indicates otherwise.“Approximately”, as applied to a specific value of a range, applies to both values ​​and, unless otherwise dependent on the precision of the measuring instrument, can mean + / - 10% of the stated value(s).

[0044] The corresponding structures, materials, actions and equivalents of all means or step-plus-function elements in the claims below are to be understood as comprising any structure, material or action for performing the function in combination with other claimed elements, as specifically claimed.

[0045] The description of the present invention is provided for illustrative and descriptive purposes only and does not claim to be exhaustive or limited to the invention as disclosed. Many modifications and variations will be obvious to those skilled in the art without altering the scope and spirit of the invention. The embodiment has been chosen and described to best explain the principles of the invention and its practical application, and to enable other skilled persons to understand the invention in various embodiments with different modifications, as appropriate for the intended use.

Claims

[1] E-Fuse (100), comprising: a fuse insert (140) with a siliciated semiconductor layer (142) over a dielectric layer (120) covering a gate conductor (116), wherein the siliciated semiconductor layer (142) is not planar; a first connection (150) which is electrically coupled to a first end (152) of the fuse link (140); and a second terminal (154) which is electrically coupled to a second end (156) of the fuse insert (140), wherein the siliciated semiconductor layer (142) comprises a semiconductor layer (122) and a silicide layer (144) formed thereon, wherein an intrinsic basis and / or an extrinsic basis of a bipolar transistor (158) is formed in the semiconductor layer (122). [2] E-Fuse (100) according to claim 1, wherein the silicidal semiconductor layer (142) comprises a dopant. [3] E-Fuse (100) according to claim 1, wherein the silicidal semiconductor layer (142) comprises silicon or silicon germanium. [4] E-Fuse (100) according to claim 1, wherein the gate conductor (116) is part of a transistor configured to electrically couple a current source to the first terminal (150) for programming the e-Fuse (100), wherein the second terminal (154) is electrically coupled to ground. [5] E-Fuse (100) according to claim 1, wherein the gate conductor (116) is not operational. [6] E-Fuse (100) according to claim 1, wherein the gate conductor (116) is a resistor. [7] E-Fuse (100) according to claim 1, wherein the fuse insert (140) has at least one lateral curve therein. [8] E-Fuse (100) according to claim 7, wherein the fuse insert (140) extends more than once orthogonally over the gate conductor (116). [9] E-Fuse (100) according to claim 1, wherein the fuse insert (140) comprises the silicided semiconductor layer (142) over the dielectric layer (120) covering a plurality of gate conductors (116), such that the fuse insert (140) comprises a number of peaks and valleys. [10] E-Fuse (100) according to claim 1, wherein the silicided semiconductor layer (142) extends orthogonally over the gate conductor (116). [11] Integrated circuit comprising: a bipolar transistor (158) with an intrinsic basis and an extrinsic basis; a CMOS transistor (168); and an e-fuse (100), comprising: a non-planar fuse insert (140) comprising a siliciated semiconductor layer (142) over a dielectric layer (120) covering a gate conductor (116), wherein the siliciated semiconductor layer (142) extends orthogonally over the gate conductor (116); a first connection (150) which is electrically coupled to a first end (152) of the non-planar fuse link (140); and a second connection (154) which is electrically coupled to a second end (156) of the non-planar fuse insert (140), wherein the siliciated semiconductor layer (142) comprises a semiconductor layer (122) and a silicide layer (144) formed thereon, wherein at least one of the intrinsic basis and the extrinsic basis of the bipolar transistor (158) is formed in the semiconductor layer (122). [12] Integrated circuit according to claim 11, wherein the silicided semiconductor layer (142) comprises a dopant. [13] Integrated circuit according to claim 11, wherein the silicided semiconductor layer (142) comprises silicon or silicon germanium. [14] Integrated circuit according to claim 11, wherein the gate conductor (116) is part of the CMOS transistor (168) and wherein the CMOS transistor (168) is configured to electrically couple a current source with the non-planar fuse insert (140) for programming the e-fuse (100). [15] Integrated circuit according to claim 11, wherein the gate conductor (116) is a resistor. [16] Integrated circuit according to claim 11, wherein the non-planar fuse insert (140) has at least one lateral curve therein. [17] Integrated circuit according to claim 16, wherein the non-planar fuse insert (140) extends more than once orthogonally over the gate conductor (116). [18] Integrated circuit according to claim 11, wherein the non-planar fuse insert (140) comprises the silicided semiconductor layer (142) over the dielectric layer (120) covering a plurality of gate conductors (116), such that the non-planar fuse insert (140) comprises a plurality of peaks and valleys. [19] Procedures, including: forming a semiconductor layer (122) for an intrinsic basis and / or an extrinsic basis for a bipolar transistor and over a dielectric layer (120) over a gate conductor (116); structuring the semiconductor layer (122) so that it extends orthogonally over the gate conductor (116); a forming of a fuse insert (140) for an electrical fuse by silicifying the semiconductor layer over the dielectric layer (120) over the gate conductor (116), wherein the silicified semiconductor layer (142) is not planar over the gate conductor (116); and a formation of the electrical fuse by forming a first connection (150) which is electrically connected to a first end (152) of the fuse connection, and a second terminal (154) which is electrically connected to a second end (156) of the fuse insert (140).

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