NFET WITH ALUMINUM-FREE EXPLOITATION WORKING LAYER AND ITS MANUFACTURING PROCESS

DE102022101976B4Active Publication Date: 2026-07-16TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
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Patent Information

Application Number
DE102022101976
Authority / Receiving Office
DE · DE
Patent Type
Patents
Current Assignee / Owner
Priority Date
2022-01-17
Filing Date
2022-01-28
Publication Date
2026-07-16
Estimated Expiration
2042-01-28

AI Technical Summary

Technical Problem

As semiconductor devices continue to shrink in size to increase integration density, the reliability of gate stacks in transistors is compromised by the presence of aluminum, leading to issues such as reduced time-dependent dielectric breakdown (TDDB).

Method used

The development of an aluminum-free work function layer in gate stacks for n-type transistors, comprising a metal-containing layer and a silicon layer, is achieved through in-situ deposition to enhance reliability and reduce gate resistance.

Benefits of technology

The aluminum-free gate stacks improve the reliability of transistors by reducing gate resistance and minimizing oxidation of the silicon layer, thereby enhancing the performance and longevity of semiconductor devices.

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Abstract

Method comprising: forming a dummy gate stack (30) over a semiconductor region (20); forming a source / drain region (48) on one side of the dummy gate stack (30); removing the dummy gate stack (30) to form a trench (58); depositing a dielectric gate layer (62) extending into the trench (58); depositing a metal-containing layer (64A) over and in direct contact with the dielectric gate layer (62); depositing a silicon-containing layer (64B) on top of the metal-containing layer (64A), the metal-containing layer (64A) and the silicon-containing layer (64B) together serving as an exit working layer (64);and performing a planarization process to remove excess parts of the silicon-containing layer (64B), the metal-containing layer (64A) and the dielectric gate layer (62), wherein remaining parts of the silicon-containing layer (64B), the metal-containing layer (64A) and the dielectric gate layer (62) form a gate stack (70), wherein after deposition of the metal-containing layer (64A) and before deposition of the silicon-containing layer (64B) the metal-containing layer (64A) itself has a p-work function, and wherein the source / drain region (48) is n-conducting.
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Citation Information

Patent Citations

  • Semiconductor device and method of manufacturing semiconductor device

    CN113053753A

  • CN000113053753A