DIELECTRIC BLOCKING LAYER AND METHOD FOR ITS MANUFACTURING

Abstract

Method comprising: manufacturing a first package component (20) comprising the following steps: manufacturing a first dielectric layer (70) having a first top surface; manufacturing a first conductive structural element (76) having a via (80) extending into the first dielectric layer (70) and a metal contact mound (82) having a second top surface that is higher than the first top surface of the first dielectric layer (70); depositing a photosensitive layer (84) having the photosensitive layer (84) covering the metal contact mound (82); and performing a photolithography process to produce a recess (90) in the photosensitive layer (84), exposing the metal contact mound (82) to the recess (90) and the photosensitive layer (84) having a third top surface that is higher than the metal contact mound (82);and bonding a second package component (94) to the first package component (20), wherein a solder area (98) extends into the recess (90) to bond the metal contact mound (82) to a second conductive structural element (96) in the second package component (94), wherein the recess (90) extends laterally beyond edges of the metal contact mound (82).

Description

Priority claim and cross-reference

[0001] The present application claims priority over the preliminary US patent application filed on June 15, 2022, with file number 63 / 366.438 and entitled “Ultra Fine Pitch Bump Interconnection”, which is incorporated by reference into the present application. background

[0002] In the fabrication of integrated circuits, package components, such as transistors, are manufactured on the surface of a semiconductor substrate in a wafer. Metal contact mounds can be fabricated on the wafer's surface. In a packaging process, upper dies can be bonded to a lower wafer via solder areas. The lower wafer can then be sawn into dies. However, this fabrication process can present challenges when reducing the distances between the metal contact mounds. For example, the probability of solder bridging between adjacent metal contact mounds increases as the distances decrease. Brief description of the drawings

[0003] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. Rather, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. The Fig. 1 to Fig. 13 and Fig. Figure 14A shows sectional views of intermediate stages in the manufacture of a package with sawn-off device dies according to some embodiments. Fig. Figure 14B shows a sectional view of a package containing a newly configured wafer according to some embodiments. Fig. Figure 15 shows a sectional view of a package according to some embodiments. Fig. Figure 16 shows a top view of a package according to some embodiments. Fig. Figure 17 shows a process flow for manufacturing a package according to some embodiments. Detailed description

[0004] The disclosure below provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element above or on top of a second element in the description below may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present disclosure.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0005] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of one element or structural element to one or more other elements or structural elements depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90° or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0006] A package component and a method for its fabrication are provided. According to some embodiments of the present disclosure, a package comprises a first package component (such as a device die) bonded to a second package component. The first package component has a metal contact mound that extends beyond a dielectric surface layer of the first package component. A photosensitive polymer is then deposited onto the metal contact mound and the dielectric surface layer and subsequently exposed and developed, creating a recess in the photosensitive polymer that exposes the metal contact mound. The metal contact mound is bonded to the second package component by a solder area. The recess serves to receive the solder area and prevents the solder from bridging adjacent solder areas.The embodiments discussed herein are intended to provide examples of how the subject matter of the present disclosure may be manufactured or used, and a person skilled in the art should readily recognize modifications that may be made without deviating from the intended scope of protection of different embodiments. In all illustrations and explanatory embodiments, similar reference numerals are used to denote similar elements. Furthermore, some method embodiments may be discussed as embodiments that are carried out in a particular sequence, but other method embodiments may be carried out in any logical sequence.

[0007] The Fig. 1 to Fig. 13 and Fig. Figure 14A shows sectional views of intermediate stages in the manufacture of a package according to some embodiments of the present disclosure. The corresponding processes are also schematically indicated in a process flow 200, which is presented in Fig. 17 is shown.

[0008] Fig. Figure 1 shows a sectional view of a package component 20. In some embodiments, the package component 20 is (or comprises) a device wafer with active devices and optionally passive devices, which are depicted as integrated circuit devices 26. The package component 20 may contain a plurality of chips 22, also referred to as (device) dies, with only one of the device dies 22 being shown. In alternative embodiments, the package component 20 is an interposer wafer that does not contain any active devices and may or may not contain passive devices. In still further embodiments, the package component 20 is (or comprises) a package substrate strip comprising coreless package substrates and package substrates with cores.In the following discussion, a device wafer is used as an example for the package component 20, and the package component 20 is accordingly referred to as a wafer 20.

[0009] According to some embodiments of the present disclosure, the wafer 20 comprises a semiconductor substrate 24 and structural elements fabricated on a top surface of the semiconductor substrate 24. The semiconductor substrate 24 may be made of or comprise crystalline silicon, crystalline germanium, silicon germanium, carbon-doped silicon, or a III-V compound semiconductor such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or the like. The semiconductor substrate 24 may also be a solid semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. Shallow trench isolation (STI) regions may be created in the semiconductor substrate 24 to isolate the active regions within the semiconductor substrate 24.Although not shown, vias can be manufactured (or not) to extend into the semiconductor substrate 24, with the vias being used to electrically connect the structural elements on opposite sides of the semiconductor substrate 24.

[0010] In some embodiments, the wafer 20 has integrated circuit devices 26 fabricated on the top surface of the semiconductor substrate 24. In some embodiments, the integrated circuit devices 26 may be transistors, resistors, capacitors, diodes, and the like. The details of the integrated circuit devices 26 are not described here. In alternative embodiments, the wafer 20 is used to fabricate interposers (which do not have active devices), and the substrate 24 may be a semiconductor substrate or a dielectric substrate.

[0011] An interlayer dielectric (ILD) 28 is fabricated over the semiconductor substrate 24 and fills the spaces between gate stacks of transistors (not shown) in the integrated circuit devices 26. In some embodiments, the ILD 28 is made of phosphosilicate glass (PSG), borosilicate glass (BSG), boron phosphosilicate glass (BPSG), fluorosilicate glass (FSG), silicon oxide, silicon oxide nitride, silicon nitride, a low-k dielectric material, or the like. The ILD 28 can be fabricated by spin coating, flowable chemical vapor deposition (FCVD), or the like. In some embodiments, the ILD 28 is fabricated by a deposition process such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or the like.

[0012] In the ILD 28, contact pins 30 are manufactured for electrically connecting the integrated circuit devices 26 to higher-level metal traces and vias. In some embodiments, the contact pins 30 are made of (or comprise) a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium niride, tantalum nitride, alloys thereof, and / or multilayers thereof. The fabrication of the contact pins 30 may include: creating contact openings in the ILD 28; filling the contact openings with one or more conductive materials; and performing a planarization process, such as a CMP process (CMP: chemical-mechanical polishing) or a machine grinding process, to bring the top surfaces of the contact pins 30 to the same level as the top surface of the ILD 28.

[0013] An interconnect structure 32 is fabricated above the ILD 28 and the contact pins 30. The interconnect structure 32 comprises metal conductors 34 and vias 36 fabricated in dielectric layers 38, also referred to as intermetal dielectrics (IMDs). Metal conductors on the same layer are collectively referred to below as a metal layer. In some embodiments, the interconnect structure 32 comprises a plurality of metal layers with metal conductors 34 interconnected by vias 36. The metal conductors 34 and the vias 36 can be made of copper or copper alloys, or of other metals. In some embodiments, the dielectric layers 38 are fabricated from low-k dielectric materials. The dielectric constants (k-values) of the low-k dielectric materials can be, for example, lower than approximately 3.0.The dielectric layers 38 can contain a carbon-containing dielectric low-k material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), or the like. In some embodiments, the dielectric layers 38 are produced by depositing a porous dielectric material into the dielectric layers 38 and subsequently performing a curing process to drive out the porous material, leaving the remaining dielectric layers 38 porous.

[0014] Single-damascene and / or dual-damascene processes can be used to fabricate the metal conductors 34 and the vias 36 in the dielectric layers 38. The damascene structures can each have a diffusion barrier layer and a copper-containing metallic material above the diffusion barrier layer. The diffusion barrier layer can contain titanium, titanium nitride, tantalum, tantalum nitride, or the like.

[0015] The metal conductors 34 comprise upper conductive (metallic) structural elements (designated 34A), such as metal conductors, metal pads, or vias. The upper conductive structural elements 34A are arranged in an upper dielectric layer (designated as a dielectric layer 38A), which is the uppermost layer of the dielectric layers 38. In some embodiments, the upper dielectric layer 38A is made of a non-low-k dielectric material, which may include silicon nitride, undoped silicate glass (USG), silicon oxide, or the like, or multiple layers thereof. In alternative embodiments, the dielectric layer 38A is made of a low-k dielectric material similar to the material of the lower dielectric layers 38. The dielectric layer 38A may also have a multilayer structure, for example, comprising two USG layers with a silicon nitride layer in between.The upper metallic structural elements 34A can also be made of copper or a copper alloy and can have a dual damascene structure or a single damascene structure.

[0016] A passivation layer 40 (occasionally referred to as "Passivation-i" or "Pass-1") is produced above the interconnect structure 32. The corresponding process is specified as process 202 in process flow 200, which is described in Fig. Figure 17 shows that in some embodiments, the passivation layer 40 is made of a non-low-k dielectric material having a dielectric constant that is higher than or equal to that of silicon oxide. The passivation layer 40 can be made of (or comprise) an inorganic dielectric material selected from, among others, silicon nitride (SiN), silicon oxide (SiO2), silicon oxide nitride (SiON), silicon oxide carbide (SiOC), silicon carbide (SiC), USG, or the like, combinations thereof, and multilayers thereof.

[0017] The passivation layer 40 is structured in an etching process, and vias 42 are produced in the passivation layer 40 to contact metal conductors / pads 34A. In some embodiments, the vias 42 can be produced using a single damascene process, or they can be produced together with metal pads 44.

[0018] Metal pads 44 are manufactured above and in contact with the vias 42. The corresponding process is specified as process 204 in process flow 200, which is described in Fig. Figure 17 shows that the metal pads 44 can be electrically connected to the integrated circuit devices 26 by conductive structural elements, such as the metal conductors 34 and the vias 36. In some embodiments, the metal pads 44 are aluminum pads or aluminum-copper pads, but other metallic materials can also be used. In some embodiments, the metal pads have an aluminum atom content higher than approximately 90% or 95%.

[0019] In Fig. 2. A passivation layer 46 is produced on the metal pads 44. The passivation layer 46 can be a single layer or a composite layer, and it can be made of a non-porous material. In some embodiments, the passivation layer 46 is a composite layer comprising a silicon oxide layer and a silicon nitride layer over the silicon oxide layer. The passivation layer 46 is then structured by an etching process to create openings 47, so that the passivation layer 46 can cover some parts of the metal pads 44, while other parts of the top surfaces of the metal pads 44 are exposed by the openings 47.

[0020] Fig. Figure 3 shows the fabrication of a dielectric layer 48. In some embodiments, the dielectric layer 48 comprises a polymer, which may be a polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), or the like. Accordingly, the dielectric layer 48 is alternatively referred to as a polymer layer 48, but it may also be fabricated from or comprise other dielectric materials, such as inorganic dielectric materials. The corresponding process is specified as process 206 in process flow 200, which is described in Fig. Figure 17 shows that the polymer layer 48 can be produced by centrifugal coating followed by curing. Openings 50 are created in the polymer layer 48, for example, by an exposure process and a subsequent development process.

[0021] The Fig. 4 to Fig. Figure 6 shows the fabrication of vias and higher-level conductive pads. Fig. 4. A metallic seed layer 54 is deposited over the polymer layer. The corresponding process is specified as process 208 in process sequence 200, which is described in Fig. Figure 17 shows that the metallic seed layer 54 is a conductive seed layer and can be a metallic seed layer. In some embodiments, the metallic seed layer 54 is a composite layer with two or more layers. The metallic seed layer 54 can have a bottom layer and an top layer, the bottom layer being a titanium layer, a titanium nitride layer, a tantalum layer, a tantalum nitride layer, or the like. The materials for the top layer can be copper or a copper alloy. In alternative embodiments, the metallic seed layer 54 is a single layer, which can be, for example, a copper layer. The metallic seed layer 54 can be produced by physical vapor deposition (PVD), plasma-enhanced electrochemical vapor deposition (PECVD), atomic layer deposition (ALD), or the like, but other suitable methods can also be used.The metallic seed layer 54 is a conformal layer that extends into the openings 50.

[0022] Fig. Figure 4 also shows the production of a structured plating mask 56. The corresponding process is specified as process 210 in process flow 200, which is in Fig. Figure 17 shows that in some embodiments, the plating mask 56 is made of or incorporates a photoresist. The plating mask 56 is structured to create openings 58 through which some parts of the metallic seed layer 54 are exposed. The structuring of the plating mask 56 may include an exposure process and a development process.

[0023] Fig. Figure 5 shows the plating of a conductive material / conductive structural elements 60 in the openings 58 and on the metallic seed layer 54. The corresponding process is specified as process 212 in process sequence 200, which is described in Fig. Figure 17 shows that in some embodiments, the conductive structural elements 60 are manufactured by a plating process, which may be an electrochemical plating process, a currentless plating process, or the like. The plating may be carried out in a chemical electrolyte liquid. The conductive structural elements 60 may comprise copper, aluminum, nickel, tungsten, or the like, alloys thereof, and / or multilayers thereof. In some embodiments, the conductive structural elements 60 comprise copper and do not contain aluminum.

[0024] As in Fig. As shown in Figure 5, the plating mask 56 is then removed, and the deeper parts of the metallic seed layer 54 are exposed. Subsequently, an etching process is carried out to remove the exposed parts of the metallic seed layer 54. The corresponding process is specified as process 214 in process flow 200, which is shown in Fig. Figure 17 shows the resulting structure. Fig. Figure 6 shows. Throughout this description, the conductive material 60 and the corresponding underlying portions of the metallic seed layer 54 are collectively referred to as redistribution lines (RDLs) 62. The RDLs 62 may include vias 64 (also referred to as vias or conductive vias) extending into the polymer layer 48 and pad portions 66 (also referred to as conductive pads or metal pads) above the polymer layer 48. In some embodiments, the conductive pads 66 have planar top surfaces. In alternative embodiments, the top surfaces of the conductive pads 66 have depressions directly above the respective conductive vias 64 due to the plating process, with dashed lines 67 being used to represent the surfaces of the conductive pads 66.

[0025] Fig. Figure 7 shows the fabrication of a dielectric layer 70. In some embodiments, the dielectric layer 70 is an (organic) polymer layer made of (or incorporating) a polymer (which may be photosensitive), such as a polyimide, PBO, BCB, an epoxy, or the like. The corresponding process is shown as process 216 in process flow 200, which is described in Fig. Figure 17 shows that in some embodiments, the production of the dielectric layer 70 involves depositing the dielectric layer in a flowable form and subsequently performing a hardening process to cure the dielectric layer 70. To level the top surface of the dielectric layer 70, a planarization process, such as a CMP process or a machine grinding process, may (or may not) be performed. Accordingly, the dielectric layer 70 is also referred to as a planarization layer. In alternative embodiments, no planarization process is performed, and the top surface of the dielectric layer 70 may have a topology that reflects the topology of the underlying structural elements.For example, the parts of the dielectric layer 70 directly above the conductive pads 66 can have top surfaces that are higher than the top surfaces of the surrounding parts of the dielectric layer 70.

[0026] In a subsequent process, the dielectric layer 70 is structured, for example by an exposure process and a photodevelopment process. This creates openings 72 in the dielectric layer 70, and the conductive pads 66 are exposed. After the photodevelopment process, the dielectric layer 70 is also post-cured so that it is not restructured when it receives light again in a later process, which is used to expose a photosensitive layer 84 ( Fig. 9).

[0027] Fig. Figure 8 shows the fabrication of subsurface metallizations (UBMs) and the fabrication of conductive pillars and solder regions (if fabricated) according to some embodiments. The corresponding process is specified as process 218 in process flow 200, which is described in Fig. Figure 17 shows that in an exemplary manufacturing process, a metallic seed layer 74 is deposited as a protective layer, wherein Fig. Figure 8 shows some remaining parts of the protective seed layer 74. In some embodiments, the metallic seed layer 74 has a titanium layer and a copper layer over the titanium layer. In alternative embodiments, the entire metallic seed layer 74 is made of a homogeneous material such as copper or a copper alloy, the homogeneous material being in contact with the dielectric layer 70 and the top surface of the conductive pads 66. The metallic seed layer 74 can be produced by PVD, ALD, or the like.

[0028] Then, a conductive material 76 is plated. The process for cladding the conductive material 76 can include fabricating a structured plating mask (not shown) and plating the conductive material 76 into openings in the structured plating mask. The structured plating mask can be a photoresist and can be a one-, two-, or three-layer plating mask. The conductive material 76 can comprise copper, nickel, palladium, aluminum, alloys thereof, and / or multilayers thereof. In some embodiments, solder layers are also plated onto the conductive material 76 and into the openings in the structured plating mask. Subsequently, the structured plating mask is removed.

[0029] In some embodiments, solder layers 78 are plated over the conductive material 76. The plating is performed using the same plating mask as for plating the material 76. In alternative embodiments, no solder layer is plated. The solder layers 78 are shown with dashed lines to indicate whether or not they may be produced.

[0030] The metallic protective seed layer 74 is then etched, and the portions of the metallic seed layer 74 exposed after removal of the plating mask are removed, while the portions of the metallic seed layer 74 located directly beneath the conductive material 76 remain. The resulting structure is in Fig. Figure 8 shows the remaining portions of the metallic seed layer 74, also referred to as UBMs 74. The UBMs 74 and the conductive material 76 together form vias 80 and electrical connecting elements 82. In the following discussion, the electrical connecting elements 82 are also referred to as metal contact mounds 82. The metal contact mounds 82 protrude above the top surface of the dielectric layer 70. In some embodiments, where the solder layers 78 are also produced, a remelting process can be carried out after etching the metallic seed layer, so that the solder layers 78 have convex surfaces.

[0031] In Fig. 9. A dielectric layer 84 is produced. The dielectric layer 84 can be a photosensitive layer containing a photosensitive polymer such as polyimide, PBO, BCB, or the like. The dielectric layer 84 is applied to the UBMs 74 by spin coating. The corresponding process is specified as process 220 in process sequence 200, which is described in Fig. Figure 17 is shown. After application, the photosensitive layer 84 is pre-cured to drive out the solvent contained therein.

[0032] A top surface of the photosensitive layer 84 is higher than the top surfaces of the metal contact bumps 82. Since the metal contact bumps 82 project above the top surface of the dielectric layer 70, it is clear that the top surface of the photosensitive layer 84 may not be planar and that the portions of the photosensitive layer 84 located directly above the metal contact bumps 82 may be higher than other portions. In some embodiments, the top surface of the photosensitive layer 84 is planarized in a polishing process, such as a CMP process and / or a machine grinding process. This makes the entire top surface of the photosensitive layer 84 planar. In alternative embodiments, the planarization process is not performed. Consequently, the top surface of the photosensitive layer 84 has higher (raised) portions directly above the metal contact bumps 82 and lower portions that are laterally offset from the metal contact bumps 82.

[0033] In alternative embodiments, the dielectric layer 84 can be an inorganic dielectric layer containing silicon oxide, silicon nitride, silicon oxide nitride, silicon carbide, silicon oxide carbide, or the like. Accordingly, the layer 84 is structured by processes that include fabricating a structured etch mask (such as a photoresist) over the dielectric layer 84 and subsequently etching the dielectric layer 84 using the structured etch mask to define structures.

[0034] In some embodiments where the dielectric layer 84 contains a photosensitive material, an exposure process 88 is carried out to expose the photosensitive layer 84. The corresponding process is specified as process 222 in the process sequence 200, which is described in Fig. Figure 17 shows that the exposure process 88 is carried out using a lithographic mask 86 which has transparent structures 86A that allow light to pass through and opaque structures 86B that block the light. The photosensitive layer 84 can be made from a positive photosensitive material, with the exposed areas being removed during development while the unexposed areas remain. Alternatively, the photosensitive layer 84 can be made from a negative photosensitive material, with the unexposed areas being removed during development while the exposed areas remain. Fig. Figure 9 shows an example in which the photosensitive layer 84 is positive and the transparent structures 86A are located in the lithographic mask 86 directly above the metal contact hills 82. In other embodiments, a negative photosensitive layer 84 can be used, and the transparent and opaque structures are located in the Fig. The 9 structures shown are in contrast.

[0035] In the illustrated example, the structures 86A directly above the metal contact mounds 82 have transverse dimensions W2 that are larger than the transverse dimensions W1 of the metal contact mounds 82. Furthermore, the structures 86A can extend laterally beyond the edges of the metal contact mounds 82 in all transverse directions (viewed from above) that are parallel to the top surface of the photosensitive layer 84. In alternative embodiments, the structures 86A can extend laterally beyond the edges of the metal contact mounds 82 in some, but not all, transverse directions that are parallel to the top surface of the photosensitive layer 84.

[0036] In alternative embodiments, the edges of the structures 86A can be aligned vertically to the respective edges of the metal contact mounds 82, so that subsequently generated recesses 90 (see Fig. 10) have boundaries that are oriented vertically to the respective edges of the lower-lying metal contact mounds. In further embodiments, the edges of the structures 86A can be recessed laterally relative to the respective edges of the metal contact mounds 82, so that the subsequently created recesses 90 ( Fig. 10) have boundaries which are laterally recessed relative to the respective edges of the lower metal contact hills, and thus the transverse dimensions of the recesses are smaller than the transverse dimensions of the lower metal contact hills 82.

[0037] In Fig. In step 10, the exposed photosensitive layer 84 is developed, and recesses 90 are created in the photosensitive layer 84, exposing the metal contact mounds 82. The corresponding process is specified as process 224 in process sequence 200, which is described in Fig. Figure 17 shows that in some embodiments, the undersides 90BS1 of the recesses 90 are coplanar (or substantially coplanar, for example with a height difference of less than about 1 µm or about 0.5 µm) with the tops of the metal contact mounds 82. Accordingly, some portions of the photosensitive layer 84 are located directly beneath the recesses 90. This can be achieved by controlling the depth of field, the light intensity, the exposure time, and / or the like during the exposure process.

[0038] In alternative embodiments, the underside of the photosensitive layer 84 is lower than the upper surfaces of the metal contact mounds 82 and higher than an upper surface 70TS of the dielectric layer 70. This can also be achieved by controlling the depth of field in the exposure process, controlling the light intensity, controlling the exposure time, and / or the like. The undersides of the respective recesses 90 are shown by dashed lines 90BS2.

[0039] In further embodiments, the top surface 70TS of the dielectric layer 70 is exposed to the recesses 90. The corresponding undersides of the recesses 90 are designated 90BS3. Side walls of the corresponding recesses 90 are designated 90SW. Since the dielectric layer 70 has been pre-cured, it is no longer affected by the exposure and development processes for structuring the photosensitive layer 84. Accordingly, the dielectric layer 70 can be used for the exposure process 88 ( Fig. 9) Although light is received, the top surface 70TS of the dielectric layer 70 is not recessed even when the dielectric layer 70 is exposed to the recesses 90.

[0040] As explained above, the photosensitive layer 84 may or may not be planarized. In embodiments where the photosensitive layer 84 is planarized, its top surface (except for the top surface below the recesses 90) is planar and is shown as top surface 84TS1. In alternative embodiments where the photosensitive layer 84 is not planarized, top surfaces 84TS2 of the portions of the photosensitive layer 84 enclosing the recesses 90 may be raised so that they are higher than the top surfaces 84TS1 of the portions of the photosensitive layer 84 between the raised portions. The raised top surfaces 84TS2 are shown by dashed lines. The top surfaces 84TS1 and 84TS2 are also recognizable in the final package shown in the Fig. 14A, Fig. 14B and Fig. Figure 15 is shown. In later figures, the raised top surface 84TS2 may only be shown for one of the recesses 90, but other recesses 90 may also have raised top surfaces 84TS2.

[0041] In Fig. In Figure 11, a package component 94 is aligned with the wafer 20. Although only one package component 94 is shown, multiple package components 94 may be present, each bonded to one of the device dies 22. In some embodiments, a dielectric layer 95 is fabricated on a surface of the package component 94. The dielectric layer 95 may be made of a solder mask, an organic dielectric material, an inorganic dielectric material, or the like. In some embodiments, the package component 94 is or incorporates a device die (containing active devices), an interposer, a package substrate, a printed circuit board, a package, or the like. Throughout this description, the package component 94 is also referred to as an upper die.The package component 94 has electrical connection elements 96, which can be metal pillars (such as copper pillars), bond pads, or the like. The electrical connection elements 96 are fabricated on the surface of the package component 94 and may or may not protrude beyond the underside of the dielectric layer 95. Solder areas 98 are created on the electrical connection elements 96. The solder areas 98 and the electrical connection elements 96 are aligned with the metal contact mounds 82 in an alignment process.

[0042] The package component 94 is then placed on the fixture die 22 in the wafer 20. The solder areas 98 are inserted into the recesses 90. A melting process is then performed to melt the solder areas 98 and the solder layers 78 (if present), so that the package component 94 is bonded to the fixture die 22. The corresponding process is specified as process 226 in the process flow 200, which is described in Fig. Figure 17 shows that the resulting perpendicular regions are called perpendicular regions 98', which are shown in Figure 17. Fig. Figure 12 shows that the bonding process is self-adjusting due to the limitation of the solder areas 98' and the electrical connecting elements 96 by the side walls of the recesses 90.

[0043] After the solder areas 98' have solidified, the undersides of the electrical connectors 96 can be higher than, at the same level as, or lower than the top surfaces 84TS1 and / or 84TS2 of the photosensitive layer 84. If the undersides of the electrical connectors 96 are lower than the top surface 84TS2 of the photosensitive layer 84, the lower parts of the electrical connectors 96 are also inserted into the recesses 90.

[0044] In Fig. In step 13, an underfill 102 is distributed between wafer 20 and package component 94. The corresponding process is specified as process 228 in process flow 200, which is described in Fig. Figure 17 shows that in some embodiments, the underfill 102 partially or completely fills the recesses 90. For example, the upper parts of the recesses 90, which are not occupied by the solder areas 98', can be filled with the underfill 102. If the solder areas 98' prevent the underfill 102 from flowing into the lower parts of the recesses 90, the lower parts of the recesses 90 may be air gaps. Otherwise, the lower parts of the recesses 90 are also filled with the underfill 102.

[0045] In a subsequent process, an encapsulation material 104 is applied to encapsulate the package component 94, as shown in Fig. 14A is shown. The corresponding process is specified as process 230 in process flow 200, which is shown in Fig. shown in 17. This results in a newly configured wafer 106. In some embodiments, which are also shown in Fig. As shown in Figure 14A, the newly configured wafer 106 is sawn along scoring grooves 108 to separate it into individual packages 106'. The corresponding process is specified as process 222 in process flow 200, which is shown in Fig. Figure 17 shows that the separate packages 106' are identical and each contains the device die 22 and the package component 94. In the resulting packages 106', the edges of the encapsulation material 104 are oriented vertically to the edges of the device dies 22.

[0046] As described in the preceding embodiments, the recesses 90 can have undersides that are at the same level as, or lower than, the topsides of the metal contact mounds 82. Furthermore, the topside of the dielectric layer 70 may or may not be exposed to the recesses 90. In some embodiments, the undersides of all recesses 90 lie in the same plane. In alternative embodiments, the undersides of the recesses 90 can lie in different planes within the same device die (and the same wafer 20).

[0047] Fig. Figure 14A shows four possible bond structures 110A, 110B, 110C, and 110D, each featuring the metal contact mound 82, the solder area 98', the electrical connection element 96, and the recess 90. A single package 96' (and a single reconfigured wafer 96) can each exhibit one or more of the bond structures 110A, 110B, 110C, and 110D in any combination. The different bond structures within the same package / wafer may be caused by process variation or may be intentionally produced.It should also be noted that the elements shown in bond structures 110A, 110B, 110C, and 110D are some of several possible combinations of elements, including, but not limited to, the undersides of the recesses 90, regardless of whether the solder areas 98' contact the sidewalls of the photosensitive layer 84, extend onto the sidewalls of the metal contact mounds 82, or extend onto the sidewalls of the electrical connecting elements 96. All other possible combinations are also considered whenever feasible.

[0048] In the bond structure 110A, the underside of the recess 90 can lie in a plane designated 90BS1, 90BS2, and 90BS3. A portion of the solder area 98' is arranged above and in contact with the top surface of the metal contact mound 82. The solder area 98' is also arranged below and in contact with the underside of the electrical connection element 96 and may or may not extend onto the side walls of the electrical connection element 96.

[0049] In bond structure 110B, the underside of recess 90 can be located between the top surface of metal contact mound 82 and the top surface 70TS of dielectric layer 70. In some embodiments, the entire solder area 98' is located above the metal contact mound 82. In alternative embodiments, as shown, the solder area 98' extends below the top surface of metal contact mound 82 and contacts the side walls of metal contact mound 82. The solder area 98' can also contact the underside and side walls of electrical connector 96, or it can be limited to the area below the underside of electrical connector 96. The solder area 98' may or may not extend to the side walls of the photosensitive layer 84 that are exposed to the recesses 90.

[0050] In the bond structure 110C, the solder area 98' is spaced from the side walls of the photosensitive layer 84. Recesses 90 extend to the top of the dielectric layer 70, or they may extend deeper, as indicated by dashed lines. The solder area 98' contacts the top of the metal contact mound 82, and it may (or may not) contact the side walls of the metal contact mound 82 to create vertical interfaces. The solder area 98' may also contact the bottom of the electrical connector 96, and it may or may not contact the side walls of the electrical connector 96.

[0051] In the bond structure 110D, the top surface 70TS of the dielectric layer 70 is exposed to the recess 90. The solder area 98' contacts the side walls of the metal contact mound 82 to create vertical interfaces. The solder area 98' can extend up to the top surface 70TS or be higher than it. The solder area 98' is also located below and in contact with the underside of the electrical connecting element 96.

[0052] Fig. Figure 14B shows a newly configured wafer 106 according to alternative embodiments. In this embodiment, the resulting packages are used at the wafer level. For example, in high-performance applications, such as AI (artificial intelligence) applications, the newly configured wafer 106 is used unsawled and can be mounted on a fixture. It is also powered when not sawn. In the newly configured wafer 106, the encapsulation material 104 can contact the sidewalls of the wafer 20.

[0053] Fig. Figure 15 shows a newly configured wafer 96 and sawn packages 96' according to alternative embodiments. In these embodiments, the package component 94 can comprise a dielectric layer 170, a metal contact mound 182, a photosensitive layer 184, and recesses 190. The structures, materials, and fabrication processes for the dielectric layer 170, the metal contact mound 182, the photosensitive layer 184, and the recesses 190 can be the same as for the corresponding dielectric layer 70, metal contact mound 82, photosensitive layer 84, and recesses 90 in the wafer 20, and therefore the details are not repeated here. The relationship between the dielectric layer 170, the metal contact hill 182, the photosensitive layer 184 and the recesses 90 may also be similar to that which has been described for the bond structures 110A, 110B, 110C and 110D.In some embodiments, the recesses 190 are aligned with the corresponding lower recesses 90, and they may have transverse dimensions that are equal to, greater than, or smaller than the transverse dimensions of the corresponding lower recesses 90.

[0054] In some embodiments, which are in the Fig. 14A, Fig. 14B and Fig. As shown in Figure 15, the newly configured wafer 106 and the packages 106' have the dielectric layer 70 and the photosensitive layer 84 above the dielectric layer 70. The dielectric layer 70 and the photosensitive layer 84 can be made of materials selected from the same group (or from different groups) of materials, such as polyimide, PBO, BCB, and the like. The material of the dielectric layer 70 can be the same material as, or a different material from, that of the photosensitive layer 84. In some embodiments, the interface between the dielectric layer 70 and the photosensitive layer 84 can be discernible, regardless of whether these two layers are made of the same material or different materials.

[0055] Fig.Figure 16 shows a top view of the newly configured wafer 106 and the packages 106' (designated 106 / 106') according to some embodiments. Multiple metal contact mounds 82 may be present, arranged as a matrix or as another structure. Recesses 90, which may be filled or optionally overfilled with solder areas, may extend laterally beyond the edges of the metal contact mounds 82. Alternatively, the recesses 90 may be narrower than the respective underlying metal contact mounds 82, or they may have the same top-view shape and dimensions as these.

[0056] In the embodiments described above, some processes and structural elements according to some embodiments of the present disclosure are discussed for fabricating a three-dimensional package (3D package). Other processes and structural elements may also be used. For example, test structures may be used to assist in the verification testing of a 3D encapsulation or 3D integrated circuit (IC) devices. The test structures may include, for example, test pads fabricated in a redistribution layer or on a substrate that enable the testing of the 3D encapsulation or 3D IC, the use of probes and / or test cards, and the like. The verification testing may be performed on intermediate structures as well as on the final structure.Furthermore, the structures and procedures disclosed here can be used in conjunction with testing methodologies that include intermediate verification of proven good dies to increase yield and reduce costs.

[0057] The embodiments of the present disclosure have several advantages. By producing a dielectric layer (which may be a photosensitive layer) and removing recesses from the dielectric layer to create recesses, the recesses can accommodate solder areas and limit the lateral extent of the solder areas. The solder areas can thus be small distances apart without the risk of bridging.

[0058] According to some embodiments of the present disclosure, a method comprises manufacturing a first package component with the following steps: manufacturing a first dielectric layer having a first top surface; manufacturing a first conductive structural element, wherein the first conductive structural element has a via embedded in the first dielectric layer and a metal contact mound having a second top surface that is higher than the first top surface of the first dielectric layer; depositing a photosensitive layer, wherein the photosensitive layer covers the metal contact mound; and performing a photolithography process to create a recess in the photosensitive layer, wherein the metal contact mound is exposed to the recess and the photosensitive layer has a third top surface that is higher than the metal contact mound.The process further includes bonding a second package component to the first package component, wherein a solder area extends into the recess to bond the metal contact mound to a second conductive structural element in the second package component.

[0059] In one embodiment, performing the photolithography process comprises: performing an exposure process on the photosensitive layer; and developing the photosensitive layer to remove a portion of the photosensitive layer covering the metal contact mound. In one embodiment, the recess extends laterally beyond the edges of the metal contact mound, with a portion of the photosensitive layer located directly beneath the recess. In another embodiment, a sidewall of the metal contact mound is exposed to the recess, with the solder area extending to a plane lower than the second top surface of the metal contact mound to contact the sidewall of the metal contact mound. In another embodiment, the first dielectric layer includes a further photosensitive layer.In one embodiment, the recess extends to the first top surface of the first dielectric layer, wherein the first dielectric layer is not structured in the photolithography process.

[0060] In one embodiment, the first dielectric layer and the photosensitive layer are made from the same photosensitive material. In another embodiment, the method further comprises performing a planarization process on the photosensitive layer after the photosensitive layer has been applied and before the photolithography process has been carried out. In another embodiment, at the start of the photolithography process, the third top surface of the photosensitive layer has: a lower portion that is laterally offset from the metal contact mound; and a higher portion directly above the metal contact mound, the higher portion being taller than the lower portion. In another embodiment, after completion of the photolithography process, the third top surface of the photosensitive layer has a raised portion that encloses the recess, the raised portion being a component of the higher portion.

[0061] According to some embodiments of the present disclosure, a structure comprises a first package component comprising: a dielectric layer; a conductive structural element, wherein the conductive structural element has a via extending into the dielectric layer and a metal contact mound projecting beyond a first top surface of the dielectric layer; and a photosensitive structure extending from a lower level to a higher level, wherein the lower level is lower than a second top surface of the metal contact mound and the higher level is higher than the second top surface of the metal contact mound. The structure further comprises a solder region extending into the photosensitive structure to be connected to the metal contact mound, the solder region extending laterally beyond edges of the metal contact mound.In one embodiment, the photosensitive structure comprises a photosensitive material selected from the group consisting of a polyimide, PBO and BCB.

[0062] In one embodiment, the dielectric layer and the photosensitive structure comprise photosensitive materials. In another embodiment, the dielectric layer and the photosensitive structure are made of the same photosensitive material and are in contact with each other to create a recognizable interface between them. In another embodiment, the solder region contacts a sidewall of the photosensitive structure. In yet another embodiment, the structure further comprises a second package component with an additional metal contact mound, wherein the additional metal contact mound is bonded to the first metal contact mound by the solder region, and a bottom surface of the additional metal contact mound is at the same level as, or lower than, the first top surface of the dielectric layer.

[0063] According to some embodiments of the present disclosure, a structure comprises: a device die; a first and a second solder region; and a second package component. The device die comprises: a first photosensitive structure; a first and a second metal contact mound that are adjacent to each other and extend higher than the first photosensitive structure; and a second photosensitive structure above and in contact with the first photosensitive structure, wherein the second photosensitive structure has a first and a second recess, and the first and second metal contact mounds are arranged below the first and second recesses, respectively. The first and second solder regions extend into the first and second recesses, respectively, with a portion of the second photosensitive structure separating the first solder region from the second solder region.The second package component has a first conductive structural element bonded to the first metal contact mound by means of the first solder area; and a second conductive structural element bonded to the second metal contact mound by means of the second solder area.

[0064] In one embodiment, the first recess is wider than the first metal contact mound. In another embodiment, the second photosensitive structure has a lower part directly below the first recess, the lower part having a top surface that is level with the first metal contact mound. In another embodiment, the first and second photosensitive structures are made of the same photosensitive material.

[0065] Features of various embodiments have been described above so that those skilled in the art can better understand the aspects of the present disclosure. It should be clear to those skilled in the art that they can readily use the present invention as a basis for designing or modifying other methods and structures to achieve the same objectives and / or to obtain the same advantages as in the embodiments presented here. Those skilled in the art should also recognize that such equivalent interpretations do not deviate from the fundamental concept and scope of protection of the present disclosure and that they can make various changes, substitutions, and modifications without deviating from the fundamental concept and scope of protection of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 366438

[0001]

Claims

[1] Procedure, encompassing: Creating a first package component using the following steps: Creating a first dielectric layer with a first top surface, Fabricating a first conductive structural element, wherein the first conductive structural element has a via extending into the first dielectric layer and a metal contact mound with a second top surface that is higher than the first top surface of the first dielectric layer, Applying a photosensitive layer, wherein the photosensitive layer covers the metal contact mound, and Performing a photolithography process to create a recess in the photosensitive layer, exposing the metal contact mound to the recess and giving the photosensitive layer a third top surface that is higher than the metal contact mound; and Bonding a second package component to the first package component, wherein a solder area extends into the recess to bond the metal contact mound to a second conductive structural element in the second package component. [2] Method according to claim 1, wherein carrying out the photolithography process comprises: Performing an exposure process on the light-sensitive layer; and Developing the photosensitive layer to remove part of it that covers the metal contact mound. [3] Method according to claim 1 or 2, wherein the recess extends laterally beyond the edges of the metal contact mound, and Part of the light-sensitive layer is located directly beneath the cutout. [4] Method according to any one of the preceding claims, wherein a side wall of the metal contact mound is exposed to the recess, and the solder area extends to a level deeper than the second top surface of the metal contact mound in order to contact the side wall of the metal contact mound. [5] Method according to any one of the preceding claims, wherein the first dielectric layer has another light-sensitive layer. [6] Method according to any one of the preceding claims, wherein the recess extends to the first top surface of the first dielectric layer, and the first dielectric layer is not structured in the photolithography process. [7] Method according to any of the preceding claims, wherein the first dielectric layer and the photosensitive layer are made from the same photosensitive material. [8] Method according to any of the preceding claims, further comprising carrying out a planarization process on the light-sensitive layer after the application of the photosensitive layer and prior to carrying out the photolithography process. [9] A method according to any of the preceding claims, wherein, at the start of the photolithography process, the third top surface of the photosensitive layer has the following: a lower portion that is laterally offset from the metal contact mound; and a higher part directly above the metal contact hill, with the higher part being higher than the lower part. [10] Method according to claim 9, wherein after completion of the photolithography process the third top surface of the photosensitive layer has a raised part enclosing the recess, the raised part being a component of the higher part. [11] Structure with: a first package component which has the following features: a dielectric layer a conductive structural element, wherein the conductive structural element has a via embedded in the dielectric layer and a metal contact mound projecting above a first top surface of the dielectric layer, and a light-sensitive structure extending from a lower level to a higher level, wherein the lower level is lower than a second top surface of the metal contact hill and the higher level is higher than the second top surface of the metal contact hill; and a solder area extending into the photosensitive structure to be connected to the metal contact hill, with the solder area extending laterally beyond edges of the metal contact hill. [12] Structure according to claim 11, wherein the photosensitive structure comprises a photosensitive material selected from the group consisting of a polyimide, polybenzoxazole (PBO) and benzocyclobutene (BCB). [13] Structure according to claim 11 or 12, wherein the dielectric layer and the photosensitive structure both contain photosensitive materials. [14] Structure according to claim 13, wherein the dielectric layer and the photosensitive structure are made of the same photosensitive material and are in contact with each other to create a recognizable interface between them. [15] Structure according to one of claims 11 to 14, wherein the solder area contacts a side wall of the photosensitive structure. [16] Structure according to one of claims 11 to 15, further comprising a second package component with a further metal contact mound, wherein the further metal contact hill is bonded to the metal contact hill through the solder area, and a bottom side of the further metal contact hill is at the same level as, or lower than, the first top side of the dielectric layer. [17] Structure with: a device die which has the following features: a first light-sensitive structure, a first and a second metal contact hill, adjacent to each other and extending higher than the first photosensitive structure, and a second light-sensitive structure above and in contact with the first light-sensitive structure; a first and a second solder region extending into the second photosensitive structure, wherein a part of the second photosensitive structure separates the first solder region from the second solder region, and the first and second metal contact mounds are arranged below a first upper part of the first solder region and a second upper part of the second solder region, respectively; and a second package component which has the following features: a first conductive structural element that is bonded to the first metal contact mound by means of the first solder area, and a second conductive structural element that is bonded to the second metal contact hill by means of the second solder area. [18] Structure according to claim 17, wherein the first solder area is wider than the first metal contact hill. [19] Structure according to claim 17 or 18, wherein the second photosensitive structure has a lower part directly below the first upper part of the first solder area, the lower part having a top surface that is at the same level as the first metal contact hill. [20] Structure according to any one of claims 17 to 19, wherein the first and the second photosensitive structure are made of the same photosensitive material.

Images