MANUFACTURING PROCESS FOR SEMICONDUCTOR COMPONENT
Patent Information
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- DENSO CORP
- Filing Date
- 2023-11-13
- Publication Date
- 2026-07-09
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Abstract
Description
[0001] The invention relates to a manufacturing process for a semiconductor device.
[0002] A manufacturing process for a semiconductor device includes, for example, a process in which a semiconductor wafer formed with a multitude of elemental structures is divided into pieces such that each piece contains the elemental structure. As an example of the process of dividing a semiconductor wafer, JP 2014-13812A discloses a technique in which the semiconductor wafer is cut along a boundary between adjacent elemental structures (e.g., by dicing).
[0003] In recent years, scribing and fracturing has become a more common alternative to dicing. In scribing and fracturing, a pressure element is first pressed against a semiconductor wafer along a boundary between adjacent element structures to create a crack. Next, a splitting element is pressed against the wafer along this boundary to split it. Unlike dicing, scribing and fracturing does not split the wafer by cutting; instead, it splits it from the crack. Therefore, scribing and fracturing is suitable for relatively hard materials and can reduce the width between adjacent element structures compared to scribing.
[0004] In a scribing and fracturing process, a pressure element is pressed against a semiconductor wafer to generate stress within the wafer, thereby creating a crack. This stress remains as residual stress even after the wafer has been cut into pieces. Therefore, if a manufactured semiconductor device is repeatedly subjected to stress, chipping, unwanted cracks, or similar defects can occur in the vicinity of an area where this residual stress is present. These defects lead to a deterioration in the reliability of the semiconductor device.
[0005] The object of the invention is to provide a technique for manufacturing a semiconductor device with high reliability by using a scribing and breaking process.
[0006] According to one embodiment of the invention, a manufacturing method for a semiconductor device comprises the following: forming a plurality of element structures in the form of a matrix on a first surface of a semiconductor wafer; forming a crack extending in a thickness direction of the semiconductor wafer along a boundary between adjacent element structures by pressing a pressure element along the boundary against a second surface of the semiconductor wafer opposite the first surface; and dividing the semiconductor wafer along the boundary by pressing a dividing element against the semiconductor wafer along the boundary on the side of the first surface.
[0007] In the manufacturing process according to the first embodiment, the element structures are formed on the first surface of the semiconductor wafer in the form of the matrix, and the pressure element is pressed against the semiconductor wafer on the side of the second surface to apply a stress in the semiconductor wafer in a region adjacent to the second surface. This creates a crack in the semiconductor wafer in the region adjacent to the second surface. The semiconductor wafer is then split by pressing the splitting element against the semiconductor wafer on the side of the first surface. Therefore, in the manufactured semiconductor device, the residual stress does not exist in a region adjacent to the first surface, on which the individual element structure is formed, but rather in a region adjacent to the second surface, which is opposite the first surface.Due to the manufacturing process described above, residual stress is present in the area adjacent to the second surface, which faces the first surface on which the element structure, such as a groove or gate electrode, is formed, thus enabling the function of the semiconductor device. Therefore, even if chipping or similar defects occur due to the residual stress, it is less likely that the performance of the semiconductor device will be impaired. Accordingly, the manufacturing process described above can produce the semiconductor device with high reliability.
[0008] The tasks, features and advantages of the invention will become apparent from the following detailed description with reference to the accompanying drawings, in which identical parts are designated by the same reference numerals and which show the following: Fig. 1 a diagram showing a top view of a semiconductor wafer; Fig. 2. A diagram to illustrate an element structure formation process; Fig. 3 a diagram to illustrate a metal layer formation process; Fig. 4. A diagram to illustrate a crack formation process; Fig. 5. A diagram to illustrate a crack formation process; Fig. 6. A diagram to illustrate a division process; Fig. 7 a diagram showing several split semiconductor devices; Fig. 8 a curve which, with respect to a distance measured from a split surface in a direction perpendicular to the split surface, represents a residual stress present in the vicinity of a crack after a semiconductor wafer has been split along the crack; and Fig. 9 a curve which, with respect to a distance measured in a thickness direction of the semiconductor wafer from the first surface towards the second surface, represents the residual stress within the semiconductor wafer.
[0009] In one embodiment of the invention, a manufacturing method for a semiconductor device comprises the following: forming a plurality of element structures in the form of a matrix on a first surface of a semiconductor wafer; forming a crack extending in a thickness direction of the semiconductor wafer along a boundary between adjacent element structures by pressing a pressure element along the boundary against a second surface of the semiconductor wafer opposite the first surface; and dividing the semiconductor wafer along the boundary by pressing a dividing element against the semiconductor wafer along the boundary on the side of the first surface.
[0010] In one embodiment of the invention, the semiconductor wafer can consist of silicon carbide (SiC) in the manufacturing process.
[0011] In one embodiment of the invention, the manufacturing process can further comprise the following: forming a metal layer on the second surface of the semiconductor wafer. The timing for the formation of the metal layer need not be particularly restricted. For example, the metal layer can be formed before the crack forms. The metal layer can be formed between the crack formation and the splitting of the semiconductor wafer. The metal layer can be formed after the splitting of the semiconductor wafer.
[0012] With reference to the drawings, a manufacturing process for a semiconductor device is described below as an embodiment of the invention. Fig. Figure 1 is a top view of a semiconductor wafer 2 in which several element regions 3 are arranged in a matrix. Fig. In Figure 1, each of the element regions 3 is schematically represented by a solid line. An element region 3 is a region in which an element structure, such as a transistor or a diode, is formed on a first surface 2a of the semiconductor wafer 2. For ease of description, lines that are boundaries between adjacent element regions 3 and are used when the semiconductor wafer 2 is divided into individual element regions 3 are referred to as planned division lines 4. The planned division lines 4 are not actually drawn on the semiconductor wafer 2 but are imaginary lines. The planned division lines 4 may actually be lines or indentations drawn on the semiconductor wafer 2, making them visible. The semiconductor wafer is made of silicon carbide (SiC). Alternatively, the semiconductor wafer 2 may be made of another semiconductor material such as silicon (Si) or gallium nitride (GaN). As in Fig. As shown in Figure 2 and the like, the semiconductor wafer 2 has a first surface 2a and a second surface 2b, which is opposite the first surface 2a in a thickness direction of the semiconductor wafer 2.
[0013] The manufacturing process of this embodiment comprises an element structure formation process, a metal layer formation process, a crack formation process, and a division process. - Element structure formation process -
[0014] In the element structure formation process, as described in Fig. As shown in Figure 2, several element structures 6 are formed on the first surface 2a of the semiconductor wafer 2. Each element structure 6 comprises at least one electrode, an insulating film, an n-type region, and a p-type region adjacent to the first surface 2a. The element structure 6 includes a structure such as a groove or a gate electrode to implement the function of the semiconductor device. In the element structure formation process, the element structure 6 is formed for each of the element regions 3. The element structures 6 are formed such that they are arranged in a matrix on the first surface 2a of the semiconductor wafer 2. In addition to the element structures 6 on the first surface 2a, a structure (not shown) can also be formed within the semiconductor wafer 2 for each of the element regions 3 during the element structure formation process. This structure provides the function of a transistor or a diode.For example, if the structure of a metal-oxide-semiconductor field-effect transistor (MOSFET) is formed within the semiconductor wafer 2, a source region and a body region are formed individually for each of the element structures 6 in an area exposed on the first surface 2a. On the other hand, a drain region is formed essentially over the entire area exposed on the second surface 2b. Specifically, the drain region is formed such that it extends across the multiple element regions 3 at a point exposed on the second surface 2b. - Metal layer formation process -
[0015] Next, a metal layer formation process takes place, which is carried out in Fig. 3 is shown. Fig. Figure 3 shows the semiconductor wafer 2 with the side of the second surface 2b facing upwards. In the metal layer formation process, a metal layer 40 is formed on the second surface 2b of the semiconductor wafer 2. The metal layer 40 consists, for example, of titanium, nickel, gold, nickel silicide, or the like. The metal layer 40 is formed such that it covers essentially the entire area of the second surface 2b. Specifically, the metal layer 40 is formed on the second surface 2b in such a way that it extends over several element regions 3. The metal layer 40 functions as an electrode in the completed semiconductor device. - Crack formation process -
[0016] Next, a cracking process occurs, which takes place in the Fig. 4 and Fig. Figure 5 shows that in the crack formation process, the cracking process begins as shown in Figure 5. Fig. As shown in Figure 4, a protective element 15 is attached such that it extends over the surfaces of the element structures 6 that have been formed in the respective element regions 3 of the semiconductor wafer 2. The protective element 15 can, for example, consist of a resin or the like. Next, the semiconductor wafer 2 is placed on a stage 30. In this case, the semiconductor wafer 2 is placed on the stage 30 such that the second surface 2b faces upwards, i.e., opposite the stage 30. The stage 30 has a vacuum suction device, which is not shown. Thus, the stage 30 can suction and fix the semiconductor wafer 2, and in particular the protective element 15 on it.
[0017] Then, as in Fig. As shown in Figure 5, a scribing wheel 60 is pressed against a front surface 40a of the metal layer 40 to form a scribing line with a crack 5 in the semiconductor wafer 2. Specifically, the scribing wheel 60 is pressed against the side of the second surface 2b, as indicated by the arrow in Figure 5. Fig. Figure 5 shows the gear 60 pressed against the semiconductor wafer 2 in the direction of the second surface 2b. The gear 60 is a disk-shaped (e.g., circular) element and is rotatably supported by a (not shown) support device. The gear 60 is moved back and forth along the planned division lines 4 while being pressed against the front surface 40a of the metal layer 40. As it moves along the planned division lines 4, the gear 60 rolls on the front surface 40a of the metal layer 40 like a tire rolling on a road surface. The gear 60 has a sharp circumferential edge and forms lines along the planned division lines 4 on the front surface 40a of the metal layer 40, forming lines where the metal layer 40 is plastically deformed.When the front surface 40a of the metal layer 40 is pressed by the scoring wheel 60, compressive stress is generated across the metal layer 40 in a surface layer region that adjoins the second surface 2b within the semiconductor wafer 2. While the scoring lines (i.e., the indentations) are formed on sections pressed by the scoring wheel 60, tensile stress is generated within the semiconductor wafer 2 immediately below the region where compressive stress is generated. The tensile stress is generated immediately below the region where the compressive stress is generated along the second surface 2b of the semiconductor wafer 2 in a direction away from the planned scoring lines 4. Due to this tensile stress, the crack 5 is formed within the semiconductor wafer 2, extending in the thickness direction of the semiconductor wafer 2.Since the scribing wheel 60 is moved along the planned parting lines 4 while being pressed against the front surface 40a, the crack 5 is formed in this case in a region adjacent to the second surface 2b of the semiconductor wafer 2, such that it extends in the thickness direction of the semiconductor wafer 2 and along the boundary between the adjacent element regions 3 (i.e., the element structures 6). The crack 5 is formed in the vicinity of the surface layer of the second surface 2b of the semiconductor wafer 2. The scribing wheel 60 is an example of a pressure element. - Division process -
[0018] Next, a division process takes place, which is divided into Fig. 6 is shown. Fig. Figure 6 again shows the semiconductor wafer 2 with its first surface 2a facing upwards. In the splitting process, a breaking plate 62 is pressed along the planned splitting lines 4 (i.e., along the cracks 5 formed during the cracking process) to split the semiconductor wafer 2 along the planned splitting lines 4 (i.e., along the boundaries of the element structures 6). In this case, the semiconductor wafer 2 is first placed on two support supports 34. The two support supports 34 are spaced apart, leaving a gap between them. The semiconductor wafer 2 is positioned on the support supports 34 such that the gap is located below a splitting position, that is, the gap is located below a position against which the breaking plate 62 is pressed. The breaking plate 62 is then pressed against the first surface 2a of the semiconductor wafer 2 via the protective element 15.The crushing plate 62 is a plate-shaped element, with one lower end of the crushing plate 62 (i.e., an edge pressed against the first surface 2a) having a wedge-shaped profile (i.e., a sharp edge). However, the crushing plate 62 is merely pressed against the semiconductor wafer 2 so that the semiconductor wafer 2 is not cut.
[0019] The support beams 34 are not present below the crushing plate 62. In other words, the gap between the two support beams 34 is located below the crushing plate 62. When the crushing plate 62 is pressed against the first surface 2a, the semiconductor wafer 2 is therefore bent so that it enters the gap between the two support beams 34. In this case, the crack 5 has formed in the semiconductor wafer 2 adjacent to the second surface 2b. When the crushing plate 62 is pressed against the semiconductor wafer 2 on the side of the first surface 2a, that is, as indicated by the arrow in Fig. As shown in Figure 6, when pressure is applied in the direction of the first surface 2a, the semiconductor wafer 2 is bent around the pressed section (the pressed line). This applies a force to the crack 5 in the region adjacent to the second surface 2b in a direction in which the crack 5 expands such that the two adjacent element regions 3 are separated across the crack 5 at the splitting position. As described above, tensile stress is applied to the area surrounding the crack 5. Therefore, when the breaking plate 62 is pressed against the first surface 2a, the crack 5 expands in the thickness direction of the semiconductor wafer 2, and the semiconductor wafer 2 is split from the crack 5 along the crystal plane. This splits the semiconductor wafer 2.Since the metal layer 40 is formed on the second surface 2b of the semiconductor wafer 2, a force is also applied to the metal layer 40 in a direction that separates the two adjacent element regions 3 at the splitting position. The metal layer 40 is deformed in such a way that it is separated and thus divided. Instead of being supported by the two support carriers 34, the entire second surface 2b of the semiconductor wafer 2 can be supported by a single elastic support plate or by one or more support carriers via a single elastic support plate. Although the elastic support plate is present below the breaking plate 62 in these cases, the elastic support plate is deformed according to the bending of the semiconductor wafer 2 when it is bent.When the breaking plate 62 is pressed against the first surface 2a, a force is applied to the crack 5 in a direction in which the crack 5 expands such that the two adjacent element regions 3 are separated at the splitting position, similar to the case where the semiconductor wafer 2 is supported by the two support beams 34 (i.e., in the case where the support beams 34 are not present below the breaking plate 62). The breaking plate 62 is an example of a splitting element.
[0020] In the division process, the action of pressing the breaking plate 62 against the first surface 2a is repeated along each of the planned division lines 4. Accordingly, the semiconductor wafer 2 and the metal layer 40 can be divided along the boundaries between the element regions 3. This results in the semiconductor wafer 2 being divided as shown in Fig. Figure 7 shows the structure divided into several semiconductor devices 10. In this way, the multiple semiconductor devices 10 can be obtained, each of which is formed with the element structure 6 and the metal layer 40 (i.e., a back electrode).
[0021] As described above, the semiconductor device 10 is fabricated by forming the crack 5 using the scribing wheel 60 and splitting the semiconductor wafer 2 using the breaking plate 62. In this embodiment, the semiconductor wafer 2 is split by splitting it from the crack instead of being cut (e.g., by dicing). This technique is advantageous for SiC, which is relatively hard. Furthermore, in the fabrication process of this embodiment, the width between adjacent device structures 2 can be set more narrowly than in the dicing process.
[0022] When the pinion wheel 60 is pressed against the semiconductor wafer 2 to form the crack 5 in the semiconductor wafer 2, the stress is generated within the semiconductor wafer 2 as described above. This stress remains in the semiconductor wafer 2 as residual stress even after the semiconductor wafer 2 has been separated. Fig. Figure 8 is a curve showing residual stress present in the vicinity of a crack (i.e., at a depth of approximately 1 µm from the surface pressed by the scribing wheel) after a semiconductor wafer has been split along the crack by the scribing and breaking process, with the residual stress measured from the split surface along a direction perpendicular to the split surface. The horizontal axis represents in Fig. 8 represents a distance from the split surface (i.e., the distance from the surface against which the pinion wheel is pressed), while the vertical axis represents the value of the residual stress. In Fig. 8 and Fig. 9, which will be described later, the positive value of the residual stress indicates the tensile stress, while the negative value of the residual stress indicates the compressive stress. As in Fig. As shown in Figure 8, the environment around the division surface (i.e., the environment around the in) is characterized by a symmetry of symmetry. Fig. (5 shown crack 5 and the like) exhibits a large residual stress. If the manufactured semiconductor device 10 is repeatedly subjected to stress, it is likely that the area surrounding the residual stress will experience a load and that, compared to other areas, spalling or similar defects will occur.
[0023] Since, in the manufacturing process of this embodiment, the element structure 6 is formed on the first surface 2a of the semiconductor wafer 2, and the scoring wheel 60 is pressed against the semiconductor wafer 2 on the side of the second surface 2b, the stress is applied to the area adjacent to the second surface 2b, and the crack 5 is formed therein. The semiconductor wafer 2 is then split by pressing the breaking plate 62 against the semiconductor wafer 2 on the side of the first surface 2a. As a result, the residual stress in the manufactured semiconductor device 10 is not present in an area adjacent to the first surface 2a, on which the element structure 6 is individually formed, but rather in the area adjacent to the second surface 2b, which is opposite the element structure 6.
[0024] Fig. Figure 9 is a curve showing the residual stress within the semiconductor wafer 2 when measured in the thickness direction from the first surface 2a towards the second surface 2b. As in Fig.As shown in Figure 9, a large residual stress exists adjacent to the second surface 2b (i.e., in the surrounding area at a distance of 100 µm), while there is almost no residual stress adjacent to the first surface 2a (i.e., in the surrounding area at a distance of 0 µm). As described above, in the manufacturing process of this embodiment, the residual stress is located adjacent to the second surface 2b, which is on the opposite side of the first surface 2a. The first surface 2a is formed with the element structure 6, such as a groove or a gate electrode, which implements the function of the semiconductor device 10. Therefore, even if chipping or similar defects occur due to the residual stress, it is less likely that the performance of the semiconductor device 10 will be impaired.Therefore, in the manufacturing process of this embodiment, the semiconductor device 10, which has high reliability, can be manufactured.
[0025] Although only an exemplary embodiment and examples have been chosen to illustrate the invention, it will be apparent to those skilled in the art that various modifications and adaptations can be made to it without deviating from the scope of protection as defined in the claims. The foregoing description of the exemplary embodiment of the invention and the examples serves only illustrative purposes and is not intended to limit the scope of protection as defined by the claims. QUOTES INCLUDED IN THE DESCRIPTION
[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature
[0000] JP 201413812 A
[0002]
Claims
[1] A manufacturing method for a semiconductor device (10), comprising: Forming a plurality of element structures (6) in the form of a matrix on a first surface (2a) of a semiconductor wafer (2); Forming a crack (5) extending in a thickness direction of the semiconductor wafer (2) along a boundary between adjacent element structures (6) by pressing a pressure element (60) against a second surface (2b) of the semiconductor wafer (2) along the boundary, the second surface (2b) being opposite the first surface (2a) in the thickness direction; and Dividing the semiconductor wafer (2) along the boundary by pressing a dividing element (62) against the semiconductor wafer (2) along the boundary on the side of the first surface (2a). [2] A manufacturing method according to claim 1, wherein the semiconductor wafer (2) is made of silicon carbide. [3] A manufacturing method according to claim 1 or 2, further comprising: Forming a metal layer (40) on the second surface (2b) of the semiconductor wafer (2). [4] Manufacturing method according to claim 3, wherein the formation of the metal layer (40) takes place before the formation of the crack (5) and the pressure element (60) is pressed against the second surface (2b) of the semiconductor wafer (2) via the metal layer (40) when forming the crack (5).
Citation Information
Patent Citations
JP2014013812A
US20200381302A1