Thin-layer transistor, pixel structure and method for manufacturing a thin-layer transistor

Abstract

A thin-film transistor (1, 1A, 1B, 1C, 1D, 1E, T) comprises a substrate (100), a gate (G), a semiconductor layer (SM), and a gate insulating layer (GL1, GL). The gate (G) is positioned on the substrate (100) and has a top surface (111A) and a side surface (112A). The semiconductor layer (SM) is positioned on the substrate (100) and comprises a drain region, a channel region, and a source region, with the gate (G) overlapping the channel region. The contour of a top surface of the gate insulating layer (GL1, GL) has a first surface (F1), a second surface (F2), a third surface (F3), and a fourth surface (F4) arranged sequentially to form a groove (GR1, GR2). The first surface (F1) overlaps the top surface (111A), the second surface (F2) and the third surface (F3) overlap the side surface (112A), and the fourth surface (F4) overlaps the substrate (100).

Description

BACKGROUND Technical Area

[0001] The present disclosure relates to a semiconductor element, a circuit structure and a method for manufacturing a semiconductor element, and in particular to a thin-film or thin-layer transistor, a pixel structure and a method for manufacturing a thin-layer transistor. Description of the state of the art

[0002] With the innovation of display technology, the demands on the brightness, performance, and resolution of display panels have gradually increased. Displays that use self-illuminating elements (such as micro-LEDs) have gradually become the focus of research and development for relevant manufacturers due to their advantages, such as not requiring a backlight module and offering high brightness and contrast.

[0003] Self-illuminating elements, however, are driven by thin-film transistors on the active matrix substrate. If the light-emitting element is a current-controlled element, the thin-film transistor must also supply a higher current. For example, to meet the high current requirements of micro light-emitting diodes (micro-LEDs), thin-film transistors must also exhibit high electron mobility, lower critical dimensional requirements, lower capacitive delay, and high storage capacity. The performance of current thin-film transistors, however, still needs improvement. SUMMARY

[0004] The present disclosure provides a thin-film transistor that can offer high current gain and good electrical properties.

[0005] The present disclosure provides a pixel structure capable of meeting the high power requirements of self-illuminating elements, and these self-illuminating elements exhibit high and uniform brightness. When used in displays, such a pixel structure can improve the resolution, contrast, and brightness of the screen.

[0006] The present disclosure provides a method for the fabrication of a thin-film transistor which can improve the production yield of thin-film transistors.

[0007] One embodiment of the present disclosure provides a thin-film transistor comprising a substrate, a first gate, a first semiconductor layer, and a first gate insulating layer. The first gate is arranged on the substrate and has a top surface and a side surface. The first semiconductor layer is arranged on the substrate and comprises a drain region, a channel region, and a source region, with the first gate overlapping the channel region. The first gate insulating layer is arranged between the first semiconductor layer and the first gate. A top surface contour of the first gate insulating layer has a first surface, a second surface, a third surface, and a fourth surface arranged sequentially to form a groove. The first surface overlaps the top surface, the second and third surfaces overlap the side surface, and the fourth surface overlaps the substrate.The thickness of the first gate insulating layer on the first surface is less than the thickness of the first gate insulating layer on the second surface, and the thickness of the first gate insulating layer increases from the third surface to the fourth surface.

[0008] One embodiment of the present disclosure provides a pixel structure comprising a self-illuminating element and several thin-film transistors. At least one of these thin-film transistors has the structure of the thin-film transistor mentioned above. At least one of these thin-film transistors is electrically connected to the self-illuminating element, and the self-illuminating element comprises at least one micro-LED, a sub-millimeter LED, or an organic LED.

[0009] One embodiment of the present disclosure provides a method for fabricating a thin-film transistor, comprising: forming a gate on a substrate, wherein the gate has a top surface and a side surface connected to the top surface; forming a gate insulating layer on the gate; etching the gate insulating layer such that the top surface contour of the gate insulating layer has a first surface, a second surface, a third surface, and a fourth surface arranged sequentially to form a groove; forming a semiconductor layer such that the gate insulating layer is arranged between the semiconductor layer and the gate, wherein the first surface overlaps the top surface, the second and third surfaces overlap the side surface, and the fourth surface overlaps the substrate.The thickness of the gate insulating layer on the first surface is less than the thickness of the gate insulating layer on the second surface, and the thickness of the gate insulating layer increases from the third surface to the fourth surface.

[0010] In order to make the above-mentioned features and advantages of the present disclosure clearer and more understandable, exemplary embodiments with detailed explanations in conjunction with the accompanying drawings are presented below. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1A is a schematic cross-sectional view of a thin-film transistor according to an embodiment of the present disclosure. Fig. Figure 1B is an enlarged schematic view of an area A1 in Fig. 1A. Fig. Figure 1C is a top view of a substructure of the thin-film transistor in Fig. 1A. Fig. 2A and Fig.Figure 2B are schematic cross-sectional views of substructures of a thin-film transistor in a comparative example or embodiment of the present disclosure. Fig. Figures 3A to 3E are schematic cross-sectional views of subprocesses of the fabrication of a thin-film transistor according to an embodiment of the present disclosure. Fig. Figure 4 is a circuit diagram of a pixel structure according to an embodiment of the present disclosure. Fig. Figures 5A to 5C are schematic cross-sectional views of thin-film transistors according to several embodiments of the present disclosure. Fig. Figure 6A is a schematic cross-sectional view of a thin-film transistor according to an embodiment of the present disclosure. Fig. 6B is an enlarged schematic view of an area A2 in Fig. 6A. Fig.Figure 7 is a schematic cross-sectional view of a thin-film transistor according to an embodiment of the present disclosure. Fig. Figure 8 is a schematic cross-sectional view of a partial area of ​​a pixel structure according to an embodiment of the present disclosure. DESCRIPTION OF THE EXECUTION FORMS

[0011] The following section refers in detail to exemplary embodiments of the disclosure, examples of which are shown in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to identical or similar parts.

[0012] It should be noted that when an element, such as a layer, film, area, or substrate, is described as "on" or "connected to" another element, it may be directly on top of or connected to that other element, or there may be intervening elements. Conversely, when an element is described as "directly on" or "directly connected to" another element, there are no intervening elements. The term "connected" as used here can refer to a physical and / or electrical connection. Furthermore, an "electrical connection" or "coupling" can exist between two elements even if other elements are present between them.

[0013] The terms "approximately," "nearly," or "essentially" used here encompass the stated value and the average values ​​within an acceptable range of deviation, as determined by ordinary experts in the field, taking into account the specific quantity of measurements under discussion and the errors associated with those measurements (i.e., the limitations of the measuring system). For example, "approximately" may mean that the value is within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, or ±5%. Furthermore, "approximately," "nearly," or "essentially" may be chosen with a more acceptable range of deviation or standard deviation depending on the optical properties, etching properties, or other characteristics, rather than applying a standard deviation to all properties.

[0014] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as they are generally understood by a person skilled in the art in the field to which this disclosure belongs. It is further understood that terms as defined in commonly used dictionaries should be interpreted to have a meaning consistent with their meaning in the context of the relevant prior art and the present disclosure, and that they should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0015] Fig. Figure 1A is a schematic cross-sectional view of a thin-film transistor according to an embodiment of the present disclosure. Fig. Figure 1B is an enlarged schematic view of an area A1 in Fig. 1A. Fig.Figure 1C is a top view of a substructure of the thin-film transistor in Fig. 1A. With reference to Fig. 1A, the thin-film transistor 1 contains a substrate 100, a first gate 110A, a second gate 110B, a first semiconductor layer 120A, a second semiconductor layer 120B, a first gate insulating layer 130A, a second gate insulating layer 130B, a buffer layer 140, an insulating layer 150, a barrier layer 160, a source S and a drain D.

[0016] In this embodiment, the substrate 100 material can be glass, quartz, organic polymer, opaque / reflective material (for example, conductive material, wafer, ceramic, or other suitable materials), or other suitable materials. It should be noted that, unless otherwise specified in the following text, direction Z can be the normal direction of substrate 100 and can also represent the thickness directions of different film layers, while the plane containing direction X and direction Y can be the plane of substrate 100.

[0017] The first gate 110A has a top surface 111A and a side surface 112A. The side surface 112A can have a gradually varying thickness; for example, the thickness of the side surface 112A gradually decreases in the Z direction with increasing Y direction. On the other hand, the first gate 110A, the second gate 110B, the source S, and the drain D are generally made of metal for conductivity reasons. However, the present disclosure is not limited to this. According to other embodiments, the first gate 110A, the second gate 110B, the source S, and the drain D can also be made of other conductive materials. For example: alloys, nitrides of metallic materials, oxides of metallic materials, oxynitrides of metallic materials, or stacked layers of metallic materials with other conductive materials. The present disclosure is not limited to this.

[0018] The first semiconductor layer 120A is arranged on the substrate 100. In this embodiment, the first semiconductor layer 120A is also arranged on the first gate 110A. Furthermore, the first semiconductor layer 120A includes a first source region 121A, a first channel region 122A, and a first drain region 123A, and the first gate 110A overlaps the first channel region 122A. Similarly, the second semiconductor layer 120B is arranged on the substrate 100. The second semiconductor layer 120B also includes a second source region 121B, a second channel region 122B, and a second drain region 123B, with the second channel region 122B overlapping the first gate 110A.In this embodiment, the first semiconductor layer 120A and the second semiconductor layer 120B are, for example, semiconductor materials made of polysilicon thin film and contain doped regions with different charge carrier doping concentrations (which will be explained later), but the present disclosure is not limited thereto.

[0019] On the other hand, the first gate insulating layer 130A is arranged between the first semiconductor layer 120A and the first gate 110A. In this embodiment, the material of the first gate insulating layer 130A can preferably be an inorganic material (for example, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the aforementioned materials). The materials of the second gate insulating layer 130B and the insulating layer 150 can be the same as or different from the material of the first gate insulating layer 130A; the present disclosure is not limited in this respect. Furthermore, in this embodiment, the first gate insulating layer 130A can comprise a first sublayer 131A and a second sublayer 132A, wherein the first sublayer 131A is arranged between the first gate 110A and the second sublayer 132A.The material of the first sublayer 131A can be the same as or different from the material of the second sublayer 132A. In some embodiments, the second sublayer 132A can serve as a further buffer layer, but the present disclosure is not limited to this. In other embodiments, the first gate insulating layer 130A can be a single-layer structure or stacked with several other sublayers.

[0020] See both Fig. 1A as well Fig.1B. It is worth noting that the contour (or it can also be understood as the surface contour of the second sublayer 132A in the Z direction away from the first gate 110A) of the upper surface of the first gate insulating layer 130A away from the first gate 110A has a first surface F1, a second surface F2, a third surface F3, and a fourth surface F4, arranged sequentially to form a groove GR1. The first surface F1 overlaps with the top surface 111A, the second surface F2 and the third surface F3 overlap with the side surface 112A, and the fourth surface F4 overlaps with the substrate 100, but not with the first gate 110A. Furthermore, the thickness D1 of the first gate insulating layer 130A on the first surface F1 is less than the thickness D2 of the first gate insulating layer 130A on the second surface F2, and the thickness of the first gate insulating layer 130A increases from the third surface F3 to the fourth surface F4.It should be explained that the definition of thicknesses D1 to D4 here is the layer thickness of the first gate insulating layer 130A at different positions in the Z direction. For example, thickness D1 can be the vertical distance from the top of the second sublayer 132A, away from the first gate 110A, to the top of 111A, or thickness D1 can essentially be thickness D132; thickness D2 can be the vertical distance from the second surface F2 of groove GR1 to the side surface 112A; thickness D3 can be the vertical distance from the third surface F3 of groove GR1 to the side surface 112A; thickness D4 can be the vertical distance from the fourth surface F4 of groove GR1 to the bottom surface of the first sublayer 131A.Or, viewed from another perspective, the lower surface of the first gate 110A has an extension plane exL in the Y direction, and the thickness D4 can also be defined as the vertical distance between the fourth surface F4 and the extension plane exL.

[0021] Specifically, during the manufacturing process of the first gate 110A and the first gate insulating layer 130A, the thickness of the first gate insulating layer 130A can be reduced by an etching process, and the different properties of the materials of the first gate 110A and the first gate insulating layer 130A can be used to create a difference in the thickness of the first gate insulating layer 130A above the top surface 111A and the thickness of the first gate insulating layer 130A above the side surface 112A. In this way, the thickness D1 (or thickness D132) of the first gate insulating layer 130A can be reduced, and the groove GR1, which overlaps the side surface 112A, can be formed on the top surface of the first gate insulating layer 130A.In this way, the first semiconductor layer 120A above the first gate 110A can be formed on a relatively flat surface, thereby reducing the risk of a break in the first semiconductor layer 120A, which could lead to transistor failure. From another perspective, the yield and electrical properties of the thin-film transistor 1 can be improved.

[0022] It is worth noting that in the implementation where the first sublayer 131A and the second sublayer 132A are made of different materials, a boundary between the first sublayer 131A and the second sublayer 132A can be observed using measuring instruments (such as the scanning electron microscope, SEM). Furthermore, the first sublayer 131A can be etched before the second sublayer 132A is applied, so that it is possible to observe that the first sublayer 131A covers the side surface 112A of the first gate 110A and forms a concave structure CA on the side surface 112A of the first gate 110A, with the concave structure CA overlapping the groove GR1 (as shown in [reference]). Fig. 1B shown).

[0023] Furthermore, during the etching process, the first sublayer 131A above the first gate 110A can be completely etched, such that part (or all) of the top surface 111A is not covered by the first sublayer 131A. In other words, the second sublayer 132A can be in contact with part (or all) of the top surface 111A of the first gate 110A, with the concave structure CA of the first sublayer 131A, and with the portion of the top surface of the first sublayer 131A that does not overlap with the first gate 110A. Of course, the present disclosure is not limited to this. In other, unillustrated implementations, the first sublayer 131A can also cover the top surface 111A.

[0024] Fig. 2A and Fig. Figure 2B shows schematic cross-sectional views of substructures of thin-film transistors in a comparative example and an embodiment of the present disclosure. First, let us consider Fig.Figure 2A is referenced, which shows the result of successive stacking of different film layers without etch grooves. In this case, the direct deposition of the gate insulating layer GL1 and the gate insulating layer GL results in a larger discontinuity formed by the gate insulating layer GL1 and the gate insulating layer GL. Before the formation of the semiconductor layer SM, the amorphous silicon material of the semiconductor layer SM must undergo excimer laser annealing (ELA) to form low-temperature polycrystalline silicon (LTPS). At this stage, the material of the molten semiconductor layer SM is easily affected by gravity and surface irregularities, leading to a break in the connection (for example, the formation of a discontinuous region DIS), which reduces the yield of the thin-film transistor or even causes it to fail.If no groove is etched, the thickness of the gate insulating layer increases from the top surface of the thin-film transistor towards the outside surface, initially on the inclined surface, and then returns to its original thickness. For example, the thickness D1' of the gate insulating layer GL on the top surface of the gate G is approximately 3104 Å; the thickness D2' of the gate insulating layer GL on the inclined surface of the gate G is approximately 3680 Å; the thickness D3' of the gate insulating layer GL in the region outside the gate G is approximately 3104 Å (which can also be interpreted as the distance from the top surface of the gate insulating layer GL to the top surface of the gate insulating layer GL1). Furthermore, if no groove is etched, the thickness of the gate insulating layer above the side surface of the gate G remains constant. [Table 1] thickness D1 D2 D3 D31 D32 D33 D34 D4 Thickness (Å) 1438 1560 1483 1820 1973 2141 2462 3150 The relationship of change at different positions 8% -5% 23% 8% 9% 15% 28% 8%

[0025] Table 1 lists the layer thicknesses and change trends of the first gate insulating layer 130A at various positions. See also Fig.Figure 2B and Table 1 show the result of successive stacking of different film layers with etched groove GR1. In this implementation, the thickness D1 (approximately 1438 Å) of the first gate insulating layer 130A on the first surface F1 is less than the thickness D2 (approximately 1560 Å) of the first gate insulating layer 130A on the second surface F2. Furthermore, the thickness D3 (approximately 1483 Å) of the first gate insulating layer 130A on the third surface F3 is less than the thickness D2. On the other hand, on the third surface F3 and the fourth surface F4 of the groove GR1, the thickness (for example from thickness D3 via thicknesses D31 to D34 to thickness D4) of the first gate insulating layer 130A increases from the third surface F3 to the fourth surface F4, until the first gate insulating layer 130A no longer overlaps with the first gate 110A; then the thickness of the first gate insulating layer 130A remains constant.In other words, in this implementation, the thickness of the first gate insulating layer 130A above the side surface 112A gradually increases in its change trend in the negative direction Y.

[0026] As mentioned above, in some embodiments the groove GR1 can have a suitable depth; for example, the depth DG of groove GR1 can be greater than 0 micrometers and less than half the thickness D110 of the first gate 110A. In some embodiments, the depth DG of groove GR1 can be less than the maximum thickness D120 of the second semiconductor layer 120B. Conversely, since the thickness of the first gate insulating layer 130A can be less, the layer thickness of the first gate 110A can be greater to achieve good conductivity and maintain the flatness of the top surface of the first gate insulating layer 130A. For example, in some embodiments the thickness D110 of the first gate 110A can be greater than 1000 Å.

[0027] With reference to Fig. 1A and Fig.In the case of the thin-film transistor 1B, the junction layer 160 can be located on the second gate insulating layer 130B, covering and contacting the second gate 110B. The junction layer 160 is, for example, an inorganic barrier passivation layer (IOBP) made of an inorganic material, used for surface treatment, which can protect the underlying elements or layers (for example, the second gate 110B) from corrosion caused by etching solution and impurities during the process. Furthermore, the insulating layer 150 is located between the second semiconductor layer 120B and the first gate 110A and is configured to electrically isolate the first gate 110A from the second semiconductor layer 120B.Since the layer thickness of the first gate insulating layer 130A is further reduced by the etching process, the thickness D150 of the insulating layer 150 can also be greater than the thickness D132 of the first gate insulating layer 130A on the top side 111A.

[0028] With further reference to Fig.1A, on the other hand, the first source region 121A of the first semiconductor layer 120A can contain a first lightly doped region 1211A and a first heavily doped region 1212A, the first drain region 123A can contain a second lightly doped region 1231A and a second heavily doped region 1232A. Furthermore, in the direction Y, the first lightly doped region 1211A is arranged between the first heavily doped region 1212A and the first channel region 122A, the first channel region 122A is arranged between the first lightly doped region 1211A and the second lightly doped region 1231A, the second lightly doped region 1231A is arranged between the first channel region 122A and the second heavily doped region 1232A, there is a boundary I1 between the first lightly doped region 1211A and the first channel region 122A, and there is a boundary I2 between the first channel region 122A and the second lightly doped region 1231A.

[0029] In detail, the doping concentration of the first lightly doped region 1211A and the first heavily doped region 1212A can optionally differ (for example, the doping concentration of the first lightly doped region 1211A is lower than the doping concentration of the first heavily doped region 1212A), but the present disclosure is not limited to this. It should be noted that in practical application, boundary I1 and boundary I2 are not visible; boundary I1 and boundary I2 are virtual boundaries between two regions with different doping concentrations. For example, instruments can be used to analyze the doping concentrations of the first lightly doped region 1211A and the first channel region 1212A, and the position at which the doping concentration abruptly changes is the position of the virtual boundary (i.e., boundary I1).

[0030] Similarly, the second source region 121B of the second semiconductor layer 120B can contain a first lightly doped region 1211B and a first heavily doped region 1212B, and the second drain region 123B can contain a second lightly doped region 1231B and a second heavily doped region 1232B.Furthermore, in the Y direction, the first lightly doped region 1211B is located between the first heavily doped region 1212B and the second channel region 122B; the second channel region 122B is located between the first lightly doped region 1211B and the second lightly doped region 1231B; the second lightly doped region 1231B is located between the second channel region 122B and the second heavily doped region 1232B; there is also a boundary I1 between the second channel region 122B and the first lightly doped region 1211B; and there is also a boundary I2 between the second channel region 122B and the second lightly doped region 1231B. The configuration relationship of the various doped regions in the second semiconductor layer 120B can be the same as the configuration relationship of the first semiconductor layer 120A, which is not repeated here.

[0031] Fig.1C is a top view of a substructure of the thin-film transistor of Fig. 1A. See again Fig. 1A and Fig.1C. On the other hand, the second gate insulating layer 130B is arranged on the first semiconductor layer 120A, and the second gate 110B is arranged on the second gate insulating layer 130B. In particular, in this embodiment, the second gate insulating layer 130B is arranged between the second gate 110B and the first semiconductor layer 120A. Furthermore, the buffer layer 140 is arranged between the substrate 100 and the second semiconductor layer 120B, and the second semiconductor layer 120B is arranged between the substrate 100 and the first gate 110A.In this embodiment, the material of the buffer layer 140 can be an inorganic material (for example, silicon oxide, silicon nitride, silicon oxynitride or a stacked layer of at least two of the above-mentioned materials), an organic material or a combination of the above-mentioned materials to facilitate the epitaxy or growth of different film layers above the buffer layer 140 (for example, the growth of the second semiconductor layer 120B).

[0032] On the other hand, in this embodiment, the drain D can be directly electrically connected to the first side SA1 of the first semiconductor layer 120A and the first side SB1 of the second semiconductor layer 120B. The source S can be directly electrically connected to the second side SA2 of the first semiconductor layer 120A and the second side SB2 of the second semiconductor layer 120B. The first side SA1 and the second side SA2 of the first semiconductor layer 120A can be two sides opposite each other in the Y direction, and the first side SB1 and the second side SB2 of the second semiconductor layer 120B can be two sides opposite each other in the Y direction.

[0033] In particular, the drain D can be directly electrically connected to the first drain region 123A of the first semiconductor layer 120A through the through-hole THA1, which penetrates the junction 160 and the second gate insulating layer 130B, and can be directly electrically connected to the second drain region 123B of the second semiconductor layer 120B through the through-hole THB1, which penetrates the junction 160, the second gate insulating layer 130B, the first gate insulating layer 130A and the insulating layer 150.Similarly, the source S can be directly electrically connected to the first source region 121A of the first semiconductor layer 120A via the through-hole THA2, which penetrates the junction 160 and the second gate insulating layer 130B, and to the second source region 121B of the second semiconductor layer 120B via the through-hole THB2, which penetrates the junction 160, the second gate insulating layer 130B, the first gate insulating layer 130A, and the insulating layer 150. From another perspective, the thin-film transistor 1 can also be a multi-channel thin-film transistor (TFT), which are interconnected, effectively increasing the inrush current flowing through the thin-film transistor 1.

[0034] Fig. Figures 3A to 3E are schematic cross-sectional views of a partial fabrication process of a thin-film transistor according to an embodiment of the present disclosure. Fig. 3A A substrate 100 is first provided, and a buffer layer 140, a second semiconductor layer 120B, an insulating layer 150, and a first gate 110A are successively formed on the substrate 100. The first gate 110A has a top surface 111A and a corresponding side surface 112A. The method for forming the aforementioned layers can be physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD) and is carried out by a photolithographic process. The present disclosure is not limited to this. It should be noted that in Fig. Figure 3A shows only the first gate 110A and part of the insulating layer 150 schematically. The relative relationships of the elements mentioned above can be applied to the structure described above. Fig. 1, which is not repeated here.

[0035] As in Fig.As shown in Figure 3B, a gate insulating layer is then formed on the first gate 110A. For example, the method for forming the preceding elements can be applied to directly form inorganic insulating material on insulating layer 150 and the first gate 110A to form the aforementioned first sublayer 131A. It should be noted that in the implementation where the gate insulating layer is a single insulating layer, the same insulating material can also be deposited on insulating layer 150 and the first gate 110A in this step. The present disclosure is not limited to this.

[0036] As in Fig.As shown in 3C, the gate insulating layer is then etched. For example, a photoresist layer PR can be formed on the first sublayer 131A by coating or centrifugation, as well as by baking and development processes. The photoresist layer PR can be structured such that a portion of the first sublayer 131A, which overlaps with the first gate 110A, is not covered by the photoresist layer PR. Then, according to Fig.In 3D, an etching process is performed on the first sublayer 131A, such that the first sublayer 131A exposes a portion of the top surface 111A and a portion of the side surface 112A. The etching process can be wet or dry etching, and the present disclosure is not limited to either. For example, an etchant with different etch rates can be used for the first sublayer 131A and the first gate 110A, such that a portion of the first sublayer 131A adjacent to the side surface 112A and not covered by the photoresist layer PR is more heavily eroded, forming a concave structure CA adjacent to the side surface 112A. At this point, the thickness of the first sublayer 131A (or it can be interpreted as part of the first gate insulating layer 130A) is reduced.

[0037] As in Fig.As shown in Figure 3E, the second sublayer 132A can be formed on the first sublayer 131A to form the first gate insulating layer 130A. Due to the concave structure CA of the first sublayer 131A, after the formation of the second sublayer 132A, the contour of the upper surface (i.e., the surface of the second sublayer 132A facing away from the first sublayer 131A) of the first gate insulating layer 130A can have a first surface F1, a second surface F2, a third surface F3, and a fourth surface F4, arranged sequentially to form a groove GR1. The groove GR1 can be located on both side faces 112A of the first gate 110A in the Y direction. The first semiconductor layer 120A is also formed, with the second sublayer 132A positioned between the first semiconductor layer 120A and the first gate 110A.At this point, the previously mentioned assembly of the first gate insulating layer 130A and the first semiconductor layer 120A is provisionally completed. The related features and explanations can be found in the preceding sections and are not repeated here. Since the thickness of the first gate insulating layer 130A is reduced and planarized, the step difference on the top surface of the first gate insulating layer 130A can be attenuated, allowing the first semiconductor layer 120A to be formed on a relatively flat surface. This indirectly improves the production yield of the first semiconductor layer 120A and the thin-film transistor 1.

[0038] It must be explained here that the following implementation example reuses the reference numbers and partial content from the previous implementation example, using the same numbers to represent identical or similar elements and omitting explanations of identical technical content. Explanations of the omitted parts can be found in the preceding implementation example. The following implementation example will not repeat these details.

[0039] Fig. Figure 4 is a circuit diagram of a pixel structure according to an embodiment of the present disclosure. Referring to Fig.Figure 4 includes the pixel structure 10, a capacitor Cst, a light-emitting diode LED, and a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. In this embodiment, the first transistor T1 through the seventh transistor T7 can be P-type transistors, but the present disclosure is not limited to this. In other embodiments, the first transistor T1 through the seventh transistor T7 can be N-type transistors. The light-emitting diode LED has an anode terminal and a cathode terminal, receiving the system's low voltage OVSS. The light-emitting diode LED can be at least one micro LED, one submillimeter LED, or one organic LED.The capacitor Cst has an A terminal and a B terminal, wherein the A terminal is electrically connected to the fourth transistor T4 and the fifth transistor T5, and the B terminal is electrically connected to the third transistor T3 and the sixth transistor T6, meaning that the pixel structure 10 has a 7T1C structure. In other embodiments, the pixel structure can have a 2T1C structure, a 3T1C structure, a 3T2C structure, a 4T1C structure, a 4T2C structure, a 5T1C structure, a 5T2C structure, a 6T1C structure, a 6T2C structure, a 7T2C structure, or any possible pixel structure for driving the light-emitting element LED. The present disclosure is not limited to these.

[0040] The source of the first transistor T1 is electrically connected between the second transistor T2 and the third transistor T3, for example, electrically between the drain of the third transistor T3 and the source of the second transistor T2. The gate of the first transistor T1 can receive a first sampling signal S1, and the drain of the first transistor T1 can receive a first reference voltage Vn.

[0041] The source of the second transistor T2 can be electrically connected to the drain of the third transistor T3, and the drain of the second transistor T2 can be electrically connected between the sixth transistor T6 and the seventh transistor T7, for example, between the drain of the sixth transistor T6 and the source of the seventh transistor T7. The source of the third transistor T3 is electrically connected to the B terminal of capacitor Cst. The gate of the second transistor T2 and the gate of the third transistor T3 can receive a second sampling signal S2. It is particularly noted that the first sampling signal S1 and the second sampling signal S2 can be transmitted separately via different sampling lines in a display (not shown).The first sampling signal S1 and the second sampling signal S2 can be voltage signals with the same waveform and intensity but different phases, in order to drive the corresponding transistors sequentially at different time intervals. The present disclosure is not limited to this.

[0042] With further reference to Fig.4. The source of the fourth transistor T4 receives a data voltage Data, the drain of the fourth transistor T4 is electrically connected to the A terminal of capacitor Cst, and the gate of the fourth transistor T4 receives the second sampling signal S2. The source of the fifth transistor T5 receives a second reference voltage Vp, and the drain of the fifth transistor T5 is electrically connected to the A terminal of capacitor Cst. The data voltage Data can be transmitted via a data line in the display (not shown); therefore, the source, gate, and drain of the fourth transistor T4 can be directly electrically connected to the data line, the sampling line, and the fifth transistor T5, respectively. From another perspective, the fourth transistor T4 can also be defined as a switching thin-film transistor, but the present disclosure is not limited to this.

[0043] The source of the sixth transistor T6 receives a system high voltage OVDD, the drain of the sixth transistor T6 is electrically connected to the source of the seventh transistor T7, and the gate of the sixth transistor T6 is electrically connected to the B terminal of capacitor Cst. The source of the seventh transistor T7 can be directly electrically connected to the drain of the sixth transistor T6, the drain of the seventh transistor T7 is electrically connected to the anode terminal of the light-emitting element LED, and the gate of the seventh transistor T7 receives a light emission signal EM.

[0044] The pixel structure 10 can operate sequentially in a first period, a second period and a third period, where the second period contains a preset time t1 and the preset time t1 immediately follows the first period (i.e. at the beginning of the second period) and is smaller than the second period.During the first period, the first transistor T1 receives the first sampling signal S1 and is in a switched-on state, while the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are in a switched-off state; during the second period, the second transistor T2, the third transistor T3, and the fourth transistor T4 receive the second sampling signal S2 and are in a switched-on state, while the first transistor T1 remains in a switched-on state for the preset time t1 of the second period; during the third period, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are in a switched-off state.

[0045] If, during the first period, the first transistor T1 receives the first sampling signal S1 and is in a switched-on state, the signal of the first reference voltage Vn can therefore be transmitted to the source of the first transistor T1. If, during the preset time t1 of the second period, the second transistor T2, the third transistor T3, and the fourth transistor T4 are in a switched-on state, the signal of the data voltage Data can therefore be transmitted to the A terminal of capacitor Cst, and the first reference voltage Vn can be transmitted to the B terminal of capacitor Cst.Then, when the pixel structure 10 is in the second period, but beyond the preset time t1, the first transistor T1 is in an off state, but the second transistor T2, the third transistor T3 and the fourth transistor T4 are still in an on state, at this time the potential of the gate of the sixth transistor T6 is equal to the high voltage OVDD minus the threshold voltage Vth, that is (OVDD-Vth).

[0046] When, in the third period, the second transistor T2, the third transistor T3, and the fourth transistor T4 are in an off state, the fifth transistor T5 and the seventh transistor T7 receive the light emission signal EM and are in an on state. At this point, the potential of terminal A of capacitor Cst changes from the data voltage Data to the second reference voltage Vp, where the change is represented as (Vp-Data). Therefore, the potential of terminal B of capacitor Cst changes in the second period from (OVDD-Vth) to (OVDD-Vth) + (Vp-Data). According to the following relation equation (1), the current (Id) of the transistor: Id = K(Vs-Vg-|Vth|) 2; where K is a constant related to the transistor structure, Vg is the gate voltage of the transistor, which for the sixth transistor T6 is (OVDD-Vth)+ (Vp-Data); Vs is the voltage at the source, which for the sixth transistor T6 is the high voltage OVDD. By substituting the value of the high voltage OVDD into Vs in equation (1) and substituting the value of (OVDD-Vth)+ (Vp-Data) into Vg in equation (1), Id=K(Data-Vp) can be obtained. 2The light-emitting element LED is driven by the current (i.e., Id) flowing through the sixth transistor T6 when it is switched on, T6 can also be defined as a driving thin-film transistor. The current (i.e., Id) flowing through the seventh transistor T7 enables the LED to emit light; therefore, T7 can also be defined as a light-signal-controlling thin-film transistor.

[0047] As mentioned above, it can also be seen from equation (1) and the conclusion that the brightness of the light-emitting element LED is not affected by the threshold voltage Vth of the sixth transistor T6, thus giving the display, which uses the pixel structure 10, a uniform brightness. Furthermore, since the current flowing through the sixth transistor T6 and the seventh transistor T7 in the pixel structure 10 is relatively large, at least one of the sixth transistor T6 and the seventh transistor T7 can be manufactured using the thin-film transistor 1 of this embodiment, which can have advantages such as high current gain, reduced cross-voltage, and the provision of a high current. If the light-emitting element LED is a micro LED, it can offer the advantage of high brightness combined with good stability.

[0048] Fig.Figures 5A to 5C are schematic cross-sectional views of thin-film transistors in various embodiments of the present disclosure. With reference to Fig. 5A, the thin-film transistor 1A is similar to the previously mentioned thin-film transistor 1, the main difference being that the thin-film transistor 1A can contain in the Z direction the buffer layer 140, the second semiconductor layer 120B, the insulating layer 150, the first gate 110A, the first gate insulating layer 130A and the second gate insulating layer 130B, which are arranged sequentially from the substrate 100 to the junction 160, without the second gate 110B being built up.

[0049] With reference to Fig.5B, the thin-film transistor 1B is similar to the thin-film transistor 1 mentioned above, the main difference being that the thin-film transistor 1B can contain in the Z direction the buffer layer 140, the insulating layer 150, the first gate insulating layer 130A, the first semiconductor layer 120A, the second gate insulating layer 130B and the second gate 110B, which are arranged sequentially from the substrate 100 to the junction 160, without the first gate 110A and the second semiconductor layer 120B being built up.

[0050] With reference to Fig.5C, the thin-film transistor 1C resembles the thin-film transistor 1 mentioned above, the main difference being that the thin-film transistor 1C can contain, in the direction Z, the buffer layer 140, the insulating layer 150, the first sublayer 131A, the first gate 110A, the second sublayer 132A, the first semiconductor layer 120A, the second gate insulating layer 130B, and the second gate 110B, arranged sequentially from the substrate 100 to the junction 160, without the second semiconductor layer 120B being built up. In other words, the thin-film transistor 1C can be a two-gate type thin-film transistor. Although in the embodiments of Fig. 5B to 5C not shown, the first gate insulating layer 130A can also be used with the one in Fig. The groove structure GR1 shown in Figure 1B is formed on the side surface of the first gate 110A. The relevant content can be found in the aforementioned sections and is not repeated here.

[0051] The aforementioned thin-film transistors 1A to 1C can all be arranged in the same pixel structure 10 and applied to different transistor types. For example, in Fig.The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 all adopt the structural design of the thin-film transistor 1B on the upper layer, while the sixth transistor T6 and the seventh transistor T7 can both be the structural design of the thin-film transistor 1A on the lower layer. In addition to the larger structure of the sixth transistor T6 and the seventh transistor T7 to meet their high power supply requirements, the structure of different transistors located in different layers can also effectively reduce the area occupied by the pixel structure 10 on the substrate 100. When the pixel structure 10 is applied to a display panel (not shown), it is also possible to increase the pixel density (PPI) and the resolution of the display panel. Of course, the present disclosure is not limited to this.

[0052] Fig. Figure 6A is a schematic cross-sectional view of a thin-film transistor according to an embodiment of the present disclosure. Fig. 6B is an enlarged schematic view of area A2 in Fig. 6A. With reference to Fig.6A, the thin-film transistor 1D is similar to the previously mentioned thin-film transistor 1, the main difference being that the thin-film transistor 1D also includes an insulating layer 151, which is arranged between the second gate 110B and the second semiconductor layer 120B, with the second gate 110B being located between the first semiconductor layer 120A and the second semiconductor layer 120B. Furthermore, the thin-film transistor 1D also includes a third gate 110C and a third-gate insulating layer 130C. The third gate 110C is located on the second semiconductor layer 120B and overlaps with the second channel region 122B. The third-gate insulating layer 130C is located between the third gate 110C and the second semiconductor layer 120B to electrically isolate these two.

[0053] Specifically, the thin-film transistor 1D can contain, in the Z direction, the buffer layer 140, the first gate 110A, the first gate insulating layer 130A, the first semiconductor layer 120A, the second gate insulating layer 130B, the second gate 110B, the insulating layer 150, the insulating layer 151, the second semiconductor layer 120B, and the third gate insulating layer 130BC, arranged sequentially from the substrate 100 to the junction 160. In this embodiment, the first semiconductor layer 120A and the second semiconductor layer 120B of the thin-film transistor 1D can each be electrically controlled by two gates, which can also be interpreted as the thin-film transistor 1D containing two dual-gate transistors. In other embodiments, the first gate 110A can serve as wiring for other functions to increase the layout flexibility of the circuit.In some embodiments, the first gate 110A can, for example, serve as a shielding layer to provide protection against electrostatic discharge (ESD). Depending on the design requirements, the first gate 110A may or may not be connected to a potential (for example, floating connection, ground potential, serving as a common electrode (vcom), source, or drain) and may be connected to external circuits at other positions within the thin-film transistor 1D by internal wiring (not shown). The present disclosure is not limited to these possibilities.

[0054] With further reference to Fig.6B, the insulating layer 151 can also have a similar contour to the first gate insulating layer 130A. Furthermore, the first semiconductor layer 120A, the insulating layer 150, and the insulating layer 151 can employ a similar planarization process as the aforementioned first gate insulating layer 130A to reduce step differences, so that the upper surface of the insulating layer 151 (i.e., the surface of the insulating layer 151 facing away from the first gate 110A) can also have a groove GR2. The position of groove GR2 can overlap with the position of groove GR1 and have similar properties and thickness ratios to the previously mentioned groove GR1. Fig.1B. In other words, the second semiconductor layer 120B above the insulating layer 151 and the first semiconductor layer 120A above the second sublayer 132A can both be formed on a relatively flat surface to improve the electrical properties and the efficiency of the thin-film transistor 1D, and the thickness of the first gate 110A and the second gate 110B does not need to be reduced, while maintaining their good conductivity. Reference may be made to related content in the aforementioned sections, which will not be repeated here.

[0055] Fig. Figure 7 is a schematic cross-sectional view of a thin-film transistor according to an embodiment of the present disclosure. With reference to Fig.7. Thin-film transistor 1E is similar to thin-film transistor 1 mentioned above, with the main difference being that in thin-film transistor 1E, the heavily doped region of the first semiconductor layer 120A extends into the projection of the second gate 110B, and vice versa. Specifically, the first source region 121A of the first semiconductor layer 120A can contain a first heavily doped region HD1A and a second heavily doped region HD2A, and the first drain region 123A can contain a lightly doped region LDA and a third heavily doped region HD3A.Furthermore, in the Y direction, the first heavily doped region HD1A is located between the second heavily doped region HD2A and the first channel region 122A; the first channel region 122A is located between the first heavily doped region HD1A and the lightly doped region LDA; the lightly doped region LDA is located between the first channel region 122A and the third heavily doped region HD3A; and there is a boundary I2 between the first channel region 122A and the lightly doped region LDA and a boundary I1 between the first channel region 122A and the first heavily doped region HD1A. Additionally, the length of the first heavily doped region HD1A extends in the Y direction, such that the first heavily doped region HD1A overlaps with the second gate 110B in the Z direction.

[0056] In particular, the doping concentration of the first highly doped region HD1A and the second highly doped region HD2A can be selectively different (for example: the doping concentration of the first highly doped region HD1A is higher than the doping concentration of the second highly doped region HD2A), but the present disclosure is not limited to this. As already mentioned, boundary I1 and boundary I2 are not visible and represent virtual boundaries between two regions with different doping concentrations.By reducing the length of the first channel region 122A in the direction of Y (that is, the horizontal distance between the boundary I1 and the boundary I2 in the direction of Y), a carrier channel with a shorter length can be generated, which can increase the inrush current flowing through the thin-film transistor 1E, so that the thin-film transistor 1E can provide good electrical properties when applied to elements that require a high current.

[0057] Similarly, the second source region 121B of the second semiconductor layer 120B can contain a first heavily doped region HD1B and a second heavily doped region HD2B, and the second drain region 123B can contain a lightly doped region LDB and a third heavily doped region HD3B. Furthermore, in the Y direction, the first heavily doped region HD1B is located between the second heavily doped region HD2B and the second channel region 122B, the second channel region 122B is located between the first heavily doped region HD1B and the lightly doped region LDB, the lightly doped region LDB is located between the second channel region 122B and the third heavily doped region HD3B, and the second channel region 122B and the lightly doped region LDB also have a boundary I2, while the second channel region 122B and the first heavily doped region HD1B also have a boundary I1.Furthermore, the length of the first heavily doped region HD1B extends in the Y direction, such that the first heavily doped region HD1B overlaps with the first gate 110A in the Z direction. The configuration relationship of various doped regions in the second semiconductor layer 120B can be the same as the configuration relationship of the first semiconductor layer 120A; therefore, the second semiconductor layer 120B can also have similar properties and effects to the first semiconductor layer 120A, which will not be repeated here.

[0058] Fig. Figure 8 is a schematic cross-sectional view of a portion of a pixel structure according to an embodiment of the present disclosure. Referring to Fig.8. The pixel structure 10 can also contain other film layers above it, such as a planarization layer 170 and a dielectric layer 180. The dielectric layer 180 can be located between the third gate insulating layer 130C and the planarization layer 170, and the planarization layer 170 can be located between the dielectric layer 180 and the junction 160. On the other hand, the thin-film transistor T can have a similar structure to the thin-film transistors 1A to 1D mentioned above, which will not be repeated here. It is worth noting that in Fig.8. The first gate 110A, the second gate 110B, and the third gate 110C in the thin-film transistor T can be connected in series. Alternatively, the thin-film transistor T can be electrically connected to the capacitor Cst. The capacitor Cst can have a metal layer M1, a metal layer M2, and a metal layer M3, and its internal structure can be formed by the buffer layer 140, the first gate insulating layer 130A, and the second gate insulating layer 130B.

[0059] In summary, during the fabrication process of the thin-film transistor of the present disclosure, the step difference formed by the overlying gate insulating layer can also be reduced, or the upper surface of the gate insulating layer can be relatively flat, due to the flattening of the topography of the gate insulating layer above the gate while maintaining a certain thickness of the gate metal layer to ensure better electrical performance. Therefore, the semiconductor layer on the upper surface of the gate insulating layer can also grow on a relatively flat surface, which reduces the probability of semiconductor layer breakage during the process and further improves the performance and process yield of the thin-film transistor. Description of the reference symbols 1, 1A, 1B, 1C, 1D, 1E, T thin film transistor 10 pixel structure 100 substrate 110A first gate 110B second gate 110C third gate 111A Top 112A Side surface 120A first semiconductor layer 120B second semiconductor layer 121A first source area 121B second source area 1211A, 1211B first lightly doped area 1212A, 1212B, HD1 first heavily doped area 122A first channel area 122B second channel area 123A First drainage area 123B second drain area 1231A, 1231B second lightly doped area 1232A, 1232B, HD2 second heavily doped area 130A first gate insulating layer 130B second gate insulating layer 130C third gate insulating layer 131A first sub-layer 132A second sublayer 140 buffer layer 150, 151 Insulating layer 160 barrier layer 170 Planarization layer 180 dielectric layer A1, A2 area CA concave structure Cst capacitor D Drain D1, D1', D2, D2', D3, D3', D31, D32, D33, D34, D35, D4, D110, D120, D132, D150 thickness Data Data voltage DG Depth DIS interrupted area exL extension level EM light emission signal F1 first surface F2 second surface F3 third surface F4 fourth surface G Gate GL1, GL Gate insulating layer GR1, GR2 groove HD3 third highly endowed area I1, I2 boundary LDA, LDB lightly funded area M1, M2, M3 Metal layer OVDD High Voltage PR photoresist layer S Source S1 first sampling signal S2 second sampling signal SA1, SB1 first page SA2, SB2 second page SM semiconductor layer T1 first transistor T2 second transistor T3 third transistor T4 fourth transistor T5 fifth transistor T6 sixth transistor T7 seventh transistor THA1, THA2, THB1, THB2 Through hole Vn first reference voltage Vp second reference voltage X, Y, Z direction

Claims

Thin-film transistor (1, 1A, 1B, 1C, 1D, 1E, T), comprising: a substrate (100); a first gate (110A) arranged on the substrate (100), having a top surface (111A) and a side surface (112A) connected to the top surface (111A); a first semiconductor layer (120A) arranged on the substrate (100), the first semiconductor layer (120A) comprising a first drain region (123A), a first channel region (122A), and a first source region (121A), and the first gate (110A) overlapping the first channel region (122A);and a first gate insulating layer (130A) arranged between the first semiconductor layer (120A) and the first gate (110A), wherein a contour of an upper surface of the first gate insulating layer (130A) has a first surface (F1), a second surface (F2), a third surface (F3), and a fourth surface (F4) arranged sequentially to form a groove (GR1, GR2), wherein the first surface (F1) overlaps the top surface (111A), the second surface (F2) and the third surface (F3) overlap the side surface (112A), and the fourth surface (F4) overlaps the substrate (100), wherein a thickness (D1) of the first gate insulating layer (130A) on the first surface (F1) is less than a thickness (D2) of the first gate insulating layer (130A) on the second surface (F2), and a thickness of the first The gate insulating layer (130A) increases from the third surface (F3) to the fourth surface (F4). Thin-film transistor (1, 1A, 1B, 1C, 1D, 1E, T) according to claim 1, further comprising: a second gate insulating layer (130B) arranged on the first semiconductor layer (120A); and a second gate (110B) arranged on the second gate insulating layer (130B). Thin-film transistor (1, 1A, 1B, 1C, 1D, 1E, T) according to claim 2, further comprising: a second semiconductor layer (120B) arranged on the substrate (100), wherein the second semiconductor layer (120B) comprises a second drain region (123B), a second channel region (122B) and a second source region (121B), wherein the second channel region (122B) overlaps with the first gate (110A), wherein a depth (DG) of the groove (GR1, GR2) is less than a maximum thickness (D120) of the second semiconductor layer (120B). Thin-film transistor (1, 1A, 1B, 1C, 1D, 1E, T) according to claim 3, further comprising: a buffer layer (140) arranged between the substrate (100) and the second semiconductor layer (120B), wherein the second semiconductor layer (120B) is arranged between the substrate (100) and the first gate (110A). Thin-film transistor (1, 1A, 1B, 1C, 1D, 1E, T) according to claim 4, further comprising: an insulating layer (150) arranged between the second semiconductor layer (120B) and the first gate (110A), wherein a thickness (D150) of the insulating layer (150) is greater than a thickness (D132) of the first gate insulating layer (130A) on the top side (111A). Thin-film transistor (1, 1A, 1B, 1C, 1D, 1E, T) according to claim 3, further comprising: an insulating layer (151) arranged between the second gate (110B) and the second semiconductor layer (120B), wherein the second gate (110B) is arranged between the first semiconductor layer (120A) and the second semiconductor layer (120B). Thin-film transistor (1, 1A, 1B, 1C, 1D, 1E, T) according to claim 6, further comprising: a third gate (110C) arranged on the second semiconductor layer (120B) and overlapping with the second channel region (122B); and a third gate insulating layer (130C) arranged between the third gate (110C) and the second semiconductor layer (120B). Thin-film transistor (1, 1A, 1B, 1C, 1D, 1E, T) according to claim 7, wherein the first gate (110A), the second gate (110B) and the third gate (110C) are connected in series. Thin-film transistor (1, 1A, 1B, 1C, 1D, 1E, T) according to claim 1 , wherein a depth (DG) of the groove (GR1, GR2) is greater than 0 micrometers and less than half a thickness (D110) of the first gate (110A). Thin-film transistor (1, 1A, 1B, 1C, 1D, 1E, T) according to claim 3, further comprising: a drain (D) that is directly electrically connected to a first side (SA1, SB1) of the first semiconductor layer (120A) and a first side (SB1) of the second semiconductor layer (120B); and a source (S) that is directly electrically connected to a second side (SA2, SB2) of the first semiconductor layer (120A) and a second side (SB2) of the second semiconductor layer (120B), wherein the first side (SA1, SB1) and the second side (SA2, SB2) of the first semiconductor layer (120A) are opposite each other, and the first side (SA1, SB1) and the second side (SA2, SB2) of the second semiconductor layer (120B) are opposite each other. Thin-film transistor (1, 1A, 1B, 1C, 1D, 1E, T) according to claim 1, wherein the first gate insulating layer (130A) comprises a first sublayer (131A) and a second sublayer (132A), the first sublayer (131A) being arranged between the first gate (110A) and the second sublayer (132A), and wherein the first sublayer (131A) covering the side surface (112A) of the first gate (110A), the first sublayer (131A) forming a concave structure (CA) on the side surface (112A) of the first gate (110A) and the concave structure (CA) overlapping the groove (GR1, GR2). Thin-film transistor (1, 1A, 1B, 1C, 1D, 1E, T) according to claim 11, wherein the second sublayer (132A) contacts a part of the top surface (111A) of the first gate (110A), the concave structure (CA) and a top surface of the first sublayer (131A). Thin-film transistor (1, 1A, 1B, 1C, 1D, 1E, T) according to claim 1, wherein the first semiconductor layer (120A) comprises a first heavily doped region (1212A, 1212B, HD1), a second heavily doped region (1232A, 1232B, HD2), a third heavily doped region (HD3A), and a lightly doped region (LDA, LDB), wherein the first heavily doped region (1212A, 1212B, HD1) is arranged between the second heavily doped region (1232A, 1232B, HD2) and the first channel region (122A), the first channel region (122A) is arranged between the first heavily doped region (1212A, 1212B, HD1) and the lightly doped region (LDA, LDB), the lightly doped region (LDA, LDB) between the first The first channel area (122A) and the third heavily doped area (HD3A) are arranged, and a boundary (I1, I2) exists between the first channel area (122A) and the lightly doped area (LDA, LDB). Thin-film transistor (1, 1A, 1B, 1C, 1D, 1E, T) according to claim 3, wherein the second semiconductor layer (120B) comprises a first heavily doped region (1212A, 1212B, HD1), a second heavily doped region (1232A, 1232B, HD2), a third heavily doped region (HD3A), and a lightly doped region (LDA, LDB), wherein the first heavily doped region (1212A, 1212B, HD1) is arranged between the second heavily doped region (1232A, 1232B, HD2) and the second channel region (122B), the second channel region (122B) is arranged between the first heavily doped region (1212A, 1212B, HD1) and the lightly doped region (LDA, LDB), and the lightly doped region (LDA, LDB) is arranged between the second The channel area (122B) and the third heavily doped area (HD3A) are arranged, and a boundary (I1, I2) exists between the channel area and the lightly doped area (LDA, LDB). Pixel structure (10) comprising: a self-illuminating element; and a plurality of thin-film transistors (1, 1A, 1B, 1C, 1D, 1E, T), wherein at least one of the thin-film transistors (1, 1A, 1B, 1C, 1D, 1E, T) has a structure of the thin-film transistor (1, 1A, 1B, 1C, 1D, 1E, T) according to claim 1, wherein the at least one of the thin-film transistors (1, 1A, 1B, 1C, 1D, 1E, T) is electrically connected to the self-illuminating element, and the self-illuminating element comprises at least one micro-LED, a sub-millimeter LED or an organic LED. Pixel structure (10) according to claim 15, wherein the at least one of the thin-film transistors (1, 1A, 1B, 1C, 1D, 1E, T) is a driving thin-film transistor or a light-signal-controlling thin-film transistor. Pixel structure (10) according to claim 15, wherein at least one further of the thin-film transistors (1, 1A, 1B, 1C, 1D, 1E, T) is a switching thin-film transistor, and three terminals of the switching thin-film transistor are each electrically connected to a data line, a scanning line and the at least one of the thin-film transistors (1, 1A, 1B, 1C, 1D, 1E, T). Method for fabricating a thin-film transistor (1, 1A, 1B, 1C, 1D, 1E, T), comprising: forming a gate (G) on a substrate (100) having a top surface (111A) and a side surface (112A) connected to the top surface (111A); forming a gate insulating layer (GL1, GL) on the gate (G); etching the gate insulating layer (GL1, GL) such that a contour of a top surface of the gate insulating layer (GL1, GL) has a first surface (F1), a second surface (F2), a third surface (F3) and a fourth surface (F4) arranged sequentially to form a groove (GR1, GR2);and forming a semiconductor layer (SM) such that the gate insulating layer (GL1, GL) is arranged between the semiconductor layer (SM) and the gate (G), wherein the first surface (F1) overlaps the top surface (111A), the second surface (F2) and the third surface (F3) overlap the side surface (112A), and the fourth surface (F4) overlaps the substrate (100), wherein a thickness (D1, D1', D2, D2', D3, D3', D31, D32, D33, D34, D35, D4, D110, D120, D132, D150) of the gate insulating layer (GL1, GL) on the first surface (F1) is less than a thickness (D1, D1', D2, D2', D3, D3', D31, D32, D33, D34, D35, D4, D110, D120, D132, D150) of the gate insulating layer (GL1, GL) on the second surface (F2), and a thickness (D1, D1', D2, D2', D3, D3', D31, D32, D33, D34, D35, D4, D110, D120, D132, D150) of the gate insulating layer (GL1, GL) increases from the third surface (F3) to the fourth surface (F4).

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