GROUP III N DEVICE INCLUDING CONTACTS WITH MULTIPLE CONDUCTIVE COLUMNS

Abstract

Semiconductor devices, including contacts with multiple conductive pillars, are described. In one example, a semiconductor device comprises a semiconductor substrate containing a source region, a gate region, a drain region, and a drain access region, with a III-N heterojunction structure arranged over the semiconductor substrate. The III-N heterojunction structure includes a buffer layer above the semiconductor substrate and a barrier layer above the buffer layer. A contact is arranged in the source region and / or a drain region, the contact comprising multiple conductive pillars coupled to the III-N heterojunction structure.

Description

AREA OF REVELATION

[0001] Disclosed implementations generally relate to the field of Group III N semiconductor devices and their fabrication. BACKGROUND

[0002] Group III nitride materials (also known as III-N materials) possess a unique combination of physical and electrical properties that have proven advantageous in modern microelectronics and optoelectronics. These properties include a wide bandgap, high saturation drift velocity and breakdown voltage, high thermal conductivity, robust chemical and thermal stability, and more. Because of these characteristics, III-N materials are considered promising materials for fabricating high-performance, high-frequency transistors capable of operating at high temperatures and in harsh environments. Although advances in III-N devices and their fabrication continue to progress rapidly, some gaps remain, necessitating further innovation, as outlined below. SUMMARY

[0003] The following is a simplified summary to provide a basic understanding of some examples in this disclosure. This summary is not a comprehensive overview of the examples and is not intended to identify key or critical elements of the examples, nor to define the scope of protection. Rather, the main purpose of this summary is to present some concepts of this disclosure in a simplified form as an introduction to a more detailed description, which will be presented in subsequent sections below.

[0004] In one example, a semiconductor device comprises a semiconductor substrate containing a source region, a gate region, a drain region, and a drain access region between the gate region and the drain region, wherein a III-N heterojunction structure is arranged over the semiconductor substrate. The III-N heterojunction structure includes a buffer layer over the semiconductor substrate and a barrier layer over the buffer layer. A contact is arranged in the source region and / or a drain region, wherein the contact includes multiple conductive pillars coupled to the III-N heterojunction structure.

[0005] In one example, a method for fabricating a semiconductor device is disclosed. The method includes, among other things, the following: forming a III-N heterojunction structure over a semiconductor substrate, the structure comprising a source region, a gate region, a drain region, and a drain access region between the gate region and the drain region, wherein the III-N heterojunction structure includes a buffer layer over the semiconductor substrate and a barrier layer over the buffer layer; and forming a contact in the source region and / or the drain region, wherein the contact includes multiple conductive pillars coupled to the III-N heterojunction structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Implementations of this disclosure are illustrated in the figures of the accompanying drawings by way of example and without limitation. Different references to “one” implementation in this disclosure do not necessarily refer to the same implementation, and such references may mean at least one. Furthermore, if a particular feature, structure, or characteristic is described in connection with one implementation, such feature, structure, or characteristic may be feasible in connection with other implementations, regardless of whether this is explicitly described or not.

[0007] The accompanying drawings are incorporated into the text and form part of it to illustrate one or more implementation examples of the present disclosure. Various advantages and features of the disclosure are described in detail below in conjunction with the appended claims and with reference to the accompanying drawings of the figures, in which the following applies: Fig. 1A represents a layout of a semiconductor device including contacts with multiple conductive columns according to some examples of the present disclosure; Fig. Figures 1B-1 to 1B-3 represent cross-sectional views of a contact of a semiconductor device according to some examples; Fig. 2A to 2H-2 represent layouts of multi-column contacts that can be used for source and / or drain electrodes of a semiconductor device, according to some examples; Fig. Figures 3A to 3I-3 represent cross-sectional views of a semiconductor device including a GaN device at various stages of a process flow according to an example in the present disclosure; Fig. Figure 4 shows a cross-sectional view of a semiconductor device including a GaN device according to another example in the present disclosure; Fig. 5A and Fig. 5B are flowcharts of processes for manufacturing a semiconductor device including contacts with multiple conductive columns according to some examples in the present disclosure; and Fig. Figure 6 represents an exemplary GaN resistor including multi-column contacts according to an example in the present disclosure. DETAILED DESCRIPTION

[0008] Examples of the disclosure are described with reference to the attached figures, with the same reference numbers being used generally to refer to the same elements. The figures are not drawn to scale and are provided only to illustrate examples. Numerous specific details, relationships, and procedures are subsequently set forth to provide an understanding of one or more examples. However, some examples can be implemented without such specific details. In other cases, well-known subsystems, components, structures, and techniques have not been shown in detail so as not to obscure the understanding of the examples. Accordingly, the examples of the present disclosure can be implemented without such specific components.

[0009] Furthermore, terms such as "coupled" and "connected," along with their derivatives, may be used in the following description, claims, or both. It is understood that these terms are not necessarily intended to be synonymous. "Coupled" may be used to indicate that two or more elements, which may or may not be in direct physical or electrical contact with each other, work together or interact. "Connected" may be used to indicate the establishment of communication, i.e., a communicative relationship, between two or more elements that are coupled together.Furthermore, in one or more of the examples presented here, generally speaking, an element, component or module can be configured to perform a function if the element can be programmed to perform this function or otherwise structurally set up to perform it.

[0010] Without limitation, examples of the present disclosure are set forth below in the context of improving the performance characteristics of semiconductor devices based on group III nitride materials, also referred to as III-N materials, such as gallium nitride (GaN) devices.

[0011] GaN devices, e.g., GaN transistors, offer certain performance advantages over silicon, including, among others, a lower one-state resistance (e.g., drain-source resistance or R). DSONGaN transistors offer lower switching losses and improved breakdown voltage. They incorporate a heteroepitaxic structure with a junction between materials with different band gaps (e.g., a heterojunction structure), such as aluminum gallium nitride (AlGaN) and gallium nitride, to provide a two-dimensional electron gas (2DEG) formed within the AlGaN / GaN heteroepitaxic structure. This gas is used for device operation—for example, forming a channel within the GaN device. The two-dimensional electron gas (2DEG) can be referred to as a 2DEG channel. Depletion-mode (DMODE) GaN transistors are normally open, whereas enhancement-mode (EMODE) GaN transistors are normally closed. In some examples, EMODE-GaN transistors include a gate stack with a p-doped gallium nitride (p-GaN) layer that depletes the 2DEG below the gate stack at a bias of zero or negative bias.In some examples, the p-GaN layer may comprise a GaN layer doped with magnesium (Mg) or other p-type dopants. Applying a positive gate voltage improves the 2DEG under the gate and activates the EMODE-GaN device to allow current to flow between the source and drain.

[0012] One of the problems affecting the performance of semiconductor devices, including GaN devices, concerns contact resistance. Since the contact resistance of a device, including source and drain contact resistances, is becoming an increasingly significant component of its overall resistance, efforts are being made, particularly with decreasing line widths, to reduce contact resistance. This reduces power losses in the device and improves its switching performance. Although the fabrication of source / drain contacts in a device requires high-temperature tempering processes (e.g.,While thermal processes may involve temperatures higher than 750 °C to promote the formation of contacts with desirable electrical properties, such processes can give rise to various harmful effects, especially in GaN devices where surface passivation layers may be provided in some implementations.

[0013] For example, a GaN device can be formed with one or more GaN layers over a suitable semiconductor substrate, e.g., including a silicon substrate, where the GaN layers can form a heterojunction structure (e.g., a III-N heterojunction) over the semiconductor substrate. To address adverse effects of charge trapping, such as current breakdown, increased dynamic on-resistance, etc., one or more surface passivation layers can be provided over the heterojunction structure. Furthermore, one or more field plate (FP) structures can be provided in some examples to attenuate the effects of concentrated electric fields in a GaN device, e.g., at the edges of a gate electrode of the device. If FP structures and / or surface passivation layers are implemented, dielectric films with a high dielectric constant (high κ), e.g.,Silicon nitride (SiN) films with κ values ​​in the range of about 7 to about 10 are provided to suppress charge traps and / or reduce susceptibility to high electric fields.

[0014] SiN layers used to provide dielectric separation for FP structures and / or to passivate surface states in GaN devices can represent material compositions containing hydrogen. During high-temperature processes, such as tempering processes at temperatures above 750 °C, used in device contact formation, hydrogen can diffuse into the p-GaN layer of a GaN device. The diffused hydrogen can react with dopants, such as Mg, to form a deactivated dopant complex, reducing the effect of the dopants in the device's operation. Accordingly, the diffused hydrogen in the p-GaN layer can degrade the electrical characteristics of the device, such as a reduced threshold voltage (VT). th ) and transconductance (g m ), an increased punch-through leakage loss, etc.

[0015] Furthermore, charge trapping near the contact of a device (e.g., a drain contact) can be significant in some arrangements under high voltage / current loads, which affects device reliability (e.g., R). DSON -stability) can negatively affect some implementations.

[0016] Examples presented in this disclosure recognize the aforementioned challenges and provide contact designs that not only enable lower contact resistance but also advantageously reduce the risk of p-doping deactivation in certain GaN transistors. In certain arrangements, multiple conductive pillars can be formed as part of a source / drain contact structure, which can increase the total perimeter area in contact with the III-N heterojunction structure—for example, a channel of a GaN transistor containing a 2D electron gas (2DEG) or a 2D hole gas (2DHG). In this way, the overall contact resistance can be reduced (lowered) due to the increased perimeter contact area, as in some examples. Furthermore, a silicon lining can be provided during the formation of conductive pillars to enable a lower-temperature contact annealing process, for example.In some arrangements, this occurs at temperatures below 700 °C. Accordingly, the diffusion of hydrogen from high-κ dielectric layers (e.g., SiN layers) into a p-GaN layer of the device is reduced or suppressed, thereby decreasing the risk of dopant deactivation in the p-GaN layer.

[0017] In some other examples, devices with contacts having multiple conductive columns can offer better reliability (e.g., R). DSON-stability) under high voltage / high current conditions, which can be attributed to the multi-conductor pillar design of the contact. For example, a first set of conductive pillars of a drain contact may be located closer to a gate stack of the GaN transistor than a second set of conductive pillars of the drain contact, so that the first set of conductive pillars can protect (e.g., shield) the second set of conductive pillars from charge trapping events near the drain contact. In other words, due to the corrugated nature of the contact perimeter area, as referenced in Fig. As described in 1B-1 to 1B-3, certain parts of the contact perimeter area (e.g., the inner perimeter area of ​​conductive columns) are shielded from charge trapping events. Although the present examples can provide various structures, materials, and processes that produce these and other advantageous effects, no particular result is a prerequisite unless explicitly stated in a specific claim.

[0018] Referring to the drawings, the Fig. Figure 1A represents a layout of a semiconductor device 100A including a contact design, wherein one or more contacts, each having multiple conductive columns, may be provided to obtain a reduced contact resistance, as shown in some examples. As illustrated, the semiconductor device 100A includes a GaN device 101 with a region 199 (e.g., an active region, a device region, etc.) defined by an isolation boundary 162 formed by a suitable isolation process. The region 199 includes a source region 105A (which may also include a source access region, as explained below), a gate region 105B, a drain region 105D, and a drain access region 105C located between the gate region 105B and the drain region 105D, wherein a gate layer 168 may be provided in the gate region 105B.

[0019] For example, the GaN device 101 can include source / drain contacts 160A and 160B, each containing multiple conductive columns, which may be organized as arrays or in other configurations, in the source and drain areas 105A and 105D, respectively. In some implementations, conductive columns provided to form a source contact (e.g., source contact 160A) may be organized or arranged in a different configuration than the conductive columns provided to form a drain contact (e.g., drain contact 160B). Unless otherwise specified, the terms “column” or “contact column” in the context of a multi-column contact design refer, by way of example, to a vertical conductive column comprising a multilayer stack aligned along a surface normal (e.g., parallel to the Z-axis) of the heterojunction structure of a GaN device, such as the GaN Device 101.In some other contexts, however, the term 'column' can refer to a group of entities provided as part of an array of entities organized in an [NxM] matrix configuration arranged along or on a horizontal surface, where N refers to the number of rows and M refers to the number of columns in the matrix configuration.

[0020] The source contact 160A contains several conductive columns 164A, and the drain contact 160B contains several conductive columns 164B. The conductive columns 164A and 164B can be configured to extend vertically (e.g., along the Z-axis orthogonal to the XY plane) and to be connected to at least a portion of a (in Fig. The heterojunction structure of the GaN device 101 (not explicitly shown) is coupled to form a multi-column source and drain contact 160A, 160B in the source region 105A and the drain region 105D, respectively. Depending on the implementation, each of the multiple conductive columns 164A and 164B can be spatially organized or arranged in various configurations relative to a surface of the heterojunction structure (e.g., parallel to the XY plane), including array configurations with N rows and M columns in some examples.

[0021] As shown, the first multiple conductive columns 164A, organized as a first array (e.g., including N1 rows and M1 columns, where in this particular example N1 equals 4 and M1 equals 2), are provided to form and / or operate as a multi-column source contact 160A in the source area 105A. Similarly, the second multiple conductive columns 164B, organized as a second array (e.g., including N2 rows and M2 columns, where in this particular example N2 equals 4 and M2 equals 2), are provided to form and / or operate as a multi-column drain contact 160B in the drain area 105D.

[0022] Depending on the implementation, each column of the conductive columns 164A, 164B can incorporate a metal silicide formed from a silicon-metal (Si-Met or Si-Met) stack in a multilayer fabrication process including a low-temperature PECVD (plasma-enhanced chemical vapor deposition) silicon deposition process. The silicon layer can enable the formation of an ohmic contact with the heterojunction structure—e.g., a buffer layer including a channel of the GaN device 101 (e.g., a 2DEG or 2DHG)—as described in detail below. Furthermore, in some versions of the examples where a p-GaN layer is provided as part of the GaN device 101, the multi-column contact design can be derived from Fig. 1A, comprising the conductive columns 164A and the conductive columns 164B, may be functional to mitigate doping deactivation of the p-GaN layer of the GaN device 101 in additional and / or alternative arrangements.

[0023] Fig. Figures 1B-1 to 1B-3 represent cross-sectional views of a multi-column contact 100B of a semiconductor device, where conductive columns can be formed as Si-metal stacks or columns in an active region of the semiconductor device, as in some examples. In some arrangements, the multi-column contact 100B, which is shown in Fig. Figures 1B-1 to 1B-3 show a row of conductive columns (e.g., row 166A) formed as part of the first multiple conductive columns 164A and arranged as a [4x2] array in the source region 105A, as shown in Fig. 1A shown. Likewise, in some arrangements, the multi-column contact 100B represents a row of conductive columns (e.g., row 166B) of the second set of multiple conductive columns 164B, which are also arranged as a [4x2] array in the drain region 105D, which is shown in Fig. 1A is shown.

[0024] The in Fig. Examples 1B-1 to 1B-3 illustrate three variations of the multi-column contact 100B, which is formed after a tempering process (e.g., a thermal silicide formation process) is performed as part of a contact metallization. According to the examples presented, a metal silicide can be formed based on a silicon layer and a refractory metal layer of a multi-layer stack, with the silicon and refractory metal layers being combined or consumed to varying degrees. As detailed below, the multi-layer stack can be formed in a process that includes forming the silicon layer, forming the refractory metal layer over the silicon layer, and forming a conductive layer over the refractory layer. In a scenario such as shown in Fig. As illustrated in Figure 1B-1, all the silicon and refractory metal of the multilayer stack can be combined in the tempering process to form a metal silicide. In another scenario, as shown in Fig. As illustrated in Figure 1B-2, not the entire silicon layer is reacted (e.g., transformed or consumed) during the formation of the metal silicide. Accordingly, an unconsumed portion of the silicon layer may remain beneath the metal silicide. In yet another scenario, as shown in Fig. As illustrated in Figure 1B-3, not the entire refractory metal layer is reacted (e.g., converted or consumed) during the formation of the metal silicide, resulting in a configuration where an unreacted portion of the refractory metal layer may remain above the metal silicide. In each of the preceding scenarios, the thickness of the metal silicide, and any remaining portions of the unreacted silicon and / or refractory metal layer in a conductive column, can depend on the respective initial thicknesses of the silicon and refractory metal layers, as well as the processing conditions of an annealing process.

[0025] A detailed description of the 100B multi-column contact follows, with reference to the example from Fig. 1B-1 is set out. The description of the multi-column contact 100B from Fig. 1B-1 can also refer to the in Fig. The examples described in 1B-2 and 1B-3 are applied, with the exception of variations in the metal silicide configurations according to the different scenarios previously outlined. A III-N heterojunction structure 106, comprising a barrier layer 110 over a buffer layer 104, is arranged over a semiconductor substrate 102, as described in more detail below with reference to an exemplary process flow presented in Fig. Figures 3A to 3I-3 illustrate the following. A dielectric stack 108, comprising one or more layers and / or sublayers, is arranged above the III-N heterojunction structure 106, wherein the material composition(s) and / or thickness(es) of the dielectric layers / sublayers of the stack 108 may vary depending on the implementation. A channel 151, e.g., a 2DEG, may be provided near an interface between the barrier layer 110 and the buffer layer 104 to enable device operation according to EMODE or DMODE device functionality.

[0026] As illustrated, the multi-column contact 100B comprises two conductive columns 150A, 150B, which can be formed by a contact formation process including Si deposition and metal stack formation following the formation of contact openings corresponding to the conductive columns 150A, 150B, as described below. In some arrangements, the conductive columns 150A, 150B can be coupled to at least a portion of the III-N heterojunction structure 106 to establish an electrical contact. In some arrangements, the conductive columns 150A, 150B extend into the buffer layer 104 for a distance 152, although this is not a requirement. Each conductive column 150A, 150B includes a metal silicide layer 157A (or, in short, a metal silicide) consisting of a Si layer and a refractory metal layer (in Fig. 1B-1 (not specifically shown) is formed, wherein the metal silicide layer 157A may have sidewalls that contact the buffer layer 104, e.g., including the 2DEG channel 151. A conductive layer 158, comprising, e.g., aluminum, is arranged over the metal silicide 157A, forming a multilayer metal stack 155. A contact pad 159 of the multi-column contact 100B is formed by structuring the multilayer stack 155. In some arrangements, the metal stack 155 may also include a barrier layer comprising a refractory metal (in Fig. 1B-1 to 1B-3 (not specifically shown) comprises the conductive layer 158. Depending on the implementation, the conductive columns 150A and 150B can each have a cross-sectional area in the XY plane, e.g., parallel to a horizontal surface of the III-N heterotransition structure 106, where the cross-sectional areas can be the same or different and can have a variety of shapes and sizes.

[0027] As in Fig. As illustrated in Figure 1B-1, providing multiple conductive columns, e.g., conductive columns 150A, 150B, in a contact design generates more sidewalls than would be available in a single conductive column for contacting the III-N heterojunction structure. The additional sidewalls of the multiple conductive columns 150A, 150B can therefore form a corrugated perimeter region extending in both the X and Y directions. Accordingly, the total perimeter region in contact with at least a portion of the III-N heterojunction structure, e.g., the buffer layer 104 including the 2DEG channel 151, can be increased in the present examples. In this way, the total contact resistance of the multi-column contact 100B can be reduced (lowered) due to the increased perimeter contact region, according to the teachings of this disclosure.

[0028] Furthermore, an increased perimeter contact area of ​​a multi-contact design, combined with the provision of a silicon layer during the formation of conductive columns, can advantageously allow an annealing process to be carried out at lower temperatures while still achieving a desired contact resistance. Additionally, lower temperatures used in annealing are expected to reduce the risk of p-GaN deactivation in some examples, as further explained below.

[0029] Fig. 1B-2 represents an exemplary variation of the multi-column contact 100B, showing a residual silicon layer 157B representing an unconsumed portion of a silicon layer. As shown, the residual silicon layer 157B lies beneath the metal silicide 157A and may have a thickness less than the initial thickness of the silicon layer, as previously noted.

[0030] Fig. 1B-3 represents an exemplary variation of the multi-column contact 100B, showing a residual refractory metal layer 157C, representing an unconsumed portion of a refractory metal layer. As shown, the residual refractory metal layer 157C extends over or above the metal silicide 157A and may have a thickness less than the initial thickness of the refractory metal layer, as previously noted.

[0031] Although the semiconductor device is 100A Fig. As shown in Figure 1A with conductive columns 164A and 164B having the same cross-sectional areas, shapes, and / or being organized in identical or similar array configurations, etc., such features are not limitations. Additional and / or alternative examples may therefore include a multi-column contact design, where the conductive columns for a source contact and / or a drain contact may have different cross-sectional areas, shapes, and spatial configurations depending on the implementation. Furthermore, a multi-column source contact design of a GaN device may not be identical to a multi-column drain contact design of the GaN device in some examples.In general, conductive columns of a multi-column source / drain contact design can be manufactured in a variety of shapes with different cross-sectional areas and / or configurations in an adaptable manner, as long as applicable design rules regarding the critical dimension (CD) are not violated and process corners are not affected.

[0032] Fig. 2A to 2H-2 represent layouts of various multi-column contact designs that can be used to fabricate source / drain contacts (also referred to as source / drain electrodes) of a semiconductor device, according to some examples. In some implementations, conductive columns can be arranged as regular array configurations, such as rectangular or square arrays, e.g., Design 200A and Design 200C, which are described in Fig. 2A and 2C are shown. In some implementations, a multi-column contact design may include staggered columns of conductive columns, e.g., design 200B, which is shown in Fig. 2B is shown, where each column can contain multiple conductive columns. In some arrangements, a multi-column contact design can include a "continuous column" design 200D, which is shown in Fig. 2D is shown, where there is no segmentation of a conductive column along a planar axis (e.g., the X-axis) of the layout, resulting in multiple elongated conductive cuboids aligned along the Y-axis. Similarly, a multi-column contact design can include a Design 200F, where there is no segmentation of a conductive column along the Y-axis of the layout, resulting in a "continuous row" Design 200F, which is shown in Fig. Figure 2F shows a design that can include several elongated conductive cuboids aligned along the X-axis. A combinational multi-column contact design 200E, including continuous conductive columns and segmented conductive columns, can be provided in some arrangements, as shown in Figure 2F. Fig. 2E shown. A checkerboard-like multi-column contact design 200G can be provided in some arrangements, as shown in Fig. 2G shown. Fig. 2H-1 represents another staggered column design 200H-1, wherein two columns of conductive columns can be designed such that the staggered conductive columns are in contact with each other.

[0033] Although Fig. 2A to 2H-1, which represent an intended structuring of multiple conductive columns of a contact design in a layout and a corresponding mask set, may show that actual shapes of a pattern in a GaN device may differ slightly from those shown in Fig. The layout patterns shown in 2A to 2H-1 may differ due to inherent morphological differences caused by processing conditions. For example, openings with a square shape may be formed more like circular openings. Similarly, patterns with sharp corners may be formed as features with rounded corners. Furthermore, if a staggered column design is intended (e.g., design 200H-1, which is shown in Fig. 2H-1 is shown), the corresponding feature in a final device structure has a serpentine shape 200H-2, as shown in Fig. 2H-2 is shown. Depending on how closely the individual conductive columns are placed in the staggered layout of design 200H-1, the corresponding serpentine shape 200H-2 can have a varying width, e.g., parallel to the X-axis. Accordingly, the scope of protection of the examples presented here is intended to include all such process-related morphological variations with reference to a multi-column contact design of the present disclosure.

[0034] With dedication to Fig. Figures 3A to 3I-3 are cross-sectional views of a semiconductor device including a GaN device with multi-column contacts at various stages of a process flow according to an example of the present disclosure. Fig. 3A represents an intermediate stage of the semiconductor device 300, which in some arrangements is formed on a part of a semiconductor substrate 302, analogous to the semiconductor substrate 102 made of Fig. 1B. Depending on the implementation, the semiconductor substrate 302 can be provided as a silicon wafer, a silicon-on-sapphire wafer, or a silicon carbide wafer, and / or as a semiconductor substrate including cores configured to match the coefficient of thermal expansion (CTE), and / or the like. A buffer layer 304 analogous to the buffer layer 104 from Fig. 1B is formed on substrate 302 and may comprise one or more layers of III-N semiconductor material. In some examples where substrate 302 is implemented as a silicon wafer or a sapphire wafer, the buffer layer 304 may include a nucleation layer with a stoichiometry that incorporates aluminum to match a lattice constant of substrate 302. In some examples, the buffer layer 304 may further include layers / sublayers of aluminum gallium nitride (AlGaN) with decreasing aluminum content, including an unintentionally doped (UIN) GaN sublayer in some arrangements. For the purposes of the present examples, the various layers / sublayers of a buffer layer, e.g., buffer layer 304, are not specifically shown in the figures of this disclosure.

[0035] Depending on the implementation, the buffer layer 304 can have a thickness ranging from approximately 1 micrometer (µm) to several micrometers, e.g., 3.5 µm to 7.0 µm, which can be formed by a suitable epitaxy process, such as a metal-organic vapor phase epitaxy (MOVPE) process (also known as organometallic vapor phase epitaxy (OMVPE) or metal-organic chemical vapor deposition (MOCVD)), whereby several sequential steps can be performed to form the various constituent layers and / or sublayers. In some arrangements, an exemplary buffer layer 304 can therefore consist of a stack of several layers / sublayers of suitable materials and compositions (e.g., GaN, AlGaN, etc.).) as previously noted, whereby the layers / sublayers can have variable thicknesses depending on the technology and device application. In some arrangements, the buffer layer may include 304 AlGaN-based transition layers, epitaxial layers with strain-layer superlattice (SLS) structures, and the like.

[0036] The buffer layer 304 can be formed over a region of the substrate 302, whereby different regions, such as a source region 305A, a gate region 305B, a drain region 305D, and a drain access region 305C between the gate region 305B and the drain region 305D, can be provided with reference to a GaN device 301. The source region 305A can be considered to include a source access region (not specifically shown in the figures) that connects to a region between a multi-column source electrode or contact (e.g., source electrode 322A, as shown in Fig. 3G) and can refer to the gate region 305B, similar to the drain access region 305C. A channel layer can be provided as part of the buffer layer 304 - e.g., an upper part of the buffer layer 304 near a barrier layer 310. Although a channel layer may primarily contain GaN material, some implementations may include optional trace amounts of other Group III elements, such as aluminum or indium.

[0037] A barrier layer 310, comprising a III-N semiconductor material, is formed over the buffer layer 304 in a suitable epitaxial process. In an exemplary arrangement, the barrier layer 310 can have a thickness ranging from about 1 nanometer (nm) to about 60 nm and can contain aluminum and nitrogen. In some versions of this example, the barrier layer 310 can contain gallium at a lower atomic percentage than aluminum. In some versions, the barrier layer 310 can also contain indium. In some examples, the barrier layer 310 includes an AlGaN layer.

[0038] The barrier layer 310 above the buffer layer 304 is part of a heterojunction structure 306 to effect a 2DEG (e.g., 2DEG 308, which is in Fig. (3B-3H is shown) near an interface between the barrier layer 310 and the buffer layer 304. In some examples, the stoichiometry and thickness of the barrier layer 310 can be adjusted to provide a suitable density of free charge carriers (e.g., 3 × 10 12 cm -2 up to 2×10 13 cm -2 ) of the 2DEG must be configured to enable device operation.

[0039] For the purpose of achieving EMODE functionality, a p-doped III-N layer 314, comprising, for example, one or more layers of a III-N material, is structured above the barrier layer 310 in the gate region 305B, as shown in Fig. Figure 3A shows that in some examples, the p-doped III-N layer 314 may also be referred to as a p-III-N layer or a p-GaN layer. The formation of the p-GaN layer 314 causes the 2DEG to be reduced—e.g., in some cases, it is absent. In versions of this example, the p-doped III-N layer 314 may include a GaN layer doped with magnesium (Mg) or other p-type dopants. In some examples, the p-doped GaN layer 314 may have a p-doper concentration of about 1 × 10⁻⁶ 17 atoms / cm² 3 up to 1×10 21 atoms / cm² 3 They include and can have a thickness of approximately 10 nm to 200 nm. Although the in Fig. The present disclosure is not limited to the semiconductor device 300 shown in Figures 3A to 3I-3, which includes an EMODE GaN transistor. For example, the multi-column contacts (e.g., the multi-column contacts shown in Figures 3A to 3I-3) can be used in other devices. Fig. 1B-1 and 1B-3 are shown) are used for DMODE-GaN transistors.

[0040] In some additional and / or alternative arrangements, additional layers, such as an AlGaN cap layer of about 4 nm to 10 nm (e.g. without p-doping) and / or an LPCVD (Low-Pressure Chemical Vapor Deposition) silicon nitride (SiN) cap layer of about 10 nm to 20 nm, which are not specifically shown in the figures, can be provided over the p-GaN layer 314.

[0041] As illustrated, Fig. 3A represents a stage following the structuring of the p-GaN layer 314 using a mask and a suitable photolithography and etching process to form part of a gate stack 312, which in some implementations may include optional cap layers (e.g., AlGaN / SiN layers) in addition to a gate electrode or contact 322C formed over the structured p-GaN layer 314 (and the additional cap layers, if present). As a result of structuring the p-GaN layer 314 (e.g., removing portions of the p-GaN layer 314 outside the gate region 305B), the 2DEG 308 can be established in the channel layer outside the gate region 305B.In some versions of the examples presented, the source region 305A (where a multi-column source electrode or contact is to be formed) and the drain region 305D (where a multi-column drain electrode or contact is to be formed) can be arranged asymmetrically relative to the gate region 305B, although this is not a requirement. For example, there can be a greater lateral distance between the gate region 305B and the drain region 305D than the lateral distance between the gate region 305B and the source region 305A by means of an access region, e.g., the drain access region 305C, which is arranged between the gate region 305B and the drain region 305D.In some additional and / or alternative arrangements, a source access area can also be provided between source area 305A and gate area 305B in a similar manner as previously noted, while still maintaining a source / drain area asymmetry with respect to gate area 305B.

[0042] Although this in Fig. Since 3A is not specifically shown, a suitable device isolation step can be implemented to achieve isolation with respect to the GaN device 301. Depending on the implementation, an isolation step may involve mesa etching, implantation, etc., to define a region where the 2DEG 308 outside the active region is absent, removed, or otherwise interrupted. In some examples, argon implantation at 120 keV with a dose of approximately 5 × 10 14 atoms / cm² 2to be implemented to achieve device isolation, although other implantation species, such as silicon, fluorine, nitrogen, etc., may be used to achieve device isolation in additional and / or alternative examples.

[0043] The in Fig. The manufacturing stage shown in Figure 3A further illustrates a stage after the formation of a gate stack, e.g., the gate stack 312, including the gate electrode 322C. In some arrangements, the gate stack 312 can be formed before the formation of source / drain contacts, e.g., in a gate-first flow, as in Fig. 3A-3H, although this is not a requirement. Furthermore, the gate stack 312 can be formed after the deposition of one or more dielectric layers, which in some implementations can function as surface passivation layers. For example, a dielectric layer 316 comprising a SiN layer with a thickness of about 10 nm to 100 nm can be provided as a surface passivation layer. In one implementation example, the dielectric layer 316, which in some examples can be referred to as a first dielectric layer, can be formed by a high-temperature LPCVD process, e.g., at temperatures in the range of about 700 °C to about 850 °C, using suitable precursors such as dichlorosilane (DCS) and ammonia (NH3). Although the dielectric layer 316 in Fig. While 3A is illustrated as a single layer, this is not a necessary condition. Accordingly, the dielectric layer 316 can comprise multiple SiN layers, which in some additional and / or alternative examples may function as a composite passivation layer. In some arrangements, the first dielectric layer 316 can comprise different materials, e.g., silicon dioxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), etc., and can be formed using other techniques, such as ALD.

[0044] An exemplary gate-first flow, as illustrated here, involves forming a gate contact opening (in Fig. 3A not specifically shown) over the p-GaN layer 314 (and any cap layers, if present) using a gate-contact photolithography and etching process. Subsequently, the gate electrode 322C can be placed in the gate-contact opening from a suitable conductive layer (in Fig. (3A not specifically shown). In some versions, the conductive layer may comprise a metal layer – formed, for example, by sputtering. After deposition of the conductive layer, the gate electrode 322C is patterned from the conductive layer based on a suitable gate lithography and etching process. Depending on the implementation, the conductive layer from which the gate electrode 322C is formed may comprise one or more metals, such as titanium, nickel, tungsten, platinum, iridium, aluminum, gold, etc., and / or may include other electrically conductive materials, such as carbon nanotubes or graphene, as well as metallic nitrides, such as titanium nitride (TiN), tantalum nitride (TaN), and the like.

[0045] Fig. Step 3B represents a stage in which a dielectric layer 334 is formed above the gate stack 312 and the first dielectric layer 316. In some arrangements, the dielectric layer 334, also referred to as a second dielectric layer, may comprise a SiN layer deposited using a PECVD process, which can be performed at temperatures of approximately 350 °C to 400 °C, lower than the temperatures of LPCVD used to form the first dielectric layer 316. Depending on the implementation, the second dielectric layer 334 can have a thickness ranging from several tens of nanometers to several hundred nanometers. Due to the lower temperatures used in PECVD, the dielectric layer 334 can contain hydrogen in a higher proportion (e.g., due to less outgassing) than the first dielectric layer 316.Although higher concentrations of hydrogen may be present in the second dielectric layer 334, the risk of hydrogen diffusion into the p-GaN layer 314 (e.g., through the first dielectric layer 316 near the gate region 305B) during subsequent thermal process steps, e.g., a silicide formation annealing process, is expected to be mitigated in the examples presented here due to the lower temperatures used in the silicide formation annealing process during contact metallization.

[0046] Fig. Stage 3C represents a stage in which pluralityes of contact openings 318A, 318B (also referred to as recesses or simply openings) are formed in the source region 305A and the drain region 305D, respectively, to enable the formation of multi-column source and drain contacts in subsequent stages. Depending on the implementation, individual openings of the pluralityes of openings 318A, 318B can have suitable form factors and dimensions (e.g., including circular shapes, ovoid shapes, oblong-circular shapes, rectangular shapes, square shapes, diamond shapes, etc.). In some implementations, the pluralityes of openings 318A, 318B can be organized in the same or different spatial arrangements (such as in Fig. 2A-2G illustrated). Furthermore, the individual openings of the plurals of openings 318A and 318B may have the same or different shapes or sizes in some examples, as noted previously.

[0047] The openings 318A / 318B can be formed by etching or removing material from the dielectric layers 334, 316, and part of the heterojunction structure 306, for example, using a contact opening mask and a pattern etching process, which in some arrangements may include one or more etching stages, including wet and / or dry etching processes. Depending on the implementation, contact etching processes may include, among others, inductively coupled plasma (ICP) etching, deep reactive ion etching (DRIE) etching, high aspect ratio etching (HARE) etching, etc., using appropriate chemicals and process recipes. Furthermore, contact etching processes with different etch rates, chemicals, etc. can be implemented for different layers / sublayers of the dielectric layers 316, 334 and / or the heterojunction structure 306.

[0048] In some implementations, individual openings of the plurality of openings 318A, 318B can be formed such that the openings extend into the buffer layer 304 to a suitable depth to allow contact with the 2DEG 308 of the GaN device 301. In some examples, the openings 318A, 318B can extend into the buffer layer 304 to a depth 317 in the range of about 5 nm to about 30 nm, with each individual opening having an area corresponding to a mask pattern region of about 0.3 µm by 0.3 µm.

[0049] Fig. Step 3D represents a stage in which a Si layer 319 is formed over the GaN device 301, with the Si layer 319 forming a lining 371 along the inner sidewalls of the openings 318A, 318B. In some arrangements, the Si layer 319 can have a thickness in the range of approximately 5 nm to approximately 20 nm. Depending on the implementation, the Si layer 319 can be formed using LPCVD or PECVD processes. In some arrangements, precursors such as silane, dichlorosilane (DCS), trichlorosilane (TCS), etc., can be used for deposition at temperatures in the range of approximately 450 °C to approximately 700 °C.

[0050] In one implementation example, the Si layer 319 can be formed using a low-temperature PECVD process with silane (SiH4) as a precursor, provided at approximately 12 to 16 standard cubic centimeters per minute (sccm) (depending, for example, on the reactor chamber size and deposition rate). Furthermore, an exemplary PECVD Si process can be implemented using pressures in the range of approximately 0.3 Torr to approximately 5.0 Torr, temperatures in the range of approximately 350 °C to approximately 600 °C, and an RF power of approximately 50 to 300 watts (W).

[0051] Fig. Step 3E represents a stage in which a refractory metal layer 321 is formed over the Si layer 319 as part of a Si metal stack for fabricating multi-column contacts according to the present examples. In some arrangements, the refractory metal layer 321 may comprise a refractory metal of at least one of titanium (Ti), nickel (Ni), tungsten (W), tantalum (Ta), niobium (Nb), cobalt (Co), platinum (Pt), molybdenum (Mo), rhenium (Re), vanadium (V), zirconium (Zr), hafnium (Hf), ruthenium (Ru), and iridium (Ir), and / or in combination with a nitride of the refractory metal (e.g., Ti / TiN). In one implementation example, the refractory metal layer 321 can be formed using a sputtering process, a reactive sputtering process or an ALD process and can have a thickness in the range of about 10 nm to about 40 nm or more.

[0052] Fig. Step 3F represents a stage in which a conductive layer 323 is formed over the refractory metal layer 321 using a suitable process, such as sputtering, reactive sputtering, or ALD, to fill the openings 318A and 318B lined with the Si lining 371 and the refractory metal layer 321, respectively. In some arrangements, the conductive layer 323 may comprise a conductive bulk component of a contact column and may include a suitable metal, such as aluminum, an aluminum-Luffer alloy (e.g., including 0.5% Cu), etc. Depending on the implementation, the conductive layer 323 may have a thickness of approximately 30 nm to 200 nm or more. Furthermore, in some additional and / or alternative arrangements, a metallic barrier layer comprising a refractory metal composition can be placed over the conductive layer 323 as part of a Si metal stack, e.g.of the stack 325. In some versions of this example, the Si metal stack 325 may comprise a Si layer, a Ti layer, and a conductive Al layer.

[0053] As previously noted, annealing can be performed at lower temperatures while still achieving a desirable contact resistance—e.g., at temperatures suitable for forming a metal silicide, at least in part due to the increased perimeter area of ​​the multiple conductive columns of the S / D contacts 322A / 322B. Depending on the implementation, an annealing process (e.g., a thermal silicide formation process) can be carried out in different stages to form a metal silicide using at least a portion of the refractory metal layer 321 and at least a portion of the Si layer 319 of the Si metal stack 325. In some arrangements, the annealing process to form a metal silicide can be performed prior to the deposition of the conductive layer 323 in the Fig. The step shown in 3F is carried out. Afterwards, the conductive layer 323 can be deposited over the metal silicide. In some arrangements, the tempering process to form a metal silicide can be carried out after the deposition of the conductive layer 323 in the Fig. The 3F stage shown will be carried out.

[0054] Fig. Figure 3G exemplifies a stage of the semiconductor device 300 following the formation of a metal silicide 333 based on the consumption of the entire silicon layer 319 and refractory metal layer 321 in an annealing process. The metal silicide 333 can be formed regardless of whether the annealing process is performed before or after the deposition of the conductive layer 323. In one implementation, the refractory metal layer 321 is a titanium layer and the conductive layer 323 is an aluminum layer. In one implementation, an annealing process can involve rapid thermal annealing (RTA) or furnace annealing at temperatures in the range of approximately 500 °C to less than 700 °C for approximately 30 seconds to 5 minutes. In some examples, the metal silicide 333 can have a thickness that is approximately equal to the total combined thickness of the Si layer 319 and the Ti layer 321.In additional and / or alternative examples, there may be only partial consumption of the Si layer 319 and / or Ti layer 321, as previously described. Accordingly, in some examples, there may be a remaining portion of an unconsumed Si layer located beneath the metal silicide 333, the thickness of which may be less than the initial thickness of the Si layer 319 as deposited. Likewise, there may be a remaining portion of an unconsumed Ti layer extending over or above the metal silicide 333, the thickness of which may be less than the initial thickness of the Ti layer 321 as deposited.

[0055] Fig. Step 3H represents a stage in which contact metal etching based on suitable photolithography is performed to define contact pads 327-1, 327-2 over the filled openings 318A, 318B. In this way, multi-column contacts 322A, 322B, functioning as source and drain electrodes respectively, can be formed in the source and drain regions 305A, 305D according to the present examples. As shown in Fig. As illustrated in Figure 3H, the multi-column contacts 322A, 322B are analogous to the multi-column contact 100B with two conductive columns 150A, 150B, which are in Fig. 1B-1 are shown. Similar to contact 159 from Fig. In 1B-1, the contact pads 327-1, 327-2 can comprise the Si-metal stack 325, which can have a thickness depending on the thicknesses of the constituent layers, e.g., the conductive layer 323 (as well as a metallic barrier layer, if provided) and the underlying metal silicide 333. In additional or alternative arrangements, the multi-column contacts 322A, 322B can have configurations analogous to the multi-column contact 100B, which is described in Fig. 1B-2 and 1B-3 are shown, wherein the silicon layer 319 and the refractory metal layer 321 are only partially consumed in the formation of the metal silicide 333.

[0056] Fig. 3I-1 represents a fully formed semiconductor device 300 including the GaN device 301, wherein a source terminal 342A, a gate terminal (in Fig. 3I not shown) and a drain terminal 342B are formed by an insulator 350, which includes, for example, an interlevel dielectric (ILD: Interlevel Dielectric) and / or pre-metal dielectric (PMD: Pre-Metal Dielectric) material, to establish an electrical contact with the source electrode 322A, drain electrode 322B or gate electrode 322C.

[0057] Fig. 3I-2 and 3I-3 represent a more fully formed semiconductor device 300, including additional and / or alternative variations of multi-column contacts according to some examples. As shown, the examples are from Fig. 3I-2 and 3I-3 are essentially identical to the one in Fig. The example shown in 3I-1 applies accordingly. Fig. The process flow stages described in 3I-1 also refer to the examples from Fig. 3I-2 and 3I-3 shall be applied, with the exception of the following remarks.

[0058] In the example from Fig. 3I-2 includes the semiconductor device 300 multi-column contacts 322A' and 322B', which are formed in respective contact openings 318A, 318B that do not extend through the barrier layer 310. Accordingly, an exemplary etching process (e.g., similar to the process step from Fig. 3C) within the barrier layer 310 to form the contact openings 318A, 318B. The amount of barrier layer 310 remaining in the contact openings 318A, 318B can vary depending on the implementation. After the formation of the contact openings 318A, 318B, which extend partially into the barrier layer 310, subsequent process steps of contact metallization and tempering can be carried out similarly to the steps described in Fig. 3D-3H. For the purposes of this disclosure, the multi-column contacts 322A', 322B', which extend partially into the barrier layer 310, can be referred to as multi-column contacts with partial recessing.

[0059] In the example from Fig. 3I-3 includes the semiconductor device 300 multi-column contacts 322A'' and 322B'', which are formed in respective contact openings 318A, 318B, which terminate on an upper surface of the barrier layer 310 in an etching process (e.g. in a process step similar to Fig. 3C). After forming the contact openings 318A, 318B, which do not extend into the barrier layer 310, subsequent process steps of contact metallization and tempering can be carried out similarly to the steps described in Fig. 3D-3H. Accordingly, the multi-column contacts 322A'' and 322B'' do not extend into the barrier layer 310. For the purposes of this disclosure, the multi-column contacts 322A'', 322B'', which do not extend into the barrier layer 310, can be referred to as multi-column contacts without a recess.

[0060] Although the multi-column contacts 322A' / 322B' and 322A'' / 322B'' the 2DEG 308 in the examples from Fig. Since 3I-2 and 3I-3 do not physically contact each other, the formation of an electrically resistive contact can be enabled by a reaction between the barrier layer 310 and the Si metal stack of the conductive columns during a thermal silicide formation process. For example, a reaction between the barrier layer 310 and the Si metal stack can be enabled by mechanisms such as nitrogen vacancy formation, barrier tunneling, metal spiking, etc.

[0061] Fig. Figure 4 shows a cross-sectional view of a semiconductor device 400 including a GaN device 401, wherein in some examples of the present disclosure a field-plate structure can be associated with a multi-column contact of the GaN device 401. As illustrated, the GaN device 401 is essentially similar to the GaN device 301, except for a first field plate (FP1) 436, a second FP (FP2) 440, and a dielectric layer 338, which is at least partially arranged between them, wherein the multi-column source and drain contact 322A, 322B of the GaN device 401 can be fabricated using a gate-first flux similar to the flux described above. Accordingly, the description of the gate-first flux previously given with reference to Fig. As set forth in 3A-3H, this is also applicable with regard to the formation of the semiconductor device 400, unless otherwise noted here. Depending on the implementation, the formation of the semiconductor device 400 may involve a self-aligned source-contact process or a non-self-aligned source-contact process, which in some examples may be used to form multiple conductive columns of a source contact. In some arrangements, FP1 436 may be formed from an Al-based FP metal layer formed over the dielectric layer 334 using a deposition process, e.g., a physical vapor deposition (PVD) process, wherein the FP metal layer forms an adhesive layer (in Fig. 4 (not explicitly shown) may contain TiN, titanium-tungsten (TiW), etc., which contacts the dielectric layer 334. In some arrangements, the FP1 436 may have a thickness of approximately 30 nm to 500 nm.

[0062] In an exemplary self-aligned source-contact process, the FP1 436 can be provided as a hard mask for contact opening formation. Accordingly, in some arrangements, the FP1 436 can extend completely to form a conductive column of the multi-column source electrode 322A closest to and contacting the gate region 305B, as in, for example, Fig. Figure 4 illustrates this. In a non-self-aligned source contact process, the FP1 436 may only partially extend over part of the source area 305A, thus lacking direct contact with the multi-column source contact 322A.

[0063] In some examples, a dielectric layer 338 is formed over at least part of the FP1 436, as in Fig. Figure 4 illustrates this. As shown, the dielectric layer 338, which in some examples may be referred to as a third dielectric layer, can be structured to extend over the drain access region 305C while partially overlying the FP1 436 in the gate region 305B. Similar to the second dielectric layer 334, the third dielectric layer 338 can be formed using PECVD and may include SiN or a similar material, including hydrogen. Although the hydrogen in the third dielectric layer 338 could be susceptible to diffusion at high temperatures, this risk can be advantageously mitigated in the disclosed examples due to low-temperature contact annealing, which is made possible by the multi-column contact design used in the fabrication of the source and drain contacts 322A, 322B, as previously noted.

[0064] A contact metallization process, including silicon metal stack formation and annealing, can be carried out similarly to the steps described in Fig. 3C-3H are set out, with the exception that in the example from Fig. 4. A second FP, e.g., FP2 440, coupled to the multi-column source contact 322A, can be formed during contact structuring. In one arrangement, the FP2 440 can extend at least partially over the third dielectric layer 338, as shown in Fig. 4 shown. Similar to the example from Fig. 3I Each conductive column of the multi-column source / drain contacts 322A / 322B contains the metal silicide 333, which is formed in a suitable annealing process as previously described. Accordingly, the conductive columns of the multi-column source / drain contacts 322A / 322B each contain metal silicide sidewall portions that contact the buffer layer 304, including the 2DEG 308. Furthermore, the semiconductor device 400 is made of Fig. 4 including the GaN device 401 with the source and drain connections 342A, 342B, similar to the one in Fig. The arrangement shown in Figure 3I. Additional details regarding a self-aligned contact process flow, which can be combined with some examples of a multi-column contact design as set forth herein, can be found in application No. 18 / 189,870, filed on March 24, 2023, which is hereby incorporated by reference in its entirety for all purposes.

[0065] Although the examples in this disclosure specifically describe Al-based Si-metal stacks for forming multi-column contacts, other lining materials and / or metals can be used to form conductive columns in additional and / or alternative implementations. Furthermore, although the examples are presented in detail in the context of forming multi-column contacts after the formation of a gate stack (e.g., in a gate-first process flow), the teachings of this disclosure are not limited thereto. Accordingly, multi-column contacts that function as source / drain contacts in a GaN device, e.g., the source / drain contacts 322A / 322B, can also be fabricated in a gate-last process flow according to some additional and / or alternative examples, wherein the multi-column contacts are formed before a gate stack including a gate electrode is formed.

[0066] In some implementations, hydrogen-containing dielectric layers (surrounding or overlying the gate stack, including a p-GaN layer) can be formed in a gate-last flow after the source and drain electrodes have already been formed. Accordingly, the risk of hydrogen diffusion and simultaneous dopant deactivation due to high-temperature contact annealing in such a flow can be minimal, reducing the need for a multi-column contact design to address this issue. Nevertheless, a multi-column contact design coupled with a silicon lining process in a gate-last flow can be incorporated according to some additional and / or alternative examples, still realizing the benefits of lower contact resistance.Due to the colonnade-like arrangement of multiple conductive columns formed in the heterojunction structure of a device, the conductive columns of a drain contact at the end facing the gate stack are also functional for shielding the inner conductive columns from charge trapping events near the drain contact. Accordingly, improved device reliability (e.g., BR) can be achieved. DSON -stability) under high voltage / high current conditions can also be obtained in "gate-last" GaN devices. Further details regarding an exemplary gate-last process flow, which can be combined with some examples of a multi-column contact design as set forth herein, can be found in application no. 18 / 788,650, filed on July 30, 2024, which is hereby incorporated by reference in its entirety for all purposes.

[0067] Furthermore, some multi-column contact designs of the present disclosure can enable the formation of drain contacts that increase an effective gate-to-drain length (Lgd) in a GaN device without increasing the actual lateral spacing between a gate and a drain in the device. For example, a staggered column design, such as design 200H-1 (in Fig. (2H-1 shown) an effective Lgd due to alternating columns spaced further away from the gate. Devices with longer Lgd may be able to withstand higher voltages and can therefore advantageously support higher voltage applications with greater reliability.

[0068] In further variations, an exemplary multi-column contact design of the present disclosure can be implemented in the fabrication of GaN resistors using similar process steps as previously described. In such implementations, the formation of a gate stack (e.g., including a p-GaN layer for an EMODE-GaN transistor) above the barrier layer 310 can be omitted. Fig. Figure 6 represents a GaN transistor 600 including multi-column contacts 322A, 322B according to an example from the present disclosure. As illustrated, a continuous 2DEG 308 is formed in the heterojunction structure 306 due to the absence of a p-GaN layer above the barrier layer 310. The multi-column contacts 322A, 322B, including the Si-metal stacks, are formed similarly to the structures described in the previously presented Fig. Figures 1B-1 to 1B-3 are shown. In some examples, the multi-column contacts 322A, 322B can be laterally spaced by a distance D1, depending on a desired resistance value and / or the dimensioning of the GaN resistor 600. The 2DEG extending between the multi-column contacts 322A, 322B is therefore functional as a resistor body according to the examples shown. Furthermore, the multi-column contacts 322A, 322B are functional as resistor heads, which are coupled to the respective terminals 342A, 342B of the GaN resistor 600.

[0069] Fig. 5A and Fig. 5B are flowcharts of processes for manufacturing a semiconductor device including multi-column contacts according to some examples in the present disclosure. Process 500A, which is described in Fig. As shown in 5A, the process can begin with the formation of a III-N heterojunction structure over a semiconductor substrate, where the III-N heterojunction structure may include a III-N buffer layer over the semiconductor substrate and a III-N barrier layer over the buffer layer. In block 504, a p-doped III-N layer is formed over the III-N barrier layer in the gate region to enable p-GaN functionality. In some examples, the steps outlined in blocks 502 and 504 may cover certain aspects of the process. Fig. 3A, as previously described. In block 506, a contact is formed in the source region and / or the drain region, the contact comprising several conductive columns coupled to at least part of the III-N heterojunction structure, which affects some aspects of Fig. 3C-3G, as previously described, may be affected.

[0070] Procedure 500B, which is in Fig. Figure 5B illustrates additional steps required to perform certain aspects relating to Block 506. Fig. 5A can be used. In Block 520, multiple openings can be formed in the source region and / or drain region of a GaN device. In some arrangements, the multiple openings can be formed before or after the formation of a gate stack of the GaN device. In some arrangements, the multiple openings extend to at least a portion of the III-N heterojunction structure, e.g., a III-N buffer layer, which is functional to support a conductive channel. Furthermore, the opening formation can involve a self-aligned contact process or a non-self-aligned contact process, as previously noted.

[0071] In Block 522, a silicon layer can be deposited in the multiple openings, for example, using a low-temperature deposition process such as PECVD, with the silicon layer forming a lining in the contact openings that are functional for contacting a channel of the GaN device (e.g., a 2-dimensional electron gas (2DEG) or a 2D hole gas (2DHG)). In some examples, these steps outlined for Block 522 may incorporate aspects from Fig. 3D effects are affected. In block 524, a refractory metal layer can be deposited over the silicon layer, which affects some aspects of Fig. 3E may affect. In some arrangements, the rate of refractory metal layer deposition can be controlled based on factors such as the number of apertures, aperture shape factor (e.g., depth and width of individual apertures), spatial configuration of the apertures, etc., to enable better process control. In Block 526, a conductive layer, comprising, for example, aluminum, can be formed over the refractory metal layer to create a Si metal stack. In some examples, the steps outlined in Block 526 may incorporate aspects of Fig. 3F concerns. In Block 525, a silicide formation annealing process can be carried out at low temperatures (e.g., in the range of about 500 °C to less than 700 °C) before or after the conductive layer is deposited. The Si-metal stack is then structured to form multi-column contacts in the source and / or drain region (Block 528). In some examples, the steps outlined in Block 528 may incorporate aspects from Fig. 3H concerns.

[0072] Although various examples of the present revelation have been described previously, they were presented only as examples and not as limitations. Numerous modifications to the revealed examples may be made according to the revelation here without altering the nature or scope of protection of the revelation. Accordingly, the meaning and scope of protection of the present revelation should not be limited by any of the previously described examples. Instead, the scope of protection of the revelation should be defined according to the claims appended here and their equivalents.

[0073] For example, unless otherwise stated and / or specified, in this disclosure and the following claims, one or more of any of the layers described herein can be formed in any number of suitable ways, such as by spin-on techniques, sputtering techniques (e.g., magnetron and / or ion beam sputtering), (thermal) growth techniques, or deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), PECVD, or atomic layer deposition (ALD), etc. As another example, silicon nitride can be silicon-rich silicon nitride or oxygen-rich silicon nitride. Silicon nitride may contain some oxygen, but not so much that the dielectric constant of the materials is substantially different from that of high-purity silicon nitride.

[0074] Furthermore, in at least some additional or alternative implementations, the functions / actions described in the blocks may occur out of order as shown in the flowcharts. For example, two blocks shown sequentially may, depending on the functionality / actions involved, actually be executed essentially simultaneously, or the blocks may sometimes be executed in reverse order. Additionally, the functionality of a given block in the flowcharts and / or block diagrams may be separated into multiple blocks, and / or the functionality of two or more blocks in the flowcharts and / or block diagrams may be at least partially integrated. Finally, some blocks in the flowcharts may be optionally omitted.Although some of the diagrams include arrows on communication paths to indicate a primary direction of communication, it is also understood that communication can occur in the opposite direction relative to the arrows shown. Finally, other blocks can be added / inserted between the blocks that are illustrated.

[0075] The sequence or order of the actions, steps, functions, components or blocks illustrated in any of the flowcharts and / or block diagrams depicted in the drawings of figures of the present disclosure may be modified, altered, replaced, adapted or otherwise rearranged within a particular flowchart or block diagram, including the removal or omission of a particular action, step, function, component or block.Furthermore, the actions, steps, functions, components, or blocks illustrated in one flowchart may be mixed, rearranged, or otherwise combined with the actions, steps, functions, components, or blocks illustrated in another flowchart to produce additional variations, modifications, and configurations relating to one or more processes for the purposes of implementing the teachings of this revelation. Likewise, although various examples have been presented here, not all features of any given example are necessarily limited to or required for it.

[0076] At least some parts of the preceding description may include a degree of directional terminology, such as "upper," "lower," "above," "below," "left," "right," "front," "back," "vertical," "horizontal," etc., which may be used with reference to the orientation of some of the figures or illustrative elements thereof being described. Because components of some examples can be positioned in a number of different orientations, the directional terminology is used for illustrative purposes and is in no way restrictive. Likewise, references to features designated as "first," "second," etc., do not indicate any particular order, importance, or the like, and such references may be interchanged depending on the context, implementation, etc. Furthermore, expressions such as "above," "below," "below," etc., do not meanThe spatial orientation of two components does not necessarily imply that one component is directly above or below the other. Furthermore, the features and / or components of the examples described here can be combined unless specifically stated otherwise.

[0077] Although various implementations have been shown and described in detail, the claims are not limited to any particular implementation or example. Nothing in the above detailed description should be interpreted as implying that any particular component, element, step, action, or function is essential and therefore must be included in the scope of protection of the claims. When phrases such as "at least one of A and B," or phrases of similar meaning, are mentioned or described, such a phrase should be understood to mean "only A, only B, or both A and B." A singular reference to an element should not mean "one and only one," unless explicitly stated, but rather "one or more."Similarly, formulations such as "a plurality" or "several" can mean "one or more" or "at least one" depending on the context. All structural and functional equivalents to the elements of the implementations described above are expressly included herein by reference and are to be encompassed by the claims appended below. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] WO 18 / 189,870

[0064] WO 18 / 788,650

[0066]

Claims

[1] Semiconductor device comprising the following: a semiconductor substrate comprising a source region, a gate region, a drain region, and a drain access region between the gate region and the drain region; a III-N heterojunction structure above the semiconductor substrate, wherein the III-N heterojunction structure includes a buffer layer above the semiconductor substrate and a barrier layer above the buffer layer; and a contact in the source region and / or the drain region, wherein the contact includes multiple conductive columns coupled to the III-N heterotransition structure. [2] Semiconductor device according to claim 1, wherein the multiple conductive columns extend to or into the buffer layer. [3] Semiconductor device according to claim 2, wherein the multiple conductive columns are coupled via a channel in the buffer layer. [4] Semiconductor device according to claim 1, further comprising: a p-doped III-N layer above the barrier layer in the gate region. [5] Semiconductor device according to claim 1, wherein the multiple conductive columns are organized in an (NxM) array. [6] Semiconductor device according to claim 1, wherein each conductive column of the contact has the same cross-sectional area. [7] Semiconductor device according to claim 1, wherein at least one conductive column of the contact has a different cross-sectional area than other conductive columns of the contact. [8] Semiconductor device according to claim 1, wherein each conductive column of the contact comprises the following: a metal silicide; and a conductive layer over the metal silicide. [9] Semiconductor device according to claim 8, wherein the metal silicide has a thickness in the range of about 5 nanometers (nm) to about 40 nm. [10] Semiconductor device according to claim 8, wherein the metal silicide comprises at least one of titanium, tungsten, tantalum, niobium, cobalt, platinum, molybdenum, rhenium, vanadium, zirconium, hafnium, ruthenium and iridium. [11] Semiconductor device according to claim 8, further comprising: a silicon layer, with the metal silicide located on the silicon layer. [12] Semiconductor device according to claim 11, wherein the silicon layer has a thickness of less than 5 nm. [13] Semiconductor device according to claim 8, further comprising: a refractory metal layer, wherein the refractory metal layer is located on the metal silicide. [14] Semiconductor device according to claim 13, wherein the refractory metal layer has a thickness of less than 10 nm. [15] Semiconductor device according to claim 8, wherein the conductive layer comprises aluminium. [16] Method comprising the following: Forming a III-N heterojunction structure over a semiconductor substrate, comprising a source region, a gate region, a drain region, and a drain access region between the gate region and the drain region, wherein the III-N heterojunction structure includes a buffer layer over the semiconductor substrate and a barrier layer over the buffer layer; and Forming a contact in the source region and / or the drain region, wherein the contact includes multiple conductive columns coupled to the III-N heterojunction structure. [17] The method of claim 16, further comprising: Extending the multiple conductive columns to or into the buffer layer. [18] The method of claim 16, further comprising: Formation of a p-doped III-N layer above the barrier layer in the gate region. [19] Method according to claim 16, wherein the contact is formed before a gate stack is formed in the gate area. [20] Method according to claim 16, wherein the contact is formed after a gate stack has been formed in the gate area. [21] Method according to claim 16, wherein forming the contact comprises: Forming several openings in at least one of the source region and the drain region, with individual openings of the several openings extending to or into the buffer layer; Deposition of a silicon layer in the multiple openings, wherein the silicon layer contacts the buffer layer; Deposition of a refractory metal layer over the silicon layer; and Deposition of a conductive layer over the refractory metal layer. [22] Method according to claim 21, wherein the silicon layer is formed by a plasma-enhanced chemical vapor deposition (PECVD) process at a temperature in the range of about 350 °C to about 600 °C. [23] Method according to claim 22, wherein the PECVD process uses a silane(SiH4) gas precursor supplied at about 12 to 16 standard cubic centimeters per minute (sccm), wherein the PECVD process has a pressure in the range of about 0.3 Torr to about 5.0 Torr and an RF power in the range of about 50 W to about 300 W. [24] Method according to claim 21, wherein the refractory metal layer comprises at least one of titanium, tungsten, tantalum, niobium, cobalt, platinum, molybdenum, rhenium, vanadium, zirconium, hafnium, ruthenium and iridium. [25] Method according to claim 21, wherein the conductive layer comprises aluminium. [26] The method of claim 21, further comprising: Formation of a metal silicide based on the silicon layer and the refractory metal layer. [27] Method according to claim 26, wherein the formation of the metal silicide comprises the following: Performing tempering at a temperature in the range of approximately 500 °C to less than 700 °C for a duration of approximately 30 seconds to 5 minutes. [28] Method according to claim 26, wherein the formation of the metal silicide takes place prior to the deposition of the conductive layer. [29] Method according to claim 26, wherein the formation of the metal silicide takes place after the deposition of the conductive layer.

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