Semiconductor Device and Method for Manufacturing a Semiconductor Device

Abstract

Semiconductor device (B1) comprising: a substrate (11) having an insulating layer (111), a carrier conductor (112) and a back surface metal layer (113), wherein the carrier conductor (112) has a front surface (1120) facing one side (z1) of a thickness direction (z); at least one semiconductor element (21) arranged on the front surface (1120); at least one control terminal (45) for controlling the at least one semiconductor element (21); a control terminal carrier (48) arranged between the substrate (11) and the at least one control terminal (45) in the thickness direction (z) to support the control terminal (45); and a sealing resin (50) with a front resin surface (51) facing one side (z1) of the thickness direction (z), wherein the sealing resin (50) covers at least a part of the support substrate (11),wherein the control connection (45) has an electrically conductive cylindrical holder (451) and a metal pin (452) inserted into the holder (451), wherein the control connection (45) projects in the direction of one side (z1) of the thickness direction (z) with respect to the front resin surface (51), the sealing resin (50) is formed with at least one first recess (511) which is recessed in the direction of an opposite side (z2) of the thickness direction (z) from the front resin surface (51), the at least one first recess (511) having a first recess inner surface (512) which has a first end edge (513) which is held in contact with the control connection carrier (48), and the control connection (45) is arranged in the at least one first recess (511) such that the control connection (45) is completely exposed by the sealing resin (50),wherein the semiconductor device (B1) further comprises: a first power terminal (14) and at least one second power terminal (15) arranged on one side (x1) of a first direction (x) relative to the support substrate (11), the first direction (x) being perpendicular to the thickness direction (z); and at least one third power terminal (16) arranged on an opposite side (x2) of the first direction (x) relative to the support substrate (11), wherein the first power terminal (14) and the at least one second power terminal (15) each have a section covered by the sealing resin (50) and another section exposed by the sealing resin (50), and the at least one third power terminal (16) has a section covered by the sealing resin (50) and another section exposed by the sealing resin (50).

Description

TECHNICAL AREA The present disclosure relates to a semiconductor device. STATE OF THE ART Semiconductor devices with power switching elements such as MOSFETs (metal-oxide-semiconductor field-effect transistors) or IGBTs (insulated-gate bipolar transistors) are conventionally known. These semiconductor devices are used in a wide variety of electronic equipment, including industrial equipment, household appliances, information terminals, and automotive equipment. A conventional semiconductor device (power module) is disclosed in Patent Document 1. The semiconductor device disclosed in Patent Document 1 comprises a semiconductor element and a support substrate (ceramic substrate). The semiconductor element is, for example, an IGBT made of silicon (Si). The support substrate carries the semiconductor element. The support substrate has an insulating base and a conductive layer provided on each side of the base. The base is, for example, made of a ceramic material.The conductive layers are made of, for example, Cu (copper). The semiconductor element is bonded to one of the conductive layers. Patent documents 2 and 3 also disclose semiconductor devices with holders and terminals covered by a sealing resin. STATE OF THE ART DOCUMENTS Patent documents Patent document 1: JP 2021-190 505 APatent document 2: WO 2022 / 080 063 A1Patent document 3: US 2015 / 0103498 A1 BRIEF SUMMARY OF THE INVENTION Problem to be solved by the invention In recent years, electronic equipment has been subject to increasing demands for energy efficiency, high performance, and miniaturization. To meet these demands, improved performance and miniaturization of the semiconductor modules used in electronic equipment are necessary. One objective of the present disclosure is to provide a semiconductor device that is improved compared to conventional ones. In particular, in view of the foregoing circumstances, one objective of the present disclosure is to provide a semiconductor device that is suitable for improving performance and miniaturization. The claimed subject matter is defined in the independent claims. Preferred embodiments are defined in the dependent claims. A semiconductor device provided according to the invention comprises: a substrate having an insulating layer, a carrier conductor, and a back-surface metal layer, wherein the carrier conductor has a front surface facing one side of a thickness direction; at least one semiconductor element arranged on the front surface; at least one control terminal for controlling the at least one semiconductor element; a control terminal carrier arranged between the substrate and the at least one control terminal in the thickness direction to support the control terminal; and a sealing resin having a front resin surface facing one side of the thickness direction, wherein the sealing resin covers at least a portion of the substrate, and wherein the control terminal has an electrically conductive cylindrical holder and a metal pin inserted into the holder.wherein the control terminal projects in the direction of one side of the thickness direction with respect to the front resin surface, the sealing resin is formed with at least one first recess which is recessed in the direction of an opposite side of the thickness direction from the front resin surface, the at least one first recess having a first recess inner surface which has a first end edge which is held in contact with the control terminal carrier, and the control terminal is arranged in the at least one first recess such that the control terminal is completely exposed by the sealing resin; the semiconductor device further comprises: a first power terminal and at least one second power terminal which are arranged on one side of a first direction relative to the support substrate,wherein the first direction is perpendicular to the thickness direction; and at least one third power connection located on a side opposite the first direction relative to the support substrate, wherein the first power connection and the at least one second power connection each have a section covered by the sealing resin and another section exposed by the sealing resin, and the at least one third power connection has a section covered by the sealing resin and another section exposed by the sealing resin. Advantages of the invention The configuration described above provides a semiconductor device that features a configuration which favors an improvement in performance and a reduction in size. Other features and advantages of the present disclosure will become clearer from the detailed description below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a perspective view of a semiconductor device according to a first example of a first aspect of the present disclosure. Fig. 2 is a perspective view showing relevant sections of the semiconductor device according to the first example of the present disclosure. Fig. 3 is a perspective view showing relevant sections of the semiconductor device according to the first example of the present disclosure. Fig. 4 is a top view of the semiconductor device according to the first example of the present disclosure. Fig. 5 is a top view showing relevant sections of the semiconductor device according to the first example of the present disclosure. Fig. 6 is a side view showing relevant sections of the semiconductor device according to the first example of the present disclosure. Fig. 7 is an enlarged top view showing relevant sections of the semiconductor device according to the first example of the present disclosure.Fig. 8 is a top view showing relevant sections of the semiconductor device according to the first example of the present disclosure. Fig. 9 is a top view showing relevant sections of the semiconductor device according to the first example of the present disclosure. Fig. 10 is a side view showing relevant sections of the semiconductor device according to the first example of the present disclosure. Fig. 11 is a bottom view showing relevant sections of the semiconductor device according to the first example of the present disclosure. Fig. 12 is a sectional view along line XII-XII shown in Fig. 5. Fig. 13 is a sectional view along line XIII-XIII shown in Fig. 5. Fig. 14 is an enlarged sectional view showing relevant sections of the semiconductor device according to the first example of the present disclosure.Figure 15 is an enlarged sectional view showing relevant sections of the semiconductor device according to the first example of the present disclosure. Figure 16 is a partially enlarged view showing part of Figure 13. Figure 17 is a partially enlarged view showing part of Figure 4. Figure 18 is a sectional view along line XVIII-XVIII shown in Figure 5. Figure 19 is a sectional view along line XIX-XIX shown in Figure 5. Figure 20 is a sectional view along line XX-XX shown in Figure 5. Figure 21 is a sectional view along line XXI-XXI shown in Figure 5. Figure 22 is a sectional view along line XXII-XXII shown in Figure 5. Figure 23 is an enlarged sectional view corresponding to Figure 16, showing a semiconductor device according to a first embodiment of the first example. Fig. 24 is an enlarged sectional view, which Fig.Fig. 25 is an enlarged sectional view corresponding to Fig. 16, which shows a semiconductor device according to a second embodiment of the first example. Fig. 26 is an enlarged sectional view corresponding to Fig. 16, which shows a semiconductor device according to a third embodiment of the first example. Fig. 27 is an enlarged sectional view corresponding to Fig. 16, which shows a semiconductor device according to a fourth embodiment of the first example. Fig. 28 is a perspective view of a semiconductor device according to a second embodiment of the first aspect of the present disclosure. Fig. 29 is an enlarged sectional view corresponding to Fig. 16, which shows the semiconductor device according to the second embodiment of the present disclosure.Figure 30 is a perspective view of a semiconductor device according to a first embodiment of the invention based on a second aspect of the present disclosure. Figure 31 is a top view of the semiconductor device according to the first embodiment of the invention based on the second aspect of the present disclosure. Figure 32 is a top view corresponding to Figure 31, in which the sealing resin is shown by imaginary lines. Figure 33 is a top view corresponding to Figure 32, with the sealing resin and the second conductive component omitted. Figure 34 is a top view corresponding to Figure 33, with the first conductive component omitted. Figure 35 is a bottom view of the semiconductor device according to the first embodiment of the invention based on the second aspect of the present disclosure. Figure 36 is a sectional view along line XXXVI-XXXVI shown in Figure 32.Figure 37 is a partially enlarged sectional view showing part (near the first element) of Figure 36. Figure 38 is a partially enlarged sectional view showing part (near the second element) of Figure 36. Figure 39 is a sectional view along line XXXIX-XXXIX shown in Figure 32. Figure 40 is a sectional view along line XL-XL shown in Figure 32. Figure 41 is a sectional view along line XLI-XLI shown in Figure 32. Figure 42 is a sectional view along line XLII-XLII shown in Figure 32. Figure 43 is a sectional view along line XLIII-XLIII shown in Figure 32. Figure 44 is a partially enlarged sectional view showing part of Figure 40. Fig. 45 is a sectional view showing one step of a method for manufacturing the semiconductor device according to the first embodiment of the invention based on the second aspect of the present disclosure.Figure 46 is a top view of a semiconductor device according to a first embodiment of the first inventive design based on the second aspect of the present disclosure. Figure 47 is a sectional view along line XLVII-XLVII shown in Figure 46. Figure 48 is a sectional view along line XLVIII-XLVIII shown in Figure 46. Figure 49 is a sectional view corresponding to Figure 40, showing a semiconductor device according to a second embodiment of the second aspect of the first inventive design. Figure 50 is a sectional view corresponding to Figure 47, showing a semiconductor device according to a third embodiment of the second aspect of the first inventive design. Figure 51 is a sectional view corresponding to Figure 40, showing a semiconductor device according to a fourth embodiment of the second aspect of the first inventive design.Figure 52 is a top view of a semiconductor device according to a fifth variant of the first embodiment of the second aspect according to the invention. Figure 53 is a sectional view along the line LIII-LIII shown in Figure 52. MODE FOR EXECUTING THE INVENTION Examples and preferred embodiments of the present disclosure are described in detail below with reference to the drawings. First, an exemplary semiconductor device based on a first aspect of the present disclosure is described with reference to Figs. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28 to 29. A semiconductor device according to the invention, based on a second aspect of the present disclosure, is then described with reference to Figs. 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52 to 53.Furthermore, the reference numerals used in Figs. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28 to 29 (first aspect) and those in Figs. 30, 31, 32, 33, 34, Figs. 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52 to 53 (second aspect) use reference numerals independently of each other. Therefore, the same reference numeral can designate different components of the first and second aspects, or different reference numerals can designate the same (or similar) components of the first and second aspects. In the present revelation, terms such as "first", "second" and "third" are used merely as designations and are not intended to impose any requirements on the order of the elements to which these terms refer. In the description of the present disclosure, the expressions "an object A is formed in an object B" and "an object A is formed on an object B," unless expressly stated otherwise, imply the situations that "the object A is formed directly in or on the object B" and that "the object A is formed in or on the object B with something else inserted between the object A and the object B." Similarly, the expressions "an object A is set up in an object B" and "an object A is set up on an object B," unless expressly stated otherwise, imply the situations that "the object A is set up directly in or on the object B" and that "the object A is set up in or on the object B with something else inserted between the object A and the object B."Furthermore, unless explicitly stated otherwise, the expression "an object A is located on an object B" implies the situations that "object A is located on object B in contact with object B" and that "object A is located on object B with something else inserted between object A and object B." Furthermore, unless explicitly stated otherwise, the expression "an object A overlaps with object B in a certain direction" implies the situations that "object A overlaps with the entirety of object B" and that "object A overlaps with a part of object B."Furthermore, in the description of the present disclosure, the expression “A surface A is facing (a first side or a second side) in a direction B” is not limited to the situation in which the angle of surface A to direction B is 90°, and includes the situation in which surface A is inclined with respect to direction B. First example (First aspect): Figures 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 to 22 show a semiconductor device according to a first example based on the first aspect of the present disclosure. The semiconductor device A1 of the present example comprises a plurality of first semiconductor elements 10A, a plurality of second semiconductor elements 10B, a support substrate 3, a first terminal 41, a second terminal 42, a plurality of third terminals 43, a fourth terminal 44, a plurality of control terminals 45, a control terminal carrier 48, a first conductive component 5, a second conductive component 6 and a sealing resin 8. Fig. 1 is a perspective view of the semiconductor device A1. Figs. 2 and 3 are perspective views showing relevant sections of the semiconductor device A1. Fig. 4 is a top view of the semiconductor device A1. Fig. 5 is a top view showing relevant sections of the semiconductor device A1. Fig. 6 is a side view showing relevant sections of the semiconductor device A1. Fig. 7 is an enlarged top view showing relevant sections of the semiconductor device A1. Figs. 8 and 9 are top views showing relevant sections of the semiconductor device A1. Fig. 10 is a side view of the semiconductor device A1. Fig. 11 is a bottom view of the semiconductor device A1. Fig. 12 is a sectional view along line XII-XII shown in Fig. 5. Fig. 13 is a sectional view along line XIII-XIII shown in Fig. 5. Figs. 14 and 15 are sectional views of the semiconductor device A1.Figures 15 and 16 are top views showing relevant sections of the semiconductor device A1. Figure 16 is a partially enlarged view showing part of Figure 13. Figure 17 is a partially enlarged view showing part of Figure 4. Figure 18 is a sectional view along line XVIII-XVIII shown in Figure 5. Figure 19 is a sectional view along line XIX-XIX shown in Figure 5. Figure 20 is a sectional view along line XX-XX shown in Figure 5. Figure 21 is a sectional view along line XXI-XXI shown in Figure 5. Figure 22 is a sectional view along line XXII-XXII shown in Figure 5. To simplify the description, three mutually orthogonal directions are defined as the x-direction, y-direction, and z-direction. The z-direction is an example of the thickness direction, and the y-direction is an example of the first direction. Furthermore, one side in the x-direction is referred to as the x1-side, while the other side in the x-direction is referred to as the x2-side. Similarly, one side in the y-direction is referred to as the y1-side, while the other side in the y-direction is referred to as the y2-side. Additionally, one side in the z-direction is referred to as the z1-side, while the other side in the z-direction is referred to as the z2-side. Each of the first semiconductor elements 10A and the second semiconductor elements 10B is an electronic component that forms a core component for the function of the semiconductor device A1. The constituent material of the first semiconductor elements 10A and the second semiconductor elements 10B is, for example, a semiconductor material composed primarily of SiC (silicon carbide). The semiconductor material is not limited to SiC and could be, for example, Si (silicon), GaN (gallium nitride), or C (diamond). Each of the first semiconductor elements 10A and the second semiconductor elements 10B is a power semiconductor chip with a switching function, such as a MOSFET (metal-oxide-semiconductor field-effect transistor). In this example, the first semiconductor elements 10A and the second semiconductor elements 10B are MOSFETs, but they are not limited to this and could be other transistors such as IGBTs (insulated-gate bipolar transistors).The first semiconductor elements 10A and the second semiconductor elements 10B are all identical. Each of the first semiconductor elements 10A and the second semiconductor elements 10B is, for example, an n-channel MOSFET, but could also be a p-channel MOSFET. As shown in Figures 14 and 15, each of the first semiconductor elements 10A and the second semiconductor elements 10B has a front element surface 101 and a back element surface 102. The front element surface 101 and the back element surface 102 of each of the first semiconductor elements 10A and the second semiconductor elements 10B are spaced apart from each other in the z-direction. The front element surface 101 faces the z1 side in the z-direction, and the back element surface 102 faces the z2 side in the z-direction. In the present disclosure, the semiconductor device A1 comprises four first semiconductor elements 10A and four second semiconductor elements 10B. However, the number of first semiconductor elements 10A and the number of second semiconductor elements 10B are not limited to this configuration and can be changed as required according to the performance requirements of the semiconductor device A1. In the example shown in Figures 8 and 9, four first semiconductor elements 10A and four second semiconductor elements 10B are provided. The number of first semiconductor elements 10A and the number of second semiconductor elements 10B can be two, three, five, or more. The number of first semiconductor elements 10A and the number of second semiconductor elements 10B can be the same or different.The number of first semiconductor elements 10A and the number of second semiconductor elements 10B are determined based on the current carrying capacity of the semiconductor device A1. The semiconductor device A1 can be configured as a half-bridge circuit. In this case, the first semiconductor elements 10A form the upper branch of the semiconductor device A1, and the second semiconductor elements 10B form the lower branch. In the upper branch circuit, the first semiconductor elements 10A are connected in parallel. In the lower branch circuit, the second semiconductor elements 10B are connected in parallel. Each first semiconductor element 10A and a corresponding second semiconductor element 10B are connected in series to form a bridge layer. As shown in Figures 8, 9, and 21, each of the first semiconductor elements 10A is mounted on the first conductive section 32A of the support substrate 3, which will be described later. In the example shown in Figures 8 and 9, the first semiconductor elements 10A can be aligned in the y-direction and spaced apart from one another. Each of the first semiconductor elements 10A is conductively bonded to the first conductive section 32A via a conductive bonding material 19. When the first semiconductor elements 10A are bonded to the first conductive section 32A, the rear element surfaces 102 face the first conductive section 32A. Unlike the present example, the first semiconductor elements 10A can be mounted on a metal component other than a portion of a DBC substrate or the like. In this case, the metal component corresponds to the first conductive section of the present disclosure.The metal component can, for example, be mounted on a DBC substrate or the like. As shown in Figs. 8, 9, and 20, each of the second semiconductor elements 10B is mounted on the second conductive section 32B of the support substrate 3, which will be described later. In the example shown in Figs. 8 and 9, the second semiconductor elements 10B can be aligned in the y-direction and spaced apart from each other. Each of the second semiconductor elements 10B is conductively bonded to the second conductive section 32B via a conductive bonding material 19. When the second semiconductor elements 10B are bonded to the second conductive section 32B, the rear element surfaces 102 face the second conductive section 32B. As can be seen from Fig. 9, the first semiconductor elements 10A and the second semiconductor elements 10B overlap in the x-direction. However, it is possible that the first semiconductor elements and the second semiconductor elements do not overlap.Unlike in the present example, the second semiconductor elements 10B can be mounted on a metal component other than a part of a DBC substrate or the like. In such a case, the metal component corresponds to the second conductive section of the present disclosure. The metal component can, for example, be mounted on a DBC substrate or the like. Each of the first semiconductor elements 10A and the second semiconductor elements 10B has a first front surface electrode 11, a second front surface electrode 12, a third front surface electrode 13, and a back surface electrode 15. The configurations of the first front surface electrode 11, the second front surface electrode 12, the third front surface electrode 13, and the back surface electrode 15, described below, are common to the first semiconductor elements 10A and the second semiconductor elements 10B. The first front surface electrode 11, the second front surface electrode 12, and the third front surface electrode 13 are provided on the front surface of the element 101. The first front surface electrode 11, the second front surface electrode 12, and the third front surface electrode 13 are insulated from each other by an insulating film (not shown).The back surface electrode 15 is provided on the back surface of the element 102. The first front surface electrode 11 is, for example, a gate electrode through which a control signal (e.g., a gate voltage) is applied to control the first semiconductor element 10A (the second semiconductor element 10B). In each first semiconductor element 10A (every second semiconductor element 10B), the second front surface electrode 12 is, for example, a source electrode through which a source current flows. The second front surface electrode 12 of this example has a gate finger 121. The gate finger 121 is, for example, made of a linear insulator that extends in the x-direction and divides the second front surface electrode 12 into two parts in the y-direction. The third front surface electrode 13 is, for example, a source sensing electrode through which a source current flows. The back surface electrode 15 is, for example, a drain electrode through which a drain current flows.The back surface electrode 15 covers the entire (or substantially the entire) area of ​​the back surface of the element 102. The back surface electrode 15 is formed, for example, by Ag plating (silver plating). Each of the first semiconductor elements 10A (of the second semiconductor elements 10B) switches between a conducting state and an off-state in response to a drive signal (gate voltage) applied to the first front surface electrode 11 (the gate electrode). In the conducting state, a current flows from the back surface electrode 15 (the drain electrode) to the second front surface electrode 12 (the source electrode). In the off-state, this current does not flow. That is, each first semiconductor element 10A (each second semiconductor element 10B) performs a switching operation. The semiconductor device A1 uses the switching function of the first semiconductor elements 10A and the second semiconductor elements 10B to convert, for example, the DC voltage applied between the single fourth terminal 44 and the two terminals 41 and 42 into AC voltage and outputs the AC voltage at the third terminal 43.Each of the first semiconductor elements 10A corresponds to the first switching element of the present disclosure. Each of the second semiconductor elements 10B corresponds to the second switching element of the present disclosure. As shown in Figs. 5, 8 and 9, the semiconductor device A1 includes thermistors 17. The thermistors 17 are used as temperature detection sensors. The semiconductor device can be configured to include, for example, temperature-sensitive diodes instead of the thermistors 17. Alternatively, the semiconductor device may contain neither the thermistors 17 nor any other temperature sensors. The substrate 3 supports the first semiconductor elements 10A and the second semiconductor elements 10B. The specific configuration of the substrate 3 is not restricted. For example, a DBC substrate (Direct-Bonded Copper substrate) or an AMB substrate (Active-Metal Brazing substrate) can be used as the substrate. The substrate 3 has an insulating layer 31, a carrier conductor 32, and a back-surface metal layer 33. The carrier conductor 32 has the first conductive section 32A and the second conductive section 32B. The z-direction dimension of the substrate 3 is, for example, equal to or greater than 0.4 mm and equal to or less than 3.0 mm. The insulating layer 31 is, for example, made of a ceramic material with excellent thermal conductivity. Examples of such ceramic materials include SiN (silicon nitride). The insulating layer 31 is not limited to a ceramic material and can, for example, be a layer of insulating resin. The insulating layer 31 is, for example, rectangular in plan view. The dimension of the insulating layer 31 in the z-direction is, for example, equal to or greater than 0.05 mm and equal to or less than 1.0 mm. The first conductive section 32A carries the first semiconductor elements 10A, and the second conductive section 32B carries the second semiconductor elements 10B. The first conductive section 32A and the second conductive section 32B are formed on the upper surface (the surface facing the z1 side in the z-direction) of the insulating layer 31. The constituent material of the first conductive section 32A and the second conductive section 32B includes, for example, Cu (copper). The constituent material can be Al (aluminum) instead of Cu (copper). The first conductive section 32A and the second conductive section 32B are spaced apart in the x-direction. The first conductive section 32A is located on the x1 side with respect to the second conductive section 32B in the x-direction. The first conductive section 32A and the second conductive section 32B are, for example, rectangular in plan view.The first conductive section 32A and the second conductive section 32B together with the first conductive component 5 and the second conductive component 6 form paths for the main circuit current, which is switched by the first semiconductor elements 10A and the second semiconductor elements 10B. The first conductive section 32A has a first front surface 301A. The first front surface 301A is a flat surface facing the z1 side in the z-direction. The first semiconductor elements 10A are bonded to the first front surface 301A of the first conductive section 32A via a conductive bonding material 19. The second conductive section 32B has a second front surface 301B. The second front surface 301B is a flat surface facing the z1 side in the z-direction. The second semiconductor elements 10B are bonded to the second front surface 301B of the second conductive section 32B via a conductive bonding material 19. The constituent material of the conductive bonding material 19 is not restricted and can be, for example, solder, metal paste, or sintered metal.The dimension of the first conductive section 32A and the second conductive section 32B in the z-direction is, for example, equal to or greater than 0.1 mm and equal to or less than 1.5 mm. The back surface metal layer 33 is formed on the lower surface (the surface facing the z2 side in the z-direction) of the insulating layer 31. The constituent material of the back surface metal layer 33 is the same as that of the carrier conductor 32. The back surface metal layer 33 has a back surface 302. The back surface 302 is the surface facing the z2 side in the z-direction. In the example shown in Fig. 11, the back surface 302 may be exposed by the sealing resin 8. A heat dissipation component (e.g., a heat sink), not shown, may be attached to the back surface 302. The back surface 302 may not be exposed by the sealing resin 8 and may be covered by the sealing resin 8. The back surface metal layer 33 overlaps in plan view with both the first conductive section 32A and the second conductive section 32B. Each of the first terminal 41, second terminal 42, third terminal 43, and fourth terminal 44 is made from a metal plate. The metal plate contains, for example, Cu (copper) or a copper alloy. In the example shown in Figures 1 to 5, 8, 9, and 11, the semiconductor device A1 has one first terminal 41, one second terminal 42, one fourth terminal 44, and two third terminals 43. However, there is no limit to the number of terminals. The DC voltage to be converted is applied to the first terminal 41, the second terminal 42, and the fourth terminal 44. The fourth terminal 44 is a positive electrode (p-type terminal), and the first terminal 41 and the second terminal 42 are each a negative electrode (n-type terminal). The AC voltage converted by the first semiconductor elements 10A and the second semiconductor elements 10B is output at the third terminals 43. Each of the first terminal 41, the second terminal 42, the third terminals 43, and the fourth terminal 44 has a section covered with the sealing resin 8 and a section exposed by the sealing resin 8. As shown in Fig. 13, the fourth terminal 44 is conductively bonded to the first conductive section 32A. There are no restrictions on the conductive bonding methods, and techniques such as ultrasonic bonding, laser bonding, welding, or other methods using solder, metal paste, sintered silver, or the like are employed as required. As shown in Figs. 8 and 9, the fourth terminal 44 is located on the x1 side in the x-direction with respect to the first semiconductor elements 10A and the first conductive section 32A. The fourth terminal 44 conducts electrically to the first conductive section 32A and, via the first conductive section 32A, electrically to the back surface electrode 15 (drain electrode) of each first semiconductor element 10A. The first terminal 41 and the second terminal 42 conduct electrically to the second conductive component 6. In the present example, the first terminal 41 and the second conductive component 6 are formed in one piece. "The first terminal 41 and the second conductive component 6 are formed in one piece" means that they are formed, for example, by cutting and bending a single metal plate, and no bonding material or the like is included for bonding them together. Furthermore, in the present example, the second terminal 42 and the second conductive component 6 are formed in one piece. The first terminal 41 and the second terminal 42 can have other configurations as long as they conduct electrically to the second conductive component 6, and, unlike the present example, can include bonding sections in which these terminals are bonded to the second conductive component. As shown in Fig. 5 and Fig. 6, the first terminal 41 and the second terminal 42 can have different configurations.As shown in Figure 8, the first terminal 41 and the second terminal 42 are located in the x-direction with respect to the first semiconductor elements 10A and the first conductive section 32A on the x1 side. The first terminal 41 and the second terminal 42 conduct electrically to the second conductive component 6 and, via the second conductive component 6, to the second front surface electrode 12 (source electrode) of each second semiconductor element 10B. As shown in Figures 1 to 5 and 11, in the semiconductor device A1, the first terminal 41, the second terminal 42, and the fourth terminal 44 protrude from the sealing resin 8 in the x-direction towards the x1 side. The first terminal 41, the second terminal 42, and the fourth terminal 44 are spaced apart from each other. The first terminal 41 and the second terminal 42 are opposite each other in the y-direction, with the fourth terminal 44 inserted between them. The first terminal 41 is located on the y1 side in the y-direction relative to the fourth terminal 44, and the second terminal 42 is located on the y2 side in the y-direction relative to the fourth terminal 44. The first terminal 41, the second terminal 42, and the fourth terminal 44 overlap each other when viewed in the y-direction. As shown in Figures 8, 9, and 12, the two third terminals 43 are conductively bonded to the second conductive section 32B. The methods of conductive bonding are not limited, and techniques such as ultrasonic bonding, laser bonding, welding, or other methods using solder, metal paste, sintered silver, or the like are employed as required. As shown in Figure 8, the two third terminals 43 are located on the x2 side in the x-direction with respect to the second semiconductor elements 10B and the second conductive section 32B. Each third terminal 43 conducts electrically to the second conductive section 32B and, via the second conductive section 32B, electrically to the back surface electrode 15 (drain electrode) of each second semiconductor element 10B. The number of third terminals 43 is not limited to two and can be one, three, or more.If only a third terminal 43 is provided, the third terminal 43 is preferably connected to the central part in the y-direction of the second conductive section 32B. The control terminals 45 are pin-shaped terminals for controlling the first semiconductor elements 10A and the second semiconductor elements 10B. These control terminals 45 are, for example, press-fit terminals. The control terminals 45 comprise a variety of first control terminals 46A to 46E and a variety of second control terminals 47A to 47D. The first control terminals 46A to 46E are used, for example, to control the first semiconductor elements 10A. The second control terminals 47A to 47D are used, for example, to control the second semiconductor elements 10B. The first control terminals 46A to 46E are spaced apart in the y-direction. As shown in Figs. 8, 13, and 22, the first control terminals 46A to 46E are supported on the first conductive section 32A by the control terminal carrier 48 (the first carrier section 48A described later). As shown in Figs. 5 and 8, the first control terminals 46A to 46E are located in the x-direction between the first semiconductor elements 10A and the first, second, and fourth terminals 41, 42, and 44. The first control terminal 46A is a terminal (a gate terminal) for inputting a control signal for the first semiconductor elements 10A. A control signal for controlling the first semiconductor elements 10A is input to the first control terminal 46A (e.g., a gate voltage is applied there). The first control terminal 46B is a terminal (a source detection terminal) for detecting a source signal of the first semiconductor elements 10A. The voltage applied to the second front surface electrode 12 (the source electrode) of each first semiconductor element 10A (the voltage corresponding to the source current) is detected at the first control terminal 46B. The first control terminal 46C and the first control terminal 46D are terminals that conduct electrically to a thermistor 17. The first control terminal 46E is a terminal (a drain detection terminal) for detecting a drain signal from the first semiconductor elements 10A. The voltage applied to the back surface electrode 15 (the drain electrode) of each first semiconductor element 10A (the voltage corresponding to the drain current) is detected by the first control terminal 46E. The second control terminals 47A to 47D are spaced apart in the y-direction. As shown in Figs. 8 and 13, the second control terminals 47A to 47D are supported on the second conductive section 32B by the control terminal carrier 48 (the second carrier section 48B described later). As shown in Figs. 5 and 8, the second control terminals 47A to 47D are located in the x-direction between the second semiconductor elements 10B and the two third terminals 43. The second control terminal 47A is a terminal (a gate terminal) for inputting a drive signal for the second semiconductor elements 10B. A drive signal to activate the second semiconductor elements 10B is input to the second control terminal 47A (e.g., a gate voltage is applied there). The second control terminal 47B is a terminal (a source detection terminal) for detecting a source signal from the second semiconductor elements 10B. The voltage applied to the second front surface electrode 12 (the source electrode) of each second semiconductor element 10B (the voltage corresponding to the source current) is detected by the second control terminal 47B. The second control terminal 47C and the second control terminal 47D are terminals that conduct electrically to a thermistor 17. Each of the control terminals 45 (the first control terminals 46A to 46E and the second control terminals 47A to 47E) has a holder 451 and a metal pin 452. The holders 451 are made of an electrically conductive material. As shown in Figs. 14 and 15, the holders 451 are bonded to the control terminal carrier 48 (the first metal layer 482 described later) via a conductive bonding material 459. As shown in Fig. 16, each holder 451 has a tubular section 453, a first flanged section 454, and a second flanged section 455. The tubular section 453 extends in the z-direction and is, for example, cylindrical. The tubular section 453 has a first outer surface 453a and a first inner surface 453b. The first outer surface 453a faces radially outward from the tubular section 453 when viewed in the z-direction and extends in the z-direction. The first inner surface 453b faces the side opposite the first outer surface 453a when viewed in the z-direction, i.e., it faces radially inward from the tubular section 453 and extends in the z-direction. The first flange section 454 is connected to the end on the z1 side in the z-direction of the tubular section 453. The first flange section 454 has a first surface 454a and a second surface 454b. The first surface 454a faces the z1 side in the z-direction. The first surface 454a is located at the end on the z1 side in the z-direction of the holder 451. Viewed in the z-direction, the first surface 454a has the shape of a loop (a circular loop or a rectangular loop). The second surface 454b is located on the z2 side in the z-direction relative to the first surface 454a and faces the z2 side in the z-direction. The second flange section 455 is connected to the end on the z2 side in the z-direction of the tubular section 453. In the present example, the second flange section 455 is bonded to the control connection carrier 48 (the first metal layer 482 described later) via a conductive bonding material 459. A metal pin 452 is inserted into at least the first flange section 454 and the tubular section 453 of each holder 451. Part of the holder 451 is covered with the sealing resin 8. At least the first outer surface 453a (the tubular section 453) is in contact with the sealing resin 8. In the example shown in Fig. 16, the first outer surface 453a of the tubular section 453 and the second surface 454b of the first flange section 454 are completely in contact with the sealing resin 8. Each metal pin 452 is a rod-shaped component extending in the z-direction. The metal pin 452 is supported by being pressed into a holder 451. The metal pin 452 conducts electrically, at least via the holder 451, to the control terminal carrier 48 (of the first metal layer 482 described below). In the example shown in Figures 14, 15 to 16, the metal pin 452 is not inserted into the lower end (the end on the z2 side in the z-direction) of the holder 451, and the lower end of the metal pin 452 is spaced apart from the conductive bonding material 459. In this case, the metal pin 452 conducts electrically via the holder 451 to the control terminal carrier 48 (of the first metal layer 482).In the case where the lower end of the metal pin 452 (the end on the z2 side in the z-direction) is in contact with the conductive bonding material 459 inside the through-hole of the holder 451, unlike in the illustrated example, the metal pin 452 conducts electrically to the control terminal carrier 48 via the conductive bonding material 459. The metal pin 452 protrudes in the z-direction beyond the upper surface (the front resin surface 81 described later) of the sealing resin 8 towards the z1 side. The control connector carrier 48 carries the control connections 45. The control connector carrier 48 is inserted in the z-direction between the first and the second front surfaces 301A and 301B and the control connections 45. The control terminal carrier 48 has a first carrier section 48A and a second carrier section 48B. The first carrier section 48A is mounted on the first conductive section 32A and carries the first control terminals 46A to 46E of the control terminals 45. As shown in Fig. 14, the first carrier section 48A is bonded to the first conductive section 32A via a bonding material 49. The bonding material 49 can be electrically conductive or insulating and can, for example, be solder. The second carrier section 48B is mounted on the second conductive section 32B and carries the second control terminals 47A to 47D of the control terminals 45. As shown in Fig. 15, the second carrier section 48B is bonded to the second conductive section 32B via the bonding material 49. The control terminal carrier 48 (each consisting of the first carrier section 48A and the second carrier section 48B) is provided, for example, by a DBC substrate (direct-bonded copper substrate). The control terminal carrier 48 has an insulating layer 481, a first metal layer 482, and a second metal layer 483, which are laminated on top of each other. The insulating layer 481, for example, is made of a ceramic material. The insulating layer 481 is rectangular in plan view. As shown in Figures 14 and 15, the first metal layer 482 is formed on the upper surface of the insulating layer 481. Each control terminal 45 is located on the first metal layer 482. The first metal layer 482 contains, for example, Cu (copper) or a Cu alloy (copper alloy). As shown in Figure 8, the first metal layer 482 has a first section 482A, a second section 482B, a third section 482C, a fourth section 482D, a fifth section 482E, and a sixth section 482F. The first section 482A, the second section 482B, the third section 482C, the fourth section 482D, the fifth section 482E, and the sixth section 482F are spaced apart from and insulated from one another. The first section 482A, to which a plurality of wires 71 are bonded, conducts electrically via the wires 71 to the first front surface electrodes 11 (gate electrodes) of the first semiconductor elements 10A (of the second semiconductor elements 10B). A plurality of wires 73 are connected to the first section 482A and the sixth section 482F. Thus, the sixth section 482F conducts electrically via the wires 73 and the wires 71 to the first front surface electrodes 11 (gate electrodes) of the first semiconductor elements 10A (of the second semiconductor elements 10B). As shown in Fig. 8, the first control terminal 46A is bonded to the sixth section 482F of the first support section 48A, and the second control terminal 47A is bonded to the sixth section 482F of the second support section 48B. The second section 482B, to which a plurality of wires 72 are bonded, conducts electrically via the wires 72 to the third front surface electrodes 13 (source detection electrodes) of the first semiconductor elements 10A (of the second semiconductor elements 10B). As shown in Fig. 8, the first control terminal 46B is bonded to the second section 482B of the first support section 48A, and the second control terminal 47B is bonded to the second section 482B of the second support section 48B. A thermistor 17 is bonded to the third section 482C and the fourth section 482D. As shown in Fig. 8, the first control terminals 46C and 46D are each bonded to the third section 482C and the fourth section 482D of the first carrier section 48A. The second control terminals 47C and 47D are each bonded to the third section 482C and the fourth section 482D of the second carrier section 48B. The fifth section 482E of the first support section 48A, to which a wire 74 is bonded, conducts electrically via the wire 74 to the first conductive section 32A. As shown in Fig. 8, the first control terminal 46E is bonded to the fifth section 482E of the first support section 48A. The fifth section 482E of the second support section 48B does not conduct electrically to other components. Each of the wires 71 to 74 is, for example, a bonding wire. The constituent material of the wires 71 to 74 includes, for example, Au (gold), Al (aluminum), or Cu (copper). As shown in Figs. 14 and 15, the second metal layer 483 is formed on the lower surface of the insulating layer 481. As shown in Fig. 14, the second metal layer 483 of the first support section 48A is bonded to the first conductive section 32A via the bonding material 49. As shown in Fig. 15, the second metal layer 483 of the second support section 48B is bonded to the second conductive section 32B via a bonding material 49. The first conductive component 5 and the second conductive component 6, together with the first conductive section 32A and the second conductive section 32B, form a path for the main circuit current switched by the first semiconductor elements 10A and the second semiconductor elements 10B. The first conductive component 5 and the second conductive component 6 are spaced in the z-direction from the first front surface 301A and the second front surface 301B towards the z1 side and overlap with the first front surface 301A and the second front surface 301B in a top view. In this example, the first conductive component 5 and the second conductive component 6 are made of metal plates. The metal includes, for example, Cu (copper) or a Cu alloy (copper alloy). In particular, the first conductive component 5 and the second conductive component 6 are metal plates that have been bent as required. The first conductive component 5 is connected to the second front surface electrode 12 (the source electrode) of each first semiconductor element 10A and to the second conductive section 32B to conduct electrically to the second front surface electrode 12 of each first semiconductor element 10A and to the second conductive section 32B. The first conductive component 5 forms a path for the main circuit current switched by the first semiconductor elements 10A. As shown in Figures 7 and 8, the first conductive component 5 has a main section 51, a plurality of first bonding sections 52, and a plurality of second bonding sections 53. The main section 51 is located in the x-direction between the first semiconductor elements 10A and the second conductive section 32B and has a striped shape extending in the y-direction in plan view. In plan view, the main section 51 overlaps both the first conductive section 32A and the second conductive section 32B and is spaced in the z-direction from the first front surface 301A and the second front surface 301B towards the z1 side. As shown in Fig. 18, the main section 51 is located in the z-direction on the z2 side with respect to the third path section 66 and the fourth path section 67 of the second conductive component 6 described later, and is closer to the first front surface 301A and the second front surface 301B than the third path section 66 and the fourth path section 67. In the present example, the main section 51 is parallel to the first front surface 301A and the second front surface 301B. As shown in Fig. 8, the main section 51 extends continuously in the y-direction, corresponding to the regions where the first semiconductor elements 10A are arranged. In the present example, the main section 51 is configured with a plurality of first openings 514, as shown in Figs. 7, 8, and 13. Each of the first openings 514 is a through-hole that penetrates, for example, in the z-direction (the plate thickness direction of the main section 51). The first openings 514 are arranged at intervals in the y-direction. The first openings 514 are provided such that they correspond to the respective first semiconductor elements 10A. In the present example, four first openings 514 are provided in the main section 51, and these first openings 514 and the plurality of (four) first semiconductor elements 10A are located at the same positions in the y-direction. In the present example, each of the first openings 514 overlaps the gap between the first conductive section 32A and the second conductive section 32B in plan view, as shown in Figs. 8 and 13. The first openings 514 are designed to allow the flow of resin material between the top side (the z1 side in the z-direction) and the bottom side (the z2 side in the z-direction) at or near the main section 51 (the first conductive component 5) when the flowable resin material is injected to form the sealing resin 8. As shown in Fig. 8, the first bonding sections 52 and the second bonding sections 53 are connected to the main section 51 and arranged to correspond to the first semiconductor elements 10A. In particular, each of the first bonding sections 52 is located on the x1 side in the x-direction with respect to the main section 51. Each of the second bonding sections 53 is located on the x2 side in the x-direction with respect to the main section 51. As shown in Fig. 14, each of the first bonding sections 52 and the second front surface electrode 12 of a relevant first semiconductor element 10A are bonded via a conductive bonding material 59. Each of the second bonding sections 53 and the second conductive section 32B are bonded via a conductive bonding material 59. The constituent material of the conductive bonding materials 59 is not subject to any special restrictions and can be, for example, solder, metal paste or sintered metal.In the present example, each of the first bonding sections 52 has two parts separated in the y-direction. These two parts are bonded to the second front surface electrode 12 of the first semiconductor element 10A to flank the gate finger 121 of the second front surface electrode 12 in the y-direction. The second conductive component 6 conducts electrically to the second front surface electrode 12 (source electrode) of each second semiconductor element 10B and to the first and second terminals 41 and 42. The second conductive component 6 is integrally formed with the first terminal 41 and the second terminal 42. The second conductive component 6 forms a path for the main circuit current switched by the second semiconductor elements 10B. As shown in Figures 5 to 7, 12, 13, and 18 to 22, the second conductive component 6 has a plurality of third bonding sections 61, a first path section 64, a second path section 65, a plurality of third path sections 66, and a fourth path section 67. In addition, in the illustrated example, the second conductive component 6 has a first stepped section 602 and a second stepped section 603. The third bonding sections 61 are individually bonded to the second semiconductor elements 10B. Each of the third bonding sections 61 and the second front surface electrode 12 of a relevant second semiconductor element 10B are bonded via a conductive bonding material 69. The constituent material of the conductive bonding materials 69 is not subject to any particular restrictions and can, for example, be solder, metal paste, or sintered metal. In the present example, each third bonding section 61 has two flat sections 611 and two first inclined sections 612. The two flat sections 611 are aligned in the y-direction. The two flat sections 611 are spaced apart from each other in the y-direction. The shape of the flat sections 611 is not restricted, but is rectangular in the illustrated example. The two flat sections are bonded to the second front surface electrode 12 of the second semiconductor element 10B to flank the gate finger 121 of the second front surface electrode 12 in the y-direction. The first two inclined sections 612 are connected in the y-direction to the outer edges of the two flat sections 611. That is, the first inclined section 612 located on the y1 side in the y-direction is connected to the edge in the y-direction on the y1 side of the flat section 611 located on the y1 side in the y-direction. Furthermore, the first inclined section 612 located on the y2 side in the y-direction is connected to the edge in the y-direction on the y2 side of the flat section 611 located on the y2 side in the y-direction. Each first inclined section 612 is inclined such that, with increasing distance in the y-direction from the flat section 611, it extends in the z-direction towards the z1 side. The first path section 64 is inserted between the third bonding sections 61 and the first terminal 41. In the illustrated example, the first path section 64 is connected to the first terminal 41 via the first stepped section 602. In plan view, the first path section 64 overlaps with the first conductive section 32A. The first path section 64 has a shape that extends in the x-direction. The first path section 64 has a first strip section 641 and a first extension section 643. The first strip section 641 is located in the x-direction on the x2 side with respect to the first terminal 41 and is generally parallel to the first front surface 301A. The first strip section 641 has a shape that extends overall in the x-direction. In the illustrated example, the first strip section 641 has a recess 649. The recess 649 is the section in which a portion of the first strip section 641 is recessed or hollowed out in the y-direction towards the y1 side. In Figures 5 and 7, the first conductive section 32A is visible through the recess 649. The first extension section 643 extends from the side edge of the first strip section 641 in the y-direction on the y1 side and in the z-direction towards the z2 side. The first extension section 643 is spaced apart from the first conductive section 32A. In the illustrated example, the first extension section 643 extends along the z-direction and has a rectangular shape that is elongated in the x-direction. It is also possible that the first path section 64 does not include the first extension section 643. The second path section 65 is inserted between the third bonding sections 61 and the second terminal 42. In the illustrated example, the second path section 65 is connected to the second terminal 42 via the second stepped section 603. In plan view, the second path section 65 overlaps with the first conductive section 32A. The second path section 65 has a shape that extends overall in the x-direction. The second path section 65 has a second strip section 651 and a second extension section 653. The second strip section 651 is located in the x-direction on the x2 side with respect to the second terminal 42 and is generally parallel to the first front surface 301A. The second strip section 651 has a shape that extends overall in the x-direction. In the illustrated example, the second strip section 651 has a recess 659. The recess 659 is the section in which a portion of the second strip section 651 is cut out in the y-direction towards the y2 side. In Figures 5 and 7, the first conductive section 32A is visible through the recess 659. The second extension section 653 extends from the side edge of the second strip section 651 on the y2 side in the y-direction and z-direction towards the z2 side. The second extension section 653 is spaced apart from the first conductive section 32A. As with the first extension section 643, the second extension section 653 extends along the z-direction and has a rectangular shape that is elongated in the x-direction. Furthermore, the second path section 65 may not include the second extension section 653. The third path segments 66 are individually connected to the third bonding segments 61. The third path segments 66, each extending in the x-direction, are spaced apart from one another in the y-direction. There is no limit to the number of third path segments 66. In the illustrated example, five third path segments 66 are configured. Each of the third path segments 66 is configured to be located in the y-direction between the second semiconductor elements 10B or in the y-direction on the outside of the second semiconductor elements 10B. The two third path sections 66, located on opposite outer surfaces in the y-direction, are formed with recesses 669. The recesses 669 extend from the inside to the outside in the y-direction. In the illustrated example, a recess 669 is formed in each of the two third path sections 66. In Figures 5 and 7, the second conductive section 32B is visible through the recesses 669. In the present example, a third bonding section 61 is established between two adjacent third path sections 66 in the y-direction. In each third bonding section 61, the first inclined section 612 located on the y1 side in the y-direction is connected to one of the two adjacent third path sections 66 located on the y1 side in the y-direction. In each third bonding section 61, the first inclined section 612 located on the y2 side in the y-direction is connected to one of the two adjacent third path sections 66 located on the y2 side in the y-direction. The fourth path segment 67 is connected to the ends on the x1 side in the x-direction of the plurality of third path segments 66. The fourth path segment 67 has a shape that is elongated in the y-direction. The fourth path segment 67 is connected to the ends on the x2 side in the x-direction of the first strip segment 641 of the first path segment 64 and the second strip segment 651 of the second path segment 65. In the illustrated example, the first path segment 64 is connected to the end on the y1 side in the y-direction of the fourth path segment 67. The second path segment 65 is connected to the end on the y2 side in the y-direction of the fourth path segment 67. The sealing resin 8 covers the first semiconductor elements 10A, the second semiconductor elements 10B, the support substrate 3 (except for the rear surface 302), a portion of each of the first terminal 41, the second terminal 42, the third terminals 43, and the fourth terminal 44, a portion of each of the control terminals 45, the control terminal carrier 48, the first conductive component 5, the second conductive component 6, and the wires 71 to 74. The sealing resin 8 is made, for example, of black epoxy resin. The sealing resin 8 is formed, for example, by molds. The sealing resin 8 has dimensions of, for example, approximately 35 mm to 60 mm in the x-direction, approximately 35 mm to 50 mm in the y-direction, and approximately 4 mm to 15 mm in the z-direction. These dimensions represent the size of the largest section along each direction.The sealing resin 8 has a front resin surface 81, a rear resin surface 82 and a plurality of side resin surfaces 831 to 834. As shown in Figs. 10, 12, and 20, the front resin surface 81 and the rear resin surface 82 are spaced apart in the z-direction. The front resin surface 81 faces the z1 side in the z-direction, and the rear resin surface 82 faces the z2 side in the z-direction. The metal pins 452 of the control terminals 45 (the first control terminals 46A to 46E and the second control terminals 47A to 47D) protrude from the front resin surface 81. As shown in Fig. 11, the rear resin surface 82 has a frame shape in plan view that surrounds the rear surface 302 of the support substrate 3 (the lower surface of the rear surface metal layer 33). The rear surface 302 of the carrier substrate 3 lies exposed on the rear resin surface 82 and can be flush with the rear resin surface 82.Each of the lateral resin surfaces 831 to 834 is connected to the front resin surface 81 and the rear resin surface 82 and is positioned between these surfaces in the z-direction. As shown in Fig. 4, the lateral resin surface 831 and the lateral resin surface 832 are spaced apart in the x-direction. The lateral resin surface 831 faces the x2 side in the x-direction, and the lateral resin surface 832 faces the x1 side in the x-direction. The two third connections 43 project from the lateral resin surface 831, and the first connection 41, the second connection 42, and the fourth connection 44 project from the lateral resin surface 832. As shown in Fig. 4, the lateral resin surfaces 833 and 834 are spaced apart in the y-direction. The lateral resin surface 833 points in the y-direction towards the y2 side, and the lateral resin surface 834 points in the y-direction towards the y1 side. In the present example, the front resin surface 81 is formed with a plurality of first recesses 810, as shown in Figs. 1, 4, 13 and 22. Each of the first recesses 810 is cut out of the front resin surface 81 in the z-direction towards the z2 side. The first recesses 810 are provided corresponding to the control connections 45. As shown in Figures 16 and 17, the first recess 810 overlaps the entire tubular section 453 of the holder 451 in plan view. In the illustrated example, the first recess 810 has an inner surface 811 and a bottom surface 812. The inner surface 811 is connected to the front resin surface 81 and extends in the z-direction toward the z2 side. In the illustrated example, the cross-section of the inner surface 811, which is orthogonal to the z-direction, is circular. The bottom surface 812, which is connected to the end on the z2 side in the z-direction of the inner surface 811, is a flat surface facing the z1 side in the z-direction. In plan view, the recess bottom surface 812 surrounds the first surface 454a of the holder 451 (the first flange section 454). The first surface 454a and the recess bottom surface 812 are flush with each other. The first recess 810, which has such a configuration, is a trace from the forming of the sealing resin 8 by molding, while the upper end (the first flange section 454) of the holder 451 is pressed, for example, with a pin or the like, which has a shape corresponding to the first recess 810. In each of the variants described later, the first recess 810 is also a trace from the molding process. The first flange section 454 is located on the z2 side in the z-direction with respect to the front resin surface 81. As shown in Fig.As shown in Figure 16, the first outer surface 453a of the tubular section 453 and the second surface 454b of the first flange section 454 are both in complete contact with the sealing resin 8. In contrast, the first inner surface 453b of the tubular section 453 and the first surface 454a of the first flange section 454 are free from the sealing resin 8. In the example shown in Figures 16 and 17, the first recess 810 overlaps the entire first flange section 454 when viewed in the z-direction. Thus, the diameter (the maximum value of the inner diameter) of the first recess 810 is larger than the outer diameter of the first flange section 454. The first surface 454a, which is flush with the recess base surface 812, is located in a different position in the z-direction than the front resin surface 81. In particular, the first surface 454a is located on the z2 side in the z-direction with respect to the front resin surface 81. In the present example, the first dimension L1, which is the distance between the front resin surface 81 and the first surface 454a in the z-direction, is smaller than the second dimension L2, which is the length of the holder 451 in the z-direction. Preferably, the ratio of the distance in the z-direction between the front resin surface 81 and the first surface 454a (the first dimension L1) to the length of the holder 451 in the z-direction (the second dimension L2) is equal to or greater than 1 / 3. Although the recess inner surface 811 is cylindrical in the example shown in Figures 16 and 17, it can have a draft angle for forming. When the recess inner surface 811 has a draft angle, it is inclined to form a tapered shape with an inner diameter that decreases in the z-direction towards the z2 side. The draft angle of the recess inner surface 811 can be suitably set, for example, in the range of 0° to 30°. In the case where the recess inner surface 811 is inclined in a tapered manner, if the angle of inclination is relatively large, the inner diameter of the lower end (the end on the z2 side in the z-direction) of the recess inner surface 811 can be smaller than the outer diameter of the first flange section 454.In such a case, the recess bottom surface 812 described above is not formed. In this case, the lower end of the recess inner side surface 811 is in contact with the first surface 454a and forms a recess end edge. As shown in Fig. 4, the lateral resin surface 832 is formed with a plurality of recesses 832a. Each recess 832a is a section that is cut out in the x-direction in plan view. The recesses 832a have, in plan view, one formed between the first connection 41 and the fourth connection 44, and one formed between the second connection 42 and the fourth connection 44. The recesses 832a are provided to increase the creepage distance between the first connection 41 and the fourth connection 44 along the lateral resin surface 832 and the creepage distance between the second connection 42 and the fourth connection 44 along the lateral resin surface 832. As shown in Figs. 1, 12, and 13, the sealing resin 8 has a plurality of projections 851. The projections 851 extend in the z-direction from the front resin surface 81 toward the z1 side. In plan view, the projections 851 are arranged at four corners of the sealing resin 8. Each projection 851 has a projection end surface 851a at its outermost end (the end on the z1 side in the z-direction). The projection end surfaces 851a of the projections 851 are parallel (or generally parallel) to the front resin surface 81 and lie in the same plane (xy-plane). Each projection 851 can, for example, have the shape of a truncated hollow cone with a base. The protrusions 851 are used as spacers when the semiconductor device A1 is mounted on a control board or the like of a device configured to utilize the energy generated by the semiconductor device A1.Each of the projections 851 has a recess 851b and an inner wall surface 851c formed around the recess 851b. The shape of each projection 851 can be columnar and preferably cylindrical. The shape of the recess 851b can be cylindrical. The inner wall surface 851c can preferably have the shape of a single perfect circle in plan view. The semiconductor device A1 can, for example, be mechanically attached to a control board or the like by screwing it in place. In such a case, internal threads can be formed on the inner wall surfaces 851c of the recesses 851b of the projections 851. Insertion nuts can be embedded in the recesses 851b of the projections 851. Next, the effects of the present example will be described. Each of the holders 451, which form the control terminals 45, has a first surface 454a and a first outer surface 453a. The first surface 454a is located at the end on the zl-side in the z-direction of the holder 451. The first surface 454a is located in a position that differs in the z-direction from the front resin surface 81. The first outer surface 453a extends in the z-direction and is in contact with the sealing resin 8. The metal pins 452, which form the control terminals 45, project in the z-direction beyond the front resin surface 81 toward the z1-side. In such a configuration, the control terminals 45 are located in the top view within the areas surrounded by the front resin surface 81 (the sealing resin 8). The semiconductor device A1 with such a configuration enables a reduction in size in the top view.Furthermore, the first surface 454a is located at a position that differs in the z-direction from the front resin surface 81. Such a configuration increases the creepage distance between adjacent control terminals 45 along the surfaces (front resin surface 81, etc.) of the sealing resin 8. Thus, the semiconductor device A1 is suitable for increasing the withstand voltage of adjacent control terminals 45 while simultaneously reducing its size in plan view. The holder 451 has the tubular section 453 extending in the z-direction and the first flange section 454, which is connected to the end on the z1 side in the z-direction of the tubular section 453. On the first flange section 454, the first surface 454a faces the z1 side in the z-direction. The sealing resin 8 has the first recess 810. The first recess 810 extends in the z-direction from the front resin surface 81 towards the z2 side. The first flange section 454 is located on the z2 side in the z-direction with respect to the front resin surface 81. The sealing resin 8 with the first recess 810 enables the first surface 454a (the first flange section 454) to be arranged in a suitable manner in the z-direction at a different position than the front resin surface 81. Furthermore, the first recess 810 overlaps the entire tubular section 453 in a top view (viewed in the z-direction). With this configuration, when the metal pin 452 is pressed into the holder 451, it is possible to insert the metal pin 452 into the holder 451 (the tubular section 453) while the lower end of the metal pin 452 is advanced through the first recess 810. This facilitates the pressing-in process. The first recess 810 has the recess inner surface 811 and the recess bottom surface 812. The recess bottom surface 812 faces the z1 side in the z-direction and surrounds the first surface 454a in the z-direction. The entire first surface 454a is exposed by the sealing resin 8. In this configuration, the first surface 454a (the first flange section 454), which is surrounded by the recess bottom surface 812, is clearly visible in plan view. This facilitates the step of pressing the metal pin 452 into the holder 451. Furthermore, the configuration in which the recess bottom surface 812 of the first recess 810 surrounds the first surface 454a (the first flange section 454) in plan view can increase the creepage distance between adjacent control ports 45 along the surfaces of the sealing resin 8. This is advantageous for increasing the withstanding voltage of adjacent control terminals 45. The distance between the front resin surface 81 and the first surface 454a in the z-direction (the first dimension L1) is less than the length of the holder 451 in the z-direction (the second dimension L2). For example, the ratio of the distance in the z-direction between the front resin surface 81 and the first surface 454a (the first dimension L1) to the length of the holder 451 in the z-direction (to the second dimension L2) is equal to or greater than 50%. Such a configuration makes it possible to increase the creepage distance between adjacent control terminals 45 along the surfaces of the sealing resin 8 while simultaneously avoiding an increase in the dimension of the sealing resin 8 in the z-direction. First variant of the first example (First aspect): Fig. 23 shows a semiconductor device according to a first variant of the first example. Fig. 23 is an enlarged sectional view corresponding to Fig. 16, showing relevant sections of the semiconductor device A11 of the present variant. In Figs. 23, 24, 25, 26, 27, 28 to 29, the elements that are identical or similar to those of the semiconductor device A1 of the example described above are designated with the same reference numerals as those used for the example described above, and their descriptions are omitted. Different parts of variants and examples may be selectively used in any suitable combination, provided this is technically compatible. The semiconductor device A11 of the present variant differs from the semiconductor device A1 of the example described above in the configuration of the first recesses 810. In the semiconductor device A11, each first recess 810 has a recess end edge 813 and a cylindrical inner surface 814. The cylindrical inner surface 814 has a cylindrical shape extending from the front resin surface 81 in the z-direction to the z2 side. The recess end edge 813 is located at the lower end (the end on the z2 side in the z-direction) of the cylindrical inner surface 814. The recess end edge 813 is in contact with the first surface 454a. In the present variant, the recess end edge 813 is in contact with the first surface 454a at a radially central position.A radially outer section of the first surface 454a is covered with the sealing resin 8, and the remaining radially inner section is free of the sealing resin 8. In plan view, the outer circumference of the first flange section 454 surrounds the first recess 810. That is, the diameter (the maximum value of the inner diameter) of the first recess 810 is smaller than the outer diameter of the first flange section 454. Although the cylindrical inner surface 814 is cylindrical in the example shown in Fig. 23, the cylindrical inner surface 814 may have a draft angle. If the cylindrical inner surface 814 has a draft angle, it is inclined to form a tapered shape with an inner diameter that decreases in the z-direction toward the z2-side. In the semiconductor device A11 of the present variant, each of the holders 451, which form the control terminals 45, has a first surface 454a and a first outer surface 453a. The first surface 454a is located at the end on the z1 side in the z-direction of the holder 451. The first surface 454a is located in a position that differs in the z-direction from the front resin surface 81. The first outer surface 453a extends in the z-direction and is in contact with the sealing resin 8. The metal pins 452, which form the control terminals 45, project in the z-direction beyond the front resin surface 81 toward the z1 side. In such a configuration, the control terminals 45 are located in plan view in the areas surrounded by the front resin surface 81 (the sealing resin 8). The semiconductor device A11 with such a configuration enables a size reduction in top view.Furthermore, the first surface 454a is located at a position that differs from the front resin surface 81 in the z-direction. Such a configuration increases the creepage distance between adjacent control terminals 45 along the surfaces (front resin surface 81, etc.) of the sealing resin 8. Thus, the semiconductor device A11 is suitable for increasing the withstand voltage of adjacent control terminals 45 while simultaneously reducing its size in plan view. Moreover, a configuration common to the semiconductor device A1 of the example described above provides the same effects as the example described above. Second variant of the first example (First aspect): Fig. 24 shows a semiconductor device according to a second variant of the first example. Fig. 24 is an enlarged sectional view corresponding to Fig. 16, showing relevant sections of the semiconductor device A12 of the present variant. The semiconductor device A12 of the present variant differs from the semiconductor device A1 of the example described above in the configuration of the first recesses 810. Each of the first recesses 810 has a recess end edge 813, a cylindrical inner surface 814, and a tapered inner surface 815. The cylindrical inner surface 814 has a cylindrical shape extending from the front resin surface 81 in the z-direction to the z2 side. The tapered inner surface 815 is connected to the lower end (the end on the z2 side in the z-direction) of the cylindrical inner surface 814. The recess end edge 813 is located at the lower end (the end on the z2 side in the z-direction) of the tapered inner surface 815. The tapered inner surface 815 is inclined such that the inner diameter increases in the z-direction toward the z1 side. The recess end edge 813 is in contact with the first surface 454a.In the present embodiment, the recess end edge 813 is in contact with the first surface 454a at a radially central position. A radially outer section of the first surface 454a is covered with the sealing resin 8, and the remaining radially inner section is free of the sealing resin 8. In plan view, the outer circumference of the first flange section 454 surrounds the first recess 810. In the semiconductor device A12 of the present embodiment, each of the holders 451, which form the control terminals 45, has a first surface 454a and a first outer surface 453a. The first surface 454a is located at the end on the z1 side in the z-direction of the holder 451. The first surface 454a is located in a position that differs in the z-direction from the front resin surface 81. The first outer surface 453a extends in the z-direction and is in contact with the sealing resin 8. The metal pins 452, which form the control terminals 45, project in the z-direction beyond the front resin surface 81 toward the z1 side. In such a configuration, the control terminals 45 are located, in plan view, in the areas surrounded by the front resin surface 81 (the sealing resin 8). The semiconductor device A12 with such a configuration enables a size reduction in top view.Furthermore, the first surface 454a is located at a position that differs in the z-direction from the front resin surface 81. Such a configuration increases the creepage distance between adjacent control terminals 45 along the surfaces (front resin surface 81, etc.) of the sealing resin 8. Thus, the semiconductor device A12 is suitable for increasing the withstand voltage of adjacent control terminals 45 while simultaneously reducing its size in plan view. The recess end edge 813 of the first recess 810, located on the z2 side in the z-direction, is in contact with the first surface 454a of the first flange section 454. Furthermore, the tapered inner surface 815 of the first recess 810 is connected to the recess end edge 813, and the inner diameter of the tapered inner surface 815 increases in the z-direction towards the z1 side. In such a configuration, when the metal pin 452 is pressed into the holder 451, the metal pin 452, which is advanced into the first recess 810, can be guided from the tapered inner surface 815 towards the holder 451 (towards the tubular section 453). This facilitates the pressing operation of the metal pin 452 into the holder 451.Furthermore, a configuration common to the semiconductor device A1 of the example described above offers the same effects as the example described above. Third variant of the first example (First aspect): Fig. 25 shows a semiconductor device according to a third variant of the first example. Fig. 25 is an enlarged sectional view corresponding to Fig. 16, showing relevant sections of the semiconductor device A13 of the present variant. The semiconductor device A13 of the present variant differs from the semiconductor device A1 of the example described above in the configuration of the first recesses 810. Each of the first recesses 810 has a recess end edge 813, a cylindrical inner surface 814, and a tapered inner surface 815. In the present embodiment, the shapes of the cylindrical inner surface 814 and the tapered inner surface 815 are the same in longitudinal section as those of the semiconductor device A12 shown in Fig. 24. In the present embodiment, the recess end edge 813 is in contact with the radially inner edge of the first surface 454a. Therefore, the entire (or almost the entire) first surface 454a is covered with the sealing resin 8. The outer circumference of the first flange section 454 surrounds the first recess 810 in plan view. In the semiconductor device A13 of the present embodiment, each of the holders 451, which form the control terminals 45, has a first surface 454a and a first outer surface 453a. The first surface 454a is located at the end on the z1 side in the z-direction of the holder 451. The first surface 454a is located in a position that differs in the z-direction from the front resin surface 81. The first outer surface 453a extends in the z-direction and is in contact with the sealing resin 8. The metal pins 452, which form the control terminals 45, project from the front resin surface 81 in the z-direction toward the z1 side. In such a configuration, the control terminals 45 are located, in plan view, in the areas surrounded by the front resin surface 81 (the sealing resin 8). The semiconductor device A13 with such a configuration enables a size reduction in top view.Furthermore, the first surface 454a is located at a position that differs in the z-direction from the front resin surface 81. Such a configuration increases the creepage distance between adjacent control terminals 45 along the surfaces (front resin surface 81, etc.) of the sealing resin 8. Thus, the semiconductor device A13 is suitable for increasing the withstand voltage of adjacent control terminals 45 while simultaneously reducing its size in plan view. The recess end edge 813 of the first recess 810, located on the z2 side in the z-direction, is in contact with the first surface 454a of the first flange section 454. Furthermore, in the first recess 810, the tapered inner surface 815 is connected to the recess end edge 813, and the inner diameter of the tapered inner surface 815 increases in the z-direction towards the z1 side. In such a configuration, when the metal pin 452 is pressed into the holder 451, the metal pin 452, which is advanced into the first recess 810, can be guided from the tapered inner surface 815 towards the holder 451 (towards the tubular section 453). In this embodiment, the recess end edge 813 is also in contact with the radially inner edge of the first surface 454a.In such a configuration, when the metal pin is pressed into the holder 451, the metal pin 452, which is advanced into the first recess 810, can be reliably guided towards the holder 451 (to the tubular section 453). This further facilitates the step of pressing the metal pin 452 into the holder 451. Furthermore, a configuration common to the semiconductor device A1 of the example described above offers the same effects as the example described above. Fourth variant of the first example (First aspect): Fig. 26 shows a semiconductor device according to a fourth variant of the first example. Fig. 26 is an enlarged sectional view corresponding to Fig. 16, showing relevant sections of the semiconductor device A14 of the present variant. The semiconductor device A14 of the present variant differs from the semiconductor device A1 of the example described above in the configuration of the first recesses 810. Each of the first recesses 810 has the recess inner surface 811 and the recess bottom surface 812. In the example shown in Fig. 26, the recess inner surface 811 is inclined such that it forms a tapered shape with an inner diameter that decreases in the z-direction towards the z2 side. The recess bottom surface 812, which is connected to the end on the z2 side in the z-direction of the recess inner surface 811, is a flat surface facing the z1 side in the z-direction. In plan view, the recess bottom surface 812 surrounds the first surface 454a of the holder 451 (of the first flange section 454). In the present embodiment, the recess bottom surface 812 is located in the z-direction relative to the first surface 454a on the z2 side. Therefore, the first surface 454a and the recess floor surface 812 are not flush with each other, but are located in different positions in the z-direction.In the example shown in Fig. 26, the outer circumference of the first flange section 454 is free from the sealing resin 8. In the semiconductor device A14 of the present embodiment, each of the holders 451, which form the control terminals 45, has a first surface 454a and a first outer surface 453a. The first surface 454a is located at the end on the z1 side in the z-direction of the holder 451. The first surface 454a is located in a position that differs in the z-direction from the front resin surface 81. The first outer surface 453a extends in the z-direction and is in contact with the sealing resin 8. The metal pins 452, which form the control terminals 45, project in the z-direction beyond the front resin surface 81 toward the z1 side. In such a configuration, the control terminals 45 are located, in plan view, in the areas surrounded by the front resin surface 81 (the sealing resin 8). The semiconductor device A14 with such a configuration enables a size reduction in top view.Furthermore, the first surface 454a is located at a position that differs in the z-direction from the front resin surface 81. Such a configuration increases the creepage distance between adjacent control terminals 45 along the surfaces (front resin surface 81, etc.) of the sealing resin 8. Thus, the semiconductor device A14 is suitable for increasing the withstand voltage of adjacent control terminals 45 while simultaneously reducing its size in plan view. Moreover, a configuration common to the semiconductor device A1 of the example described above provides the same effects as the example described above. Fifth variant of the first example (First aspect): Fig. 27 shows a semiconductor device according to a fifth embodiment of the first example. Fig. 27 is an enlarged sectional view corresponding to Fig. 16, showing relevant sections of the semiconductor device A15 of the present embodiment. The semiconductor device A15 of the present embodiment further comprises first resin-filled sections 89. In the present embodiment, the first resin-filling sections 89 are placed in the first recesses 810, thus filling them. The resin-filling sections 89 can be made of an epoxy resin, like the sealing resin 8, but can also be made of a different material. This embodiment prevents the ingress of foreign substances (including moisture) into the first recesses 810, which are exposed by the sealing resin 8. The semiconductor device A15 with the configuration described above is advantageous for increasing durability and reliability. Furthermore, the semiconductor device A15 exhibits the same effects as the semiconductor device A1 of the example described above. Second example (First aspect): Figures 28 and 29 show a semiconductor device according to a second example of the present disclosure. Figure 28 is a perspective view showing a semiconductor device A2 of the present embodiment. Figure 29 is an enlarged sectional view corresponding to Figure 16, showing relevant sections of the semiconductor device A2. In the semiconductor device A2 of the present example, the sealing resin 8 does not have the first recesses 810 described above. On the other hand, the semiconductor device A2 has a plurality of first projections 852. The first projections 852 extend in the z-direction from the front resin surface 81 towards the z1 side. The projections 852 are provided corresponding to the control ports 45 and overlap with the control ports 45 in plan view. The metal pins 452 of the control ports 45 extend from the first projections 852. The first projections 852 are columnar. Each first projection 852 covers a portion of the holder 451 of a control port 45. As shown in Fig. 29, the first outer surface 453a of the tubular section 453 and the second surface 454b of the first flanged section 454 of the holder 451 are both in complete contact with the sealing resin 8. In particular, a portion of the first outer surface 453a and the entire second surface 454b are in contact with the first projection 852. In contrast, the first surface 454a of the first flange section 454 is free of the sealing resin 8. The first projection 852 has an upper projection surface 852a. In plan view, the upper projection surface 852a surrounds the first surface 454a of the holder 451 (the first flange section 454). The first surface 454a and the upper projection surface 852a are flush with each other. The first surface 454a, which is flush with the upper projection surface 852a, is located in a different position in the z-direction than the front resin surface 81. In particular, the first surface 454a is located on the z1 side in the z-direction with respect to the front resin surface 81. Next, the effects of the present example will be described. In the semiconductor device A2 of the present example, each of the holders 451, which form the control terminals 45, has a first surface 454a and a first outer surface 453a. The first surface 454a is located at the end on the z1 side in the z-direction of the holder 451. The first surface 454a is located in a position that differs in the z-direction from the front resin surface 81. The first outer surface 453a extends in the z-direction and is in contact with the sealing resin 8. The metal pins 452, which form the control terminals 45, project in the z-direction beyond the front resin surface 81 toward the z1 side. In such a configuration, the control terminals 45 are located in plan view in the areas surrounded by the front resin surface 81 (the sealing resin 8). The semiconductor device A2 with such a configuration enables a size reduction in top view.Furthermore, the first surface 454a is located at a position that differs in the z-direction from the front resin surface 81. Such a configuration increases the creepage distance between adjacent control terminals 45 along the surfaces (front resin surface 81, etc.) of the sealing resin 8. Thus, the semiconductor device A2 is suitable for increasing the withstand voltage of adjacent control terminals 45 while simultaneously reducing its size in plan view. The sealing resin 8 has a first projection 852. The first projection 852 extends in the z-direction from the front resin surface 81 towards the z1 side. The first flange section 454 is located on the z1 side with respect to the front resin surface 81 in the z-direction. The sealing resin 8 with the first projection 852 allows the first surface 454a (the first flange section 454) to be arranged in a suitable position in the z-direction different from the front resin surface 81. The semiconductor device according to the first aspect of this disclosure is not limited to the examples described above. Various design modifications can be freely made to the specific structure of each part of the semiconductor device. The first aspect of this revelation includes examples described in the following clauses 1 to 16. Clause 1. Semiconductor device comprising: at least one terminal having a cylindrical holder with electrical conductivity and a metal pin inserted into the holder; a terminal carrier supporting the holder; and a sealing resin covering part of the holder and the terminal carrier, wherein the sealing resin has a front resin surface facing a first side in the thickness direction, the holder has a first surface located at one end on the first side in the thickness direction, and a first outer surface extending in the thickness direction, the first surface being located at a position different in the thickness direction from the front resin surface, the first outer surface being in contact with the sealing resin, and the metal pin projecting in the thickness direction beyond the front resin surface towards the first side. Clause 2. Semiconductor device according to clause 1, wherein the holder has a tubular section extending in the thickness direction and a first flange section connected to an end on the first side in the thickness direction of the tubular section, the first flange section having the first surface facing the first side in the thickness direction and a second surface located on a second side in the thickness direction relative to the first surface and facing the second side in the thickness direction, the tubular section having the first outer surface and the first outer surface and the second surface being in complete contact with the sealing resin. Clause 3. Semiconductor device according to clause 2, wherein the sealing resin has a first recess which is recessed in the thickness direction from the front resin surface to the second side, the first flange section is located on the second side in the thickness direction relative to the front resin surface and the first recess overlaps with the entire tubular section when viewed in the thickness direction. Clause 4. Semiconductor device according to clause 3, wherein at least part of the first surface is exposed by the sealing resin. Clause 5. Semiconductor device according to clause 4, wherein the first surface is completely exposed from the sealing resin, the first recess has a recess inner surface connected to the front resin surface, and a recess bottom surface connected to an end on the second side in the thickness direction of the recess inner surface and facing the first side in the thickness direction, and the bottom surface of the recess surrounds the first surface when viewed in the thickness direction. Clause 6. Semiconductor device according to clause 3, wherein the first recess has a recess end edge which is located on the second side in the thickness direction and is in contact with the first surface. Clause 7. Semiconductor device according to clause 6, wherein the first recess has a tapered inner surface connected to the recess end edge, and the tapered inner surface is inclined such that an inner diameter thereof increases in the thickness direction towards the first side. Clause 8. Semiconductor device according to clause 6, wherein an outer circumference of the first flange section, viewed in the thickness direction, surrounds the first recess. Clause 9. Semiconductor device according to any one of clauses 3 to 8, wherein a first dimension, which is a distance between the front resin surface and the first surface in the thickness direction, is smaller than a second dimension, which is a length of the holder in the thickness direction. Clause 10. Semiconductor device according to clause 9, wherein the ratio of the first dimension to the second dimension is equal to or greater than 1 / 3. Clause 11. Semiconductor device according to claim 3, further comprising a first resin filling section which is inserted into the first recess. Clause 12. Semiconductor device according to clause 2, wherein the sealing resin has a first projection extending in the thickness direction from the front resin surface to the first side, and part of the first outer surface and the entire second surface are in contact with the first projection. Clause 13. Semiconductor device according to clause 12, wherein the first projection has an upper projection surface facing the first side in the thickness direction, the upper projection surface surrounds the first surface when viewed in the thickness direction, and the first surface and the upper projection surface are flush with each other. Clause 14. Semiconductor device according to clause 1 or 2, further comprising a carrier conductor which carries the terminal carrier and at least one semiconductor element which is electrically connected to the at least one terminal, wherein the at least one semiconductor element is carried on the carrier conductor. Clause 15. Semiconductor device according to clause 14, wherein the at least one terminal is a control terminal for controlling the at least one semiconductor element. Clause 16. Semiconductor device according to clause 15, wherein the carrier conductor has a first conductive section and a second conductive section spaced apart from each other in a first direction orthogonal to the thickness direction, the at least one semiconductor element has a first switching element bonded to the first conductive section and a second switching element bonded to the second conductive section, the control terminal has a first control terminal for controlling the first switching element and a second control terminal for controlling the second switching element, and the terminal carrier has a first carrier section carrying the first control terminal and a second carrier section carrying the second control terminal. Next, a semiconductor device according to a first embodiment of the invention, based on a second aspect of the present disclosure based on Figs. 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43 to 44, is described. The semiconductor device B1 of the present embodiment comprises a substrate 11, a plurality of power terminals 13, a plurality of semiconductor elements 21, a thermistor 22, a first conductive component 31, a second conductive component 32, a plurality of wires, a plurality of control terminals 45, a control terminal carrier 48, and a sealing resin 8. The multiple power connections 13 have one first power connection 14, two second power connections 15 and two third power connections 16.The multitude of wires includes a multitude of first wires 41, a multitude of second wires 42, a multitude of third wires 43 and a fourth wire 44. Fig. 30 is a perspective view of the semiconductor device B1. Fig. 31 is a top view of the semiconductor device B1. Fig. 32 is a top view of the semiconductor device B1, with the sealing resin 50 shown by imaginary lines. Fig. 33 is a top view of the semiconductor device B1, with the sealing resin 50 and the second conductive component 32 omitted from the top view of Fig. 32. Fig. 34 is a top view corresponding to Fig. 33, with the first conductive component 31 omitted. Fig. 35 is a bottom view of the semiconductor device B1. Fig. 36 is a sectional view along line XXXVI-XXXVI shown in Fig. 32. Figs. 37 and 38 are partially enlarged sectional views showing part of Fig. 36. Fig. 39 is a sectional view along line XXXIX-XXXIX shown in Fig. 32. Fig. 40 is a sectional view along the XL-XL line shown in Fig. 32.Figure 41 is a sectional view along line XLI-XLI shown in Figure 32. Figure 42 is a sectional view along line XLII-XLII shown in Figure 32. Figure 43 is a sectional view along line XLIII-XLIII shown in Figure 32. Figure 44 is a partially enlarged sectional view showing part of Figure 40. The following description refers to the thickness direction z, the first direction x, and the second direction y, which are orthogonal to each other. The thickness direction z corresponds to the thickness direction of the semiconductor device B1. Furthermore, "top view" means viewed in the thickness direction z. The first direction x is orthogonal to the thickness direction z. The second direction y is orthogonal to both the thickness direction z and the first direction x. The semiconductor device B1 converts the DC supply voltage applied to the first power terminal 14 and the two second power terminals 15 into AC current by means of the semiconductor elements 21. The converted AC current is fed from the two third power terminals 16 into a power supply destination, such as a motor. As shown in Figures 34, 36 to 39, 41 and 42, the support substrate 11 carries the semiconductor elements 21 in the thickness direction z. For example, a DBC substrate (direct-bonded copper substrate) is provided as the support substrate 11. As shown in Figures 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 to 43, the support substrate 11 has an insulating layer 111, a carrier conductor 112 and a back surface metal layer 113. As shown in Figs. 35, 36, 37, 38, 39, 40, 41, 42 to 43, the support substrate 11 is covered with the sealing resin 50 except for a part of the back surface metal layer 113. As shown in Figures 36, 37, 38, 39, 40, 41, 42 to 43, the insulating layer 111 has a section inserted in the thickness direction z between the carrier conductor 112 and the back surface metal layer 113. The insulating layer 111 is made of a material with relatively high thermal conductivity. For example, the insulating layer 111 is made of a ceramic material containing aluminum nitride (AlN). The insulating layer 111 can also be made of a layer of insulating resin instead of a ceramic material. As shown in Figures 33, 34, and 36 to 43, the carrier conductor 112 is located in the thickness direction z on the top side (z1-side) of the insulating layer 111. The composition of the carrier conductor 112 includes copper (Cu). As shown in Figures 42 and 43, the carrier conductor 112 is surrounded in plan view by the perimeter of the insulating layer 111. As shown in Figures 36, 37, 38, 39, 40, 41, and 42 to 43, the carrier conductor 112 has a front surface 1120. The front surface 1120 is a flat surface facing the z1-side in the thickness direction. As shown in Figures 33, 34 and 36 to 43, the support conductor 112 has a first conductive section 1121 and a second conductive section 1122. The first conductive section 1121 and the second conductive section 1122 are rectangular in plan view.The first conductive section 1121 and the second conductive section 1122 are spaced apart in the first direction x. The first conductive section 1121 is located on the x1 side with respect to the second conductive section 1122 in the first direction x. Each of the semiconductor elements 21 is bonded to either the first conductive section 1121 or the second conductive section 1122. As shown in Figs. 36, 37, 38, 39, 40, 41, 42 to 43, the back surface metal layer 113 is located in the thickness direction z below (on the z2 side of) the insulating layer 111. As shown in Fig. 35, the back surface metal layer 113 is free of the sealing resin 50. A heat dissipation component (e.g., a heat sink) may be attached to the lower surface (the surface facing the z2 side) of the back surface metal layer 113. The composition of the back surface metal layer 113 includes copper. The back surface metal layer 113 is rectangular in plan view. The back surface metal layer 113 is surrounded in plan view by the perimeter of the insulating layer 111. As shown in Figures 34 and 36 to 39, each of the semiconductor elements 21 is mounted on either the first conductive section 1121 or the second conductive section 1122. Each semiconductor element 21 is, for example, a MOSFET (metal-oxide-semiconductor field-effect transistor). Alternatively, each semiconductor element 21 can be a switching element such as an IGBT (insulated-gate bipolar transistor) or a diode. In the description of semiconductor device B1, the semiconductor element 21 is an n-channel MOSFET with a vertical structure. The semiconductor element 21 has a composite semiconductor substrate. The composition of the composite semiconductor substrate includes silicon carbide (SiC) or silicon (Si). As shown in Figures 34 and 36 to 39, the semiconductor elements 21 in the semiconductor device B1 comprise a plurality of first elements 21A and a plurality of second elements 21B. The configuration of each second element 21B is the same as the configuration of each first element 21A. The first elements 21A are mounted on the first conductive section 1121. The first elements 21A are arranged along the second direction y. The second elements 21B are mounted on the second conductive section 1122. The second elements 21B are arranged along the second direction y. Each of the first elements 21A corresponds to the first switching element of the present disclosure. Each of the second elements 21B corresponds to the second switching element of the present disclosure. As shown in Fig. 34, Fig. 37 and Fig. 38, each semiconductor element 21 has a first electrode 211, a second electrode 212, a third electrode 213 and two fourth electrodes 214. As shown in Figs. 37 and 38, the first electrode 211 faces either the first conductive section 1121 or the second conductive section 1122. A current flows through the first electrode 211 that corresponds to the electrical power before conversion by the semiconductor element 21. That is, the first electrode 211 corresponds to the drain electrode of the semiconductor element 21. As shown in Figs. 34, 37 and 38, the second electrode 212 is located in the thickness direction z relative to the first electrode 211. A current flows through the second electrode 212 that corresponds to the electrical power after conversion by the semiconductor element 21. That is, the second electrode 212 corresponds to the source electrode of the semiconductor element 21. As shown in Fig. 34, the third electrode 213 is located on the same side as the second electrode 212 in the thickness direction z. A gate voltage for controlling the semiconductor element 21 is applied to the third electrode 213. That is, the third electrode 213 corresponds to the gate electrode of the semiconductor element 21. As shown in Fig. 34, the area of ​​the third electrode 213 is smaller than the area of ​​the second electrode 212 when viewed from above. As shown in Figures 34, 37, and 38, the two fourth electrodes 214 are located in the thickness direction z on the same side as the second electrode 212 and in the first direction x adjacent to the third electrode 213. In the illustrated example, the two fourth electrodes 214 are arranged in the second direction y on either side of the third electrode 213. The potential of each fourth electrode 214 is equal to the potential of the second electrode 212. The fourth electrode 214 corresponds to a source detection electrode. Unlike the illustrated example, each semiconductor element 21 may have only one of the two fourth electrodes 214 or may have neither of the two fourth electrodes 214. As shown in Figures 37 and 38, a conductive bonding layer 23 is inserted between each of the first conductive section 1121 and the second conductive section 1122 and the first electrode 211 of each of the semiconductor elements 21. The conductive bonding layer 23 is, for example, solder. Alternatively, the conductive bonding layer 23 can comprise sintered metal particles. The first electrodes 211 of the first elements 21A are conductively bonded to the first conductive section 1121 via the conductive bonding layers 23. Thus, the first electrodes 211 of the first elements 21A conduct electricity to the first conductive section 1121. The first electrodes 211 of the second elements 21B are conductively bonded to the second conductive section 1122 via the conductive bonding layers 23. Thus, the first electrodes 211 of the second elements 21B conduct electrically to the second conductive section 1122.Unlike in the present embodiment, the first elements 21A and the second elements 21B can be mounted on a metal component other than a part of a DBC substrate or the like. In such a case, the metal component corresponds to the first conductive section and the second conductive section of the present disclosure. The metal component can be supported on a DBC substrate or the like. Each of the power terminals 13 conducts electrically to the semiconductor elements 21. A current flows in each power terminal 13 that corresponds to the electrical power before conversion by the semiconductor element 21, or a current that corresponds to the electrical power after conversion by the semiconductor element 21. The plurality of power terminals 13 comprises a first power terminal 14, two second power terminals 15, and two third power terminals 16. As shown in Figures 33 and 39, the first power terminal 14 is bonded to the first conductive section 1121. This bonding is not subject to any restrictions and can be achieved using a conductive bonding material (e.g., solder) not shown, by laser welding, or by crimping. The first power terminal 14 conducts electrically via the first conductive section 1121 to the first electrodes 211 of the first elements 21A. The first power terminal 14 is a p-type terminal (positive electrode) to which a DC supply voltage to be converted is applied. As shown in Figure 33, the first power terminal 14 is located opposite the second conductive section 1122, with the first conductive section 1121 inserted between them in the first direction x.The first power terminal 14 extends in the first direction x from the first conductive section 1121 towards the x1 side and protrudes from the sealing resin 50 in the first direction x towards side x1. As shown in Fig. 32, the first power terminal 14 has a section covered with the sealing resin 50 and a section exposed by the sealing resin 50. In the first power terminal 14, the section covered with the sealing resin 50 is bonded to the first conductive section 1121. In the first power terminal 14, the section exposed by the sealing resin 50 is used as the p-type terminal of the semiconductor device B1 described above. The second conductive component 32 is bonded to the two second power terminals 15. The two second power terminals 15 conduct electrically via the second conductive component 32 to the second electrodes 212 of the second elements 21B. The two second power terminals 15 are n-type terminals (negative electrodes) to which a DC supply voltage to be converted is applied. The two second power terminals 15 are spaced apart in the second direction y. The first power terminal 14 is located between the two second power terminals 15. As shown in Fig. 33, the two second power terminals 15 are located on the same side as the first power terminal 14 with respect to the first conductive section 1121 and the second conductive section 1122 in the first direction x.The two second power terminals 15 are spaced apart from the first conductive section 1121 and the second conductive section 1122. The two second power terminals 15 extend in the first direction x and protrude from the sealing resin 50 in the first direction x towards the x1 side. As shown in Fig. 32, each of the two second power terminals 15 has a section covered by the sealing resin 50 and a section exposed by the sealing resin 50. The second conductive component 32 is bonded to the section covered by the sealing resin 50 of each second power terminal 15. In each second power terminal 15, the section exposed by the sealing resin 50 is used as the n-type terminal of the semiconductor device B1 described above. As shown in Figures 33 and 36, the two third power terminals 16 are bonded to the second conductive section 1122. This bonding is not subject to any restrictions and can be achieved using a conductive bonding material (e.g., solder) not shown, by laser welding, or by crimping. The two third power terminals 16 conduct electrically via the second conductive section 1122 to the first electrodes 211 of the second elements 21B. Furthermore, the two third power terminals 16 conduct electrically via the second conductive section 1122 and the first conductive component 31 to the second electrodes 212 of the first elements 21A. Alternating current converted by the semiconductor elements 21 (the first elements 21A and the second elements 21B) is output at the two third power terminals 16. That is, the two third power terminals 16 are output terminals for the alternating current.The two third power terminals 16 are spaced apart in the second direction y. As shown in Fig. 33, the two third power terminals 16 are located opposite the first conductive section 1121, with the second conductive section 1122 inserted between them in the first direction x. The two third power terminals 16 extend in the first direction x from the second conductive section 1122 towards the x2 side and protrude from the sealing resin 50 in the first direction x towards the x2 side. As shown in Fig. 32, each of the two third power terminals 16 has a section covered by the sealing resin 50 and a section exposed by the sealing resin 50. In each of the third power terminals 16, the section covered by the sealing resin 50 is bonded to the second conductive section 1122.In each of the third power terminals 16, the section exposed by the sealing resin 50 is used as the output terminal of the semiconductor device B1 as described above. In the present disclosure, the semiconductor device B1 comprises four first elements 21A and four second elements 21B. However, the number of first elements 21A and the number of second elements 21B are not limited to this configuration and can be changed as required according to the performance requirements of the semiconductor device B1. In the example shown in Fig. 34, four first elements 21A and four second elements 21B are provided. The number of first elements 21A and the number of second elements 21B can be two, three, five, or more. The number of first elements 21A and the number of second elements 21B can be the same or different. The number of first elements 21A and the number of second elements 21B are determined based on the current-carrying capacity of the semiconductor device B1. The semiconductor device B1 can be configured as a half-bridge circuit. In this case, the first 21A elements form the upper branch of the semiconductor device B1, and the second 10B elements form the lower branch. In the upper branch circuit, the first 21A elements are connected in parallel. In the lower branch circuit, the second 21B elements are connected in parallel. Each first 21A element and its corresponding second 21B element are connected in series to form a bridge layer. Each of the control terminals 45 is a pin-type terminal for controlling the first elements 21A and the second elements 21B. The control terminals 45 are, for example, press-fit terminals. The control terminals 45 have a plurality of first control terminals 46A to 46C and a plurality of second control terminals 47A to 47D. The first control terminals 46A to 46C are used, for example, to control the first elements 21A. The second control terminals 47A to 47D are used, for example, to control the second elements 21B. The second control terminals 46A to 46C are spaced apart in the second direction y. As shown in Figs. 34, 39 and 40, the first control terminals 46A to 46C are supported on the first conductive section 1121 via the control terminal carrier 48 (the first carrier section 48A described later). As shown in Figs. 33 and 34, the first control terminals 46A to 46C are located in the first direction x between the first elements 21A and the first power terminal 14 and the two second power terminals 15. The first control terminal 46A is a terminal (a gate terminal) for inputting a control signal for the first elements 21A. A control signal for controlling the first elements 21A is input to the first control terminal 46A (e.g., a gate voltage is applied there). The first control terminal 46B is a terminal (a source detection terminal) for detecting a source signal of the first elements 21A. The voltage applied to the second electrode 212 (the source electrode) of each first element 21A (the voltage corresponding to the source current) is detected at the first control terminal 46B. The first control terminal 45C is a terminal (a drain detection terminal) for detecting a drain voltage of the first elements 21A. The voltage applied to the first electrode 211 (the drain electrode) of each first element 21A (the voltage corresponding to the drain current) is detected at the first control terminal 46C. The second control terminals 47A to 47D are spaced apart in the second direction y. As shown in Figs. 34, 39 and 43, the second control terminals 47A to 47D are supported on the second conductive section 1122 via the control terminal carrier 48 (the second carrier section 48B described later). As shown in Figs. 33 and 34, the second control terminals 47A to 47D are located in the first direction x between the second elements 21B and the two third power terminals 16. The second control terminal 47A is a terminal (a gate terminal) for inputting a control signal for the second elements 21B. A control signal for activating the second elements 21B is input to the second control terminal 47A (e.g., a gate voltage is applied there). The second control terminal 47B is a terminal (a source detection terminal) for detecting a source signal of the second element 21B. The voltage applied to the second electrode 212 (the source electrode) of each second element 21B (the voltage corresponding to the source current) is detected at the second control terminal 47B. The second control terminal 47C and the second control terminal 47D do not conduct electrically to any of the second elements 21B. The second control terminal 47C and the second control terminal 47D are terminals that conduct electrically to a thermistor 22. Each of the control terminals 45 (the first control terminals 46A to 46C and the second control terminals 47A to 47D) has a holder 451 and a metal pin 452. The holders 451 are made of an electrically conductive material. The holders 451 are mounted on the front surface 1120 of the carrier conductor 112 (the carrier substrate 11). As shown in Fig. 44, the holders 451 are bonded to the control terminal carrier 48 (the first metal layer 482 described later) via a conductive bonding material 459. As shown in Fig. 44, each holder 451 has a tubular section 453, a first flanged section 454, and a second flanged section 455. The tubular section 453 extends in the thickness direction z and is, for example, cylindrical. The first flange section 454 is connected to the end on the z1 side in the thickness direction z of the tubular section 453. The first flange section 454 has a first surface 454a. The first surface 454a faces the z1 side in the thickness direction z. The first surface 454a is located at the end on the z1 side in the thickness direction z of the holder 451. Viewed in the thickness direction z, the first surface 454a has the shape of a loop (a circular loop in the illustrated example). The second flange section 455 is connected to the end on the z2 side in the thickness direction z of the tubular section 453. In the present embodiment, the second flange section 455 is bonded to the control connection carrier 48 (the first metal layer 482 described later) via a conductive bonding material 459. A metal pin 452 is inserted into the first flange section 454 and part of the tubular section 453 of each holder 451. The entire holder 451 is exposed to the sealing resin 50. Each metal pin 452 is a rod-shaped component extending in the thickness direction z. The metal pin 452 is supported by a holder 451 by being pressed into the holder 451. The metal pin 452 conducts electrically via the holder 451 and the conductive bonding layer 459 to the control terminal carrier 48 (the first metal layer 482, described later). The metal pin 452 projects in the thickness direction z beyond the upper surface (the front resin surface 51, described later) of the sealing resin 50 towards the z1 side. The control connection carrier 48 carries the control connections 45. The control connection carrier 48 is inserted in the thickness direction z between the front surface 1120 of the first conductive section 1121 or the front surface 1120 of the second conductive section 1122 and the control connections 45. The control terminal carrier 48 has a first carrier section 48A and a second carrier section 48B. The first carrier section 48A is mounted on the first conductive section 1121 and carries the first control terminals 46A to 46C of the control terminals 45. As shown in Fig. 44, the first carrier section 48A is bonded to the first conductive section 1121 via a bonding layer 49. The bonding layer 49 can be electrically conductive or insulating and can, for example, be solder. The second carrier section 48B is mounted on the second conductive section 1122 and carries the second control terminals 47A to 47D of the control terminals 45. As with the first carrier section 48A, the second carrier section 48B is bonded to the second conductive section 1122 via a bonding layer (not shown). The control terminal carrier 48 (each consisting of the first carrier section 48A and the second carrier section 48B) is provided, for example, by a DBC substrate (direct-bonded copper substrate). The control terminal carrier 48 has an insulating layer 481, a first metal layer 482, and a second metal layer 483, which are laminated on top of each other. The insulating layer 481, for example, is made of a ceramic material. The insulating layer 481 is rectangular in plan view. As shown in Fig. 44, the first metal layer 482 is formed on the upper surface of the insulating layer 481. Each control terminal 45 is located on the first metal layer 482. The first metal layer 482 contains, for example, Cu (copper) or a Cu alloy (copper alloy). As shown in Fig. 34, the first metal layer 482 has a first section 482A, a second section 482B, a third section 482C, a fourth section 482D, and a fifth section 482E. The first section 482A, the second section 482B, the third section 482C, the fourth section 482D, and the fifth section 482E are spaced apart from and insulated from each other. The fourth section 482D, to which a plurality of first wires 41 are bonded, conducts electrically via the first wires 41 to the third electrodes 213 (gate electrodes) of the first elements 21A (of the second elements 21B). A plurality of third wires 43 are connected to the fourth section 482D and the first section 482A. Thus, the first section 482A conducts electrically via the third wires 43 and the first wires 41 to the third electrodes 213 (gate electrodes) of the first elements 21A (of the second elements 21B). As shown in Fig. 34, the first control terminal 46A is bonded to the first section 482A of the first support section 48A, and the second control terminal 47A is bonded to the first section 482A of the second support section 48B. The second section 482B, to which a plurality of second wires 42 are bonded, conducts electrically via the second wires 42 to the fourth electrodes 214 (source-sensing electrodes) of the first elements 21A (of the second elements 21B). As shown in Fig. 34, the first control terminal 46B is bonded to the second section 482B of the first support section 48A, and the second control terminal 47B is bonded to the second section 482B of the second support section 48B. The second control terminal 47C is bonded to the third section 482C. In particular, as shown in Fig. 34, the second control terminal 47C is bonded to the third section 482C of the second support section 48B. The first control terminal 46C and the second control terminal 47D are bonded to the fifth section 482E. In particular, the first control terminal 46C is bonded to the fifth section 482E of the first support section 48A. The fifth section 482E of the first support section 48A, to which the fourth wire 44 is bonded, conducts electrically via the fourth wire 44 to the first electrodes 211 (drain electrodes) of the first elements 21A. The second control terminal 47D is bonded to the fifth section 482E of the second support section 48B. Thermistor 22 is conductively bonded across the third section 482C and the fifth section 482E of the second carrier section 48B. Thermistor 22 is, for example, an NTC thermistor (negative temperature coefficient thermistor). An NTC thermistor has the property that its resistance gradually decreases with increasing temperature. Thermistor 22 is used as a temperature detection sensor for semiconductor device B1. Each of the first wires 41, second wires 42, third wires 43, and fourth wire 44 described above is, for example, a bonding wire. The constituent material of the first wires 41, second wires 42, third wires 43, and fourth wire is not subject to any particular restrictions and can, for example, be Au (gold), Al (aluminum), or Cu (copper). The first wires 41, second wires 42, third wires 43, and fourth wire 44 are omitted from Figures 32, 36 to 40, and 43. As shown in Fig. 44, the second metal layer 483 is formed on the lower surface (the surface facing the z2 side in the thickness direction) of the insulating layer 481. As shown in Fig. 44, the second metal layer 483 of the first support section 48A is bonded to the first conductive section 1121 via the bonding layer 49. As with the second metal layer 483 of the first support section 48A, the second metal layer 483 of the second support section 48B is bonded to the second conductive section 1122 via a bonding layer (not shown). As shown in Figures 33 and 36, the first conductive component 31 is conductively bonded to the second electrodes 212 of the first elements 21A and to the second conductive section 1122. Thus, the second electrodes 212 of the first elements 21A conduct electrically to the second conductive section 1122. The composition of the first conductive component 31 is not subject to any particular restrictions and can, for example, include copper. The first conductive component 31 is a metal clamp. As shown in Figures 33 and 36, the first conductive component 31 comprises a main body 311, a plurality of first bonding sections 312, and a plurality of second bonding sections 313. The main body 311 forms the main section of the first conductive component 31. As shown in Fig. 33, the main body 311 extends in the second direction y. As shown in Figs. 33 and 36, the main body 311 spans the gap between the first conductive section 1121 and the second conductive section 1122. As shown in Fig. 33, the main body 311 is formed with a plurality of through holes 310. The through holes 310 penetrate the main body 311 in the thickness direction z. The through-holes 310 overlap in plan view with the gap between the first conductive section 1121 and the second conductive section 1122. This allows the sealing resin 50 to flow downwards from the main body 311 in the thickness direction z (z2-side in thickness direction z) during the formation of the sealing resin 50. As shown in Figures 33 and 36, the first bonding sections 312 are individually bonded to the second electrodes 212 of the first elements 21A. Each of the first bonding sections 312 faces the second electrode 212 of one of the first elements 21A. In a top view, each first bonding section 312 extends from the main body 311 in the first direction x towards the x1 side. In the illustrated example, each first bonding section 312 is forked away from the main body 311, but this is not required. The base end of each first bonding section 312 (the end connected to the main body 311) is bent downwards in the thickness direction z (towards the z2 side). Thus, the outermost end of each first bonding section 312 (the end opposite the side connected to the main body 311) lies deeper in the thickness direction z (on the z2 side in the thickness direction z) than the main body 311. As shown in Figures 33 and 36, the second bonding sections 313 are bonded to the second conductive section 1122. Each of the second bonding sections 313 faces the second conductive section 1122. In a top view, each second bonding section 313 extends from the main body 311 in the first direction x towards the x1 side. The base end of each second bonding section 313 (the end connected to the main body 311) is bent downwards in the thickness direction z (in the thickness direction z towards the z2 side). Thus, the outermost end of each second bonding section 313 (the end opposite the side connected to the main body 311) is lower in the thickness direction z (on the z2 side in the thickness direction z) than the main body 311. As shown in Fig. 37, the semiconductor device B1 further comprises a first conductive bonding layer 33. The first conductive bonding layer 33 is inserted between the second electrodes 212 of the first elements 21A and the first bonding sections 312. The first conductive bonding layer 33 conductively bonds the second electrodes 212 of the first elements 21A and the first bonding sections 312. The first conductive bonding layer 33 is, for example, a solder. Alternatively, the first conductive bonding layer 33 can comprise sintered metal particles. As shown in Fig. 36, the semiconductor device B1 further comprises a second conductive bonding layer 34. The second conductive bonding layer 34 is inserted between the second conductive section 1122 and the second bonding section 313. The second conductive bonding layer 34 conductively bonds the second conductive section 1122 and the second bonding section 313. The second conductive bonding layer 34 is, for example, a solder. Alternatively, the second conductive bonding layer 34 can comprise sintered metal particles. As shown in Fig. 32, the second conductive component 32 is conductively bonded to the second electrodes 212 of the second elements 21B and the two second power terminals 15. Thus, the second electrodes 212 of the second elements 21B conduct electrically to the two second power terminals 15. The composition of the second conductive component 32 is not subject to any particular restrictions and may, for example, include copper. The second conductive component 32 is a metal clamp. As shown in Figs. 32, 36, and 39 to 42, the second conductive component 32 comprises a pair of main bodies 321, a plurality of third bonding sections 322, a pair of fourth bonding sections 324, a plurality of intermediate sections 326, a plurality of lateral beam sections 327, and a pair of floating sections 328. As shown in Fig. 32, the pair of main bodies 321 are spaced apart from each other in the second direction y. The pair of main bodies 321 extends in the first direction x. As shown in Figs. 36 and 40, the pair of main bodies runs parallel to the upper surface of the first conductive section 1121 and to the upper surface of the second conductive section 1122. The pair of main bodies 321 is located farther away from the first conductive section 1121 and the second conductive section 1122 than the main body 311 of the first conductive component 31. As shown in Figs. 32, 41 and 42, the plurality of intermediate sections 326 are spaced apart from each other in the second direction y and are located in the second direction y between the pair of main bodies 321. The intermediate sections 326 extend in the first direction x. As shown in Figs. 32 and 42, the third bonding sections 322 are individually bonded to the second electrodes 212 of the second elements 21B. Each of the third bonding sections 322 faces the second electrode 212 of one of the second elements 21B. In a top view, the third bonding sections 322 extend in the second direction y from the intermediate sections 326. The base end of each third bonding section 322 (the end connected to the intermediate section 326) is bent downwards in the thickness direction z (towards the z2 side in the thickness direction z). Thus, the outermost end of each third bonding section 322 (the end opposite the side connected to the intermediate section 326) is lower in the thickness direction z (on the z2 side in the thickness direction z) than the intermediate section 326. As shown in Figs. 32 and 36, the paired fourth bonding sections 324 are individually bonded to the two second power terminals 15. Each of the fourth bonding sections 324 faces a corresponding second power terminal 15. As shown in Fig. 32, the lateral beam sections 327 are aligned in the second direction y. The lateral beam sections 327 enclose areas that, in plan view, individually overlap with the first bonding sections 312 of the first conductive component 31. As shown in Figs. 32 and 41, of the plurality of lateral beam sections 327, the lateral beam sections 327 located in the middle in the second direction y are connected in the second direction y on each side to an intermediate section 326. Each of the remaining two lateral beam sections 327 is connected in the second direction y on each side to one of the main bodies 321 and one of the intermediate sections 326. As shown in Figs. 32 and 41, the paired floating sections 328 are individually connected to the paired main bodies 321. As shown in Fig. 41, each of the floating sections 328 extends downwards from one of the main bodies 321 in the thickness direction z (in the direction of the z2 side in the thickness direction z). Each of the floating sections 328 is connected to the outer edge in the second direction y of one of the main bodies 321. In the illustrated example, the lower ends of the floating sections 328 (the edges on the z2 side in the thickness direction z) overlap with the first conductive section 1121 when viewed along the second direction y. As shown in Fig. 38, the semiconductor device B1 further comprises a third conductive bonding layer 35. The third conductive bonding layer 35 is inserted between the second electrodes 212 of the second elements 21B and the third bonding sections 322. The third conductive bonding layer 35 conductively bonds the second electrodes 212 of the second elements 21B and the third bonding sections 322. The third conductive bonding layer 35 is, for example, a solder. Alternatively, the third conductive bonding layer 35 can comprise sintered metal particles. As shown in Fig. 36, the semiconductor device B1 further comprises a fourth conductive bonding layer 36. The fourth conductive bonding layer 36 is inserted between the two second power terminals 15 and the pair of fourth bonding sections 324. The fourth conductive bonding layer 36 provides a conductive bond between the two second power terminals 15 and the pair of fourth bonding sections 324. The fourth conductive bonding layer 36 is, for example, a solder compound. Alternatively, the fourth conductive bonding layer 36 can comprise sintered metal particles. As shown in Figures 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 to 43, the sealing resin 50 covers the semiconductor elements 21, the first conductive component 31, the second conductive component 32, the first wires 41, the second wires 42, and the third wires 43. The sealing resin 50 also covers a portion of the substrate 11, the power terminals 13, and the control terminal carrier 48. The sealing resin 50 is electrically insulating. The sealing resin 50 is, for example, black epoxy resin. The sealing resin 50 is formed, for example, by molds. As shown in Figs. 30 to 32 and 35 to 43, the sealing resin 50 has a front resin surface 51, a rear resin surface 52, a plurality of side resin surfaces 531 to 534, a plurality of first recesses 511 and a pair of recesses 531a. As shown in Figures 36 and 39 to 43, the front resin surface 51 faces the same side in the thickness direction z as the upper surface of the first conductive section 1121 (front surface 1120) and the upper surface of the second conductive section 1122 (front surface 1120). The metal pins 452 of the control terminals 45 (the first control terminals 46A to 46C and the second control terminals 47A to 47D) protrude from the front resin surface 51. As shown in Figures 36 and 39 to 43, the rear resin surface 52 faces away from the front resin surface 51 in the third direction z. As shown in Fig. 35, the rear resin surface 52 has a frame shape in top view, which surrounds the lower surface (the surface facing the z2 side in the thickness direction z) of the rear surface metal layer 113 of the support substrate 3.The back surface metal layer 113 of the support substrate 11 is exposed from the back resin surface 52. The lower surface (the surface facing the z2 side in the thickness direction z) of the back surface metal layer 113 can be flush with the back resin surface 52. As shown in Figs. 31, 32, 36, and 39, the lateral resin surfaces 531 and 532 are spaced apart in the first direction x. They face away from each other in the first direction x and extend in the second direction y. The lateral resin surfaces 531 and 532 are connected to the front resin surface 51. The lateral resin surface 531 faces the x1 side in the first direction x, and the lateral resin surface 532 faces the x2 side in the first direction x. The first power connection 14 and the two second power connections 15 project from the lateral resin surface 531. The two third power connections 16 project from the lateral resin surface 532. As shown in Figures 31, 32, and 40 to 43, the lateral resin surfaces 533 and 534 are spaced apart in the second direction y. The lateral resin surfaces 533 and 534 face away from each other in the second direction y and extend in the first direction x. The lateral resin surfaces 533 and 534 are connected to the front resin surface 51 and the rear resin surface 52, respectively. The lateral resin surface 533 faces the y1 side in the second direction y, and the lateral resin surface 534 faces the y2 side in the second direction y. As shown in Figs. 30, 39, 40, 43 and 44, each of the first recesses 511 is cut out from the front resin surface 51 in the thickness direction z towards the z2 side. In the present embodiment, the first recesses 810 are each provided corresponding to the control connections 45. The control connections 45 are arranged corresponding to the first recesses 511. As shown in Figs. 31, 39, 40, 43, and 44, each first recess 511 overlaps in plan view with the entire holder 451 of a control port 45. In the present embodiment, each first recess 511 has a first recess inner surface 512 and a chamfered section 515, as shown in Fig. 44. The first recess inner surface 512 extends in the thickness direction z and is inclined such that it forms a tapered shape with an inner diameter that decreases in the thickness direction z towards the z2 side. As shown in Fig. 44, the first recess inner surface 512 has a first end edge 513 and a second end edge 514. The first end edge 513 is located at the end on the z2 side in the thickness direction z of the first recess inner surface 512 and is in contact with the control connection carrier 48 (of the first metal layer 482). The second end edge 514 is located at the end on the z1 side in the thickness direction z of the first recess inner surface 512. The second end edge 514 surrounds the first end edge 513 in a top view. The chamfered section 515 is connected to the front resin surface 51 and inserted between the front resin surface 51 and the first recess inner surface 512. The specific shape of the chamfered section 515 is not subject to any particular restrictions and can, for example, have an R-shape (rounded shape) or a C-shape (beveled shape). In the illustrated example, the chamfered section 515 has an R-shape (rounded shape). The first recess 810, which has such a configuration, is a trace of the forming of the sealing resin 8 by molding, while the control terminal carrier 48 is pressed, for example, with a pin or the like having a shape corresponding to the first recess 511. Fig. 45 is a sectional view corresponding to Fig. 44, illustrating a step of the method for manufacturing the semiconductor device B1. As shown in Fig. 45, the mold 91 used for forming is provided, for example, with a cylindrical tubular pin 911. While the holder 451 is positioned inside the tubular pin 911 and the lower end (the end on the z2 side in the thickness direction z) of the tubular pin 911 is pressed against the control terminal carrier 48 (the first metal layer 482), the flowable resin material is injected into the cavity 919 of the mold 91. As can be seen in Fig. 44 and Fig.As shown in Fig. 45, the first recess inner surface 512 of the first recess 511 has a draft angle that corresponds to the outer circumferential surface of the tubular pin 911. As shown in Fig. 45, the root of the tubular pin 911 of the mold 91 has a rounded section 915. The chamfered section 515 of the first recess 511 has a shape that corresponds to the rounded section 915 of the mold 91. After the sealing resin 50 has been formed by the molding process using the mold 91, the holder 451 located inside the tubular pin 911 is completely free of the sealing resin 50. Depending on the arrangement of the control terminal holder 451, the lower end of the tubular pin 911 shown in 45 can be pressed against the area spanning the first metal layer 482 and the insulating layer 481 during the forming process. On the insulating layer 481, a step is present in the thickness direction z at the boundary between the section where the first metal layer 482 is formed and the section where the first metal layer 482 is not formed. Therefore, when the lower end of the tubular pin 911 is pressed against the area spanning the first metal layer 482 and the insulating layer 481, a gap can form between the lower end of the tubular pin 911 and the control terminal holder 48 (of the insulating layer 481).In such a case, for example, a resist layer can be formed on the section of the upper surface of the insulating layer 481 where the first metal layer 482 is not formed, in order to eliminate the step described above between the section where the first metal layer 482 is formed and the section where the first metal layer 482 is not formed on the insulating layer 481. The lower end of the tubular pin 911 can be made of a damping material. In this case, when the tubular pin 911 is pressed against the control terminal carrier 48, the damping material can absorb the step described above and thereby prevent a gap from forming between the lower end of the tubular pin 911 and the control terminal carrier 48 (the insulating layer 481). The method for forming the first recess 511 is not limited to the method described with reference to Fig. 45. For example, the sealing resin 50 can be formed by molding while the control connector carrier 48 is pressed with a column-shaped fixed pin that corresponds to the first recess 511. In this case, the holder 451 is not in place on the control connector carrier 48 during molding. After molding, the holder 451 is positioned within the first recess 511 on the control connector carrier 48. In the illustrated example, the first surface 454a of the holder 451 (first flange section 454) is located in the thickness direction z with respect to the front resin surface 51 on the z2 side. Thus, the entire holder 451 is accommodated in the first recess 511. As shown in Fig. 31, the pair of recesses 531a is recessed in the first direction x from the lateral resin surface 531 towards the x2 side. The recesses 531a extend in the thickness direction z from the front resin surface 51 to the rear resin surface 52. The recesses 531a are located in the second direction y on each side of the first power connection 14. Next, the effects of the present embodiment will be described. Each of the holders 451, which form the control terminals 45, is mounted on the front surface 1120 of the carrier conductor 112 (carrier substrate 11). The metal pins 452, which form the control terminals 45, project in the thickness direction z beyond the front resin surface 51 towards the z1 side. In such a configuration, the control terminals 45 are located, in plan view, in the areas surrounded by the front resin surface 51 (the sealing resin 50). The semiconductor device B1 with such a configuration enables a reduction in size in plan view. The holder 451 of each control port 45 is completely free of the sealing resin 50. This configuration prevents the sealing resin 50 from flowing into the holder 451, into which the metal pin 452 is to be inserted. Therefore, the semiconductor device B1 can properly maintain the electrical conductivity of the holder 451 and the metal pin 452, allowing the control port 45, which includes the holder 451 and the metal pin 452, to function correctly. The control terminals 45 are arranged in the first recesses 511 of the sealing resin 50. In the present embodiment, the sealing resin 50 has a plurality of first recesses 511, and the plurality of control terminals 45 are each arranged corresponding to the plurality of first recesses 511. Each first recess 511 (the first recess inner surface 512) has a first end edge 513 that is in contact with the control terminal carrier 48 (the first metal layer 482). Such a configuration increases the creepage distance between adjacent control terminals 45 along the surfaces (the front resin surface 51, the first recess inner surface 512 of the first recess 511, etc.) of the sealing resin 50. Thus, the semiconductor device B1 is suitable for increasing the withstand voltage of adjacent control terminals 45 while simultaneously reducing its size in plan view. Each first recess 511 overlaps the entire holder 451 of a control connection 45 in plan view. In such a configuration, the holder 451 surrounded by the first recess 511 is clearly visible in plan view. This facilitates the step of pressing the metal pin 452 into the holder 451. Variants of the semiconductor device according to the second aspect of the present disclosure are described below. Different parts of the variants can be selectively used in any suitable combination, as long as this is technically compatible. Figures 46 and 48 show a semiconductor device according to a first variant of the first embodiment of the second aspect. Figure 46 is a top view of semiconductor device B11 of the present variant. Figure 47 is a sectional view along line XLVII-XLVII shown in Figure 46. Figure 48 is a sectional view along line XLVIII-XLVIII shown in Figure 46. In Figure 46 and the following drawings, the elements that are identical or similar to those of semiconductor device B1 of the embodiment described above are designated by the same reference numerals as those used for the embodiment described above, and their descriptions are omitted. The semiconductor device B11 of the present variant differs from the semiconductor device B1 of the embodiment described above in the configuration of the first recesses 511 of the sealing resin 50. As shown in Figures 46, 47 to 48, the sealing resin 50 in the semiconductor device B11 has two first recesses 511. The first of the two first recesses 511 corresponds to a plurality of control terminals 45 (the first control terminals 46A to 46C), and these control terminals 45 (the first control terminals 46A to 46C) are arranged in the first of the first recesses 511. The first of the first recesses 511 overlaps, in plan view, with the entire holder 451 of each of these control terminals 45 (the first control terminals 46A to 46C).The second of the first two recesses 511 corresponds to a plurality of control ports 45 (the second control ports 47A to 47D), and these control ports 45 (the second control ports 47A to 47D) are arranged in the second of the first recesses 511. In plan view, the second of the first recesses 511 overlaps the entire holder 451 of each of these control ports 45 (the second control ports 47A to 47D). In the semiconductor device B11 of the present variant, each of the holders 451, which form the control terminals 45, is mounted on the front surface 1120 of the carrier conductor 112 (carrier substrate 11). The metal pins 452, which form the control terminals 45, project in the thickness direction z beyond the front resin surface 51 towards the z1 side. In such a configuration, the control terminals 45 are located in plan view within the areas surrounded by the front resin surface 51 (the sealing resin 50). The semiconductor device B1 with such a configuration enables a reduction in size in plan view. The holder 451 of each control port 45 is completely free of the sealing resin 50. This configuration prevents the sealing resin 50 from flowing into the holder 451, into which the metal pin 452 is to be inserted. Therefore, the semiconductor device B11 can properly maintain the electrical conductivity of the holder 451 and the metal pin 452, allowing the control port 45, which includes the holder 451 and the metal pin 452, to function correctly. The control terminals 45 are located in the first recesses 511 of the sealing resin 50. In semiconductor device B11, the sealing resin 50 has two first recesses 511. A plurality of control terminals 45 (the first control terminals 46A to 46C) are located in one of the first recesses 511, and a plurality of control terminals 45 (the second control terminals 47A to 47D) are located in the other first recess 511. In the configuration where a plurality of control terminals 45 are located together in one first recess 511, the sealing resin 50 can be formed relatively easily by molding. Fig. 49 shows a semiconductor device according to a second variant of the first embodiment of the second aspect. Fig. 49 is a sectional view corresponding to Fig. 40, which shows the semiconductor device B12 of the present variant. The semiconductor device B12 of the present variant further comprises first resin parts 55 and differs from the semiconductor device B1 of the embodiment described above in that the first resin parts 55 are enclosed. Each of the first resin parts 55 fills at least a portion of a first recess 511 and is in contact with at least a portion of a holder 451. In semiconductor device B12, the first resin part 55 is placed in each first recess 511 to fill it. The first resin part 55 covers the entire holder 451 located in the first recess 511. The constituent material of the first resin part 55 is not subject to any particular restrictions. The first resin part 55 may be made of the same material as the sealing resin 50 or of a different material. In semiconductor device B12, the constituent material of the first resin part 55 differs, for example, from the constituent material of the sealing resin 50. In semiconductor device B12, the elastic modulus of the first resin part 55 is, for example, smaller than that of the sealing resin 50.The constituent material of the first resin part 55 is not subject to any special restrictions in the case where the elastic modulus of the first resin part 55 is smaller than that of the sealing resin 50, but can be, for example, silicone resin or silicone gel. In the semiconductor device B12 of the present variant, each of the holders 451, which form the control terminals 45, is mounted on the front surface 1120 of the carrier conductor 112 (carrier substrate 11). The metal pins 452, which form the control terminals 45, project in the thickness direction z beyond the front resin surface 51 towards the z1 side. In such a configuration, the control terminals 45 are located in plan view within the areas surrounded by the front resin surface 51 (the sealing resin 50). The semiconductor device B1 with such a configuration enables a reduction in size in plan view. The holder 451 of each control port 45 is completely free of the sealing resin 50. This configuration prevents the sealing resin 50 from flowing into the holder 451, into which the metal pin 452 is to be inserted. Therefore, the semiconductor device B12 can properly maintain the electrical conductivity of the holder 451 and the metal pin 452, allowing the control port 45, which includes the holder 451 and the metal pin 452, to function correctly. In semiconductor device B12, the first resin part 55 is placed in each first recess 511 to fill it. The first resin part 55 covers the holder 451 located in the first recess 511. The elastic modulus of the first resin part 55 is lower than that of the sealing resin 50. This configuration reduces the stress around the holder 451 covered by the first resin part 55. Furthermore, providing the first resin parts 55 in semiconductor device B12 prevents the ingress of foreign substances (including moisture) into the first recesses 511 exposed by the sealing resin 50. Semiconductor device B12 with the configuration described above is advantageous for increasing durability and reliability.Furthermore, the semiconductor device B12 has a configuration in common with the semiconductor device B1 of the embodiment described above and thus offers the same effects as the embodiment described above. Fig. 50 shows a semiconductor device according to a third variant of the first embodiment of the second aspect. Fig. 50 is a sectional view corresponding to Fig. 47, which shows the semiconductor device B13 of the present variant. The semiconductor device B13 of the present variant further comprises first resin parts 55 and differs from the semiconductor device B11 of the variant described above in that the first resin parts 55 are enclosed. Each of the first resin parts 55 fills at least a portion of a first recess 511 and is in contact with at least a portion of each holder 451. In semiconductor device B13, the first resin part 55 fills a portion of the first recess 511. The first resin part 55 covers a portion of each of the holders 451 that are arranged in the first recess 511. The constituent material of the first resin part 55 is not subject to any particular restrictions. The first resin part 55 may be made of the same material as the sealing resin 50 or it may be made of a different material. In semiconductor device B13, for example, the constituent material of the first resin part 55 differs from the constituent material of the sealing resin 50. In semiconductor device B13, for example, the elastic modulus of the first resin part 55 is greater than that of the sealing resin 50.The constituent material of the first resin part 55 is not subject to any special restrictions in the case where the elastic modulus of the first resin part 55 is greater than that of the sealing resin 50, but can, for example, be an epoxy-based potting material. In the semiconductor device B13 of the present variant, each of the holders 451, which form the control terminals 45, is mounted on the front surface 1120 of the carrier conductor 112 (carrier substrate 11). The metal pins 452, which form the control terminals 45, project in the thickness direction z beyond the front resin surface 51 towards the z1 side. In such a configuration, the control terminals 45 are located in plan view within the areas surrounded by the front resin surface 51 (the sealing resin 50). The semiconductor device B13 with such a configuration enables a reduction in size in plan view. The holder 451 of each control port 45 is completely free of the sealing resin 50. This configuration prevents the sealing resin 50 from flowing into the holder 451, into which the metal pin 452 is to be inserted. Therefore, the semiconductor device B13 can properly maintain the electrical conductivity of the holder 451 and the metal pin 452, allowing the control port 45, which includes the holder 451 and the metal pin 452, to function correctly. In semiconductor device B13, the first resin part 55 is inserted into each first recess 511. The first resin part 55 covers at least a portion of each holder 451 located in the first recess 511. The elastic modulus of the first resin part 55 is greater than that of the sealing resin 50. This configuration improves the impact resistance of the holders 451 covered by the first resin part 55. Semiconductor device B13 with the configuration described above is advantageous for increasing performance. Furthermore, semiconductor device B13 exhibits the same effects as semiconductor device B11 of the variant described above. Fig. 51 shows a semiconductor device according to a fourth variant of the first embodiment of the second aspect. Fig. 51 is a sectional view corresponding to Fig. 40, which shows the semiconductor device B14 of the present variant. The semiconductor device B14 of the present variant further comprises first resin parts 55. In the semiconductor device B14, the dimension of the sealing resin 50 in the thickness direction z is smaller than that of the semiconductor device B1 of the embodiment described above. Accordingly, the dimension of each first recess 511 in the thickness direction z is also smaller than that of the semiconductor device B1. Furthermore, the holder 451 of each control connection 45 projects in the thickness direction z beyond the front resin surface 51 of the sealing resin 50 towards the zl side.The first surface 454a of the holder 451 (first flange section 454) is located in the thickness direction z with respect to the front resin surface 51 on the zl side. Thus, part of the holder 451 is accommodated in the first recess 511. Each of the first resin parts 55 fills at least a portion of a first recess 511 and is in contact with at least a portion of a holder 451. In semiconductor device B14, the first resin part 55 is placed in each first recess 511 to fill the first recess 511. The constituent material of the first resin part 55 is not subject to any particular restrictions. The first resin part 55 can be made of the same material as the sealing resin 50 or it can be made of a different material. For example, in semiconductor device B14, the constituent material of the first resin part 55 differs from the constituent material of the sealing resin 50. For example, in semiconductor device B14, the elastic modulus of the first resin part 55 is lower than that of the sealing resin 50.The constituent material of the first resin part 55 is not subject to any special restrictions in the case where the elastic modulus of the first resin part 55 is smaller than that of the sealing resin 50, but can be silicone resin or silicone gel. In semiconductor device B14, each first resin part 55 has a section located on the z1 side in the thickness direction z relative to the front resin surface 51. This section of the first resin part 55 located on the z1 side in the thickness direction z relative to the front resin surface 51 is the section that has been raised along the outer circumferential surface of the holder 451 (tubular section 453) in the thickness direction z towards the z1 side, for example, due to the surface tension of the first resin part 55. In the illustrated example, the first surface 454a of the holder 451 (the first flange section 454) is exposed by the first resin part 55. In the semiconductor device B14 of the present variant, each of the holders 451, which form the control terminals 45, is mounted on the front surface 1120 of the carrier conductor 112 (carrier substrate 11). The metal pins 452, which form the control terminals 45, project in the thickness direction z beyond the front resin surface 51 towards the z1 side. In such a configuration, the control terminals 45 are located in plan view within the areas surrounded by the front resin surface 51 (the sealing resin 50). The semiconductor device B14 with such a configuration enables a reduction in size in plan view. The holder 451 of each control port 45 is completely free of the sealing resin 50. This configuration prevents the sealing resin 50 from flowing into the holder 451, into which the metal pin 452 is to be inserted. Therefore, the semiconductor device B14 can properly maintain the electrical conductivity of the holder 451 and the metal pin 452, allowing the control port 45, which includes the holder 451 and the metal pin 452, to function correctly. In semiconductor device B14, the first resin part 55 is inserted into each first recess 511. The first resin part 55 covers the holder 451, which is positioned in the first recess 511. The elastic modulus of the first resin part 55 is lower than that of the sealing resin 50. This configuration reduces the stress around the holder 451 covered by the first resin part 55. In semiconductor device B14, the first surface 454a of each holder 451 is exposed by the first resin part 55. This makes it possible to press the metal pin 452 into the holder 451 after the first resin part 55 has been inserted into the first recess 511. The pressing-in step of the metal pin 452 into the holder 451 is also stabilized. Furthermore, the semiconductor device B14 has a configuration in common with the semiconductor device B1 of the embodiment described above and thus offers the same effects as the embodiment described above. Figures 52 and 53 show a semiconductor device according to a fifth variant of the first embodiment of the second aspect. Figure 52 is a top view of the semiconductor device B15 of the present variant. Figure 53 is a sectional view along line LIII-LIII shown in Figure 52. In the semiconductor device B15 of the present variant, the sealing resin 50 has a plurality of second recesses 517. The semiconductor device B15 differs from the semiconductor device B1 of the embodiment described above in that the sealing resin 50 has the second recesses 517. The second recesses 517 are cut out in the thickness direction z from the front resin surface 51 to the z2 side. In the semiconductor device B15, the sealing resin 50 has a plurality of second recesses 517. Each of the second recesses 517 is provided corresponding to one of the first recesses 511. As shown in Fig. 52, each second recess 517 surrounds a corresponding first recess 511 in a top view. In the illustrated example, the second recess 517 has the shape of a circular loop in a top view. As shown in Fig. 53, every second recess 517 has a second recess bottom surface 518. The second recess bottom surface 518 is located at the end on the z2 side in the thickness direction z of the second recess 517. The second recess bottom surface 518 is spaced from the control connection carrier 48 in the thickness direction z towards the z1 side. In the semiconductor device B15 of the present variant, each of the holders 451, which form the control terminals 45, is mounted on the front surface 1120 of the carrier conductor 112 (carrier substrate 11). The metal pins 452, which form the control terminals 45, project in the thickness direction z beyond the front resin surface 51 towards the zl side. In such a configuration, the control terminals 45 are located in plan view within the areas surrounded by the front resin surface 51 (the sealing resin 50). The semiconductor device B15 with such a configuration enables a reduction in size in plan view. The holder 451 of each control port 45 is completely free of the sealing resin 50. This configuration prevents the sealing resin 50 from flowing into the holder 451, into which the metal pin 452 is to be inserted. Therefore, the semiconductor device B15 can properly maintain the electrical conductivity of the holder 451 and the metal pin 452, allowing the control port 45, which includes the holder 451 and the metal pin 452, to function correctly. In semiconductor device B15, the sealing resin 50 has a second recess 517. The second recess 517 surrounds the first recess 511 in plan view. The end on the z2 side in the thickness direction z of the second recess 517 (the second recess bottom surface 518) is spaced from the control terminal carrier 48 in the thickness direction towards the zl side. This configuration increases the creepage distance between the control terminal 45, which is surrounded in plan view by the second recess 517, and an adjacent control terminal 45 along the surfaces (the front resin surface 51, the first recess inner surface 512 of the first recess 511, the second recess 517, etc.) of the sealing resin 50. Thus, semiconductor device B15 can increase the withstand voltage of adjacent control terminals 45 while simultaneously reducing its size in plan view.Furthermore, the semiconductor device B15 has a configuration in common with the semiconductor device B1 of the embodiment described above and thus offers the same effects as the embodiment described above. The semiconductor device according to the present disclosure is not limited to the embodiments described above. According to the present disclosure, various design modifications can be freely made to the specific structure of each part of the semiconductor device. Although the foregoing embodiments and variants describe the case in which all holders 451 of the control ports 45 are exposed by the sealing resin 50, the present disclosure is not limited to such a case. For example, the holders 451 of some of the control ports 45 may be covered with the sealing resin 50. The second aspect of this disclosure exhibits the configurations described in the following clauses 1B to 17B. Clause 1B. Semiconductor device comprising: a support substrate having a front surface facing a first side in the thickness direction; at least one terminal having a holder with electrical conductivity provided on the front surface and a metal pin inserted into the holder; and a sealing resin having a front resin surface facing the first side in the thickness direction and covering at least a part of the support substrate, wherein the holder of at least one of the at least one terminals is completely exposed by the sealing resin and the metal pin projects in the thickness direction beyond the front resin surface towards the first side. Clause 2B. Semiconductor device according to clause 1B, further comprising a terminal carrier which is inserted in the thickness direction between the substrate and the at least one terminal, wherein the holder is supported on the terminal carrier. Clause 3B. Semiconductor device according to clause 2B, wherein the sealing resin covers part of the terminal carrier. Clause 4B. Semiconductor device according to clause 3B, comprising a plurality of such connections, wherein the sealing resin has at least one first recess which is recessed in the thickness direction from the front resin surface to a second side, the at least one first recess having a first end edge which is in contact with the connection carrier, and the plurality of connections are arranged in the at least one first recess. Clause 5B. Semiconductor device according to clause 4B, comprising a plurality of such first recesses, wherein the plurality of terminals are each arranged according to the plurality of first recesses, each of the plurality of first recesses overlapping in the thickness direction with the entire holder of a corresponding terminal. Clause 6B. Semiconductor device according to clause 4B, wherein the first recess overlaps with the totality of the holders of the plurality of connections. Clause 7B. Semiconductor device according to clause 5B or 6B, further comprising a first resin part which fills at least a part of the first recess, wherein the first resin part is in contact with at least a part of the holder. Clause 8B. Semiconductor device according to clause 7B, wherein a constituent material of the first resin part differs from a constituent material of the sealing resin and an elastic modulus of the first resin part is smaller than an elastic modulus of the sealing resin. Clause 9B. Semiconductor device according to clause 7B, wherein a constituent material of the first resin part differs from a constituent material of the sealing resin and an elastic modulus of the first resin part is greater than an elastic modulus of the sealing resin. Clause 10B. Semiconductor device according to any one of clauses 4B to 9B wherein the sealing resin has a second recess which is recessed in the thickness direction from the front resin surface to the second side, and the second recess, viewed in the thickness direction, surrounds the first recess. Clause 11B. Semiconductor device according to clause 10B, wherein the second recess has a second recess bottom surface located in the thickness direction at one end on the second side, and the second recess bottom surface is spaced in the thickness direction from the terminal carrier to the first side. Clause 12B. Semiconductor device according to one of clauses 4B to 11B (or one of clauses 4B to 6B), wherein the at least one first recess has a first recess inner surface, the first recess inner surface has a first end edge located in the thickness direction at one end on the second side, and a second end edge located in the thickness direction at one end on the first side, and the second end edge, viewed in the thickness direction, surrounds the first end edge. Clause 13B. Semiconductor device according to clause 12B, wherein the at least one first recess has a chamfered section provided between the front resin surface and the first recess inner surface. Clause 14B. Semiconductor device according to one of clauses 1B to 13B (or one of clauses 1B to 6B), wherein the holder has a first surface located at one end on the first side in the thickness direction, and the first surface is located on the second side in the thickness direction relative to the front resin surface. Clause 15B. Semiconductor device according to one of clauses 2B to 13B (or one of clauses 2B to 6B), further comprising at least one semiconductor element which is arranged on the front surface and electrically connected to the at least one terminal. Clause 16B. Semiconductor device according to clause 15B, wherein the at least one terminal is a control terminal for controlling the at least one semiconductor element. Clause 17B. Semiconductor device according to clause 16B, wherein the support substrate has a first conductive section and a second conductive section spaced apart from each other in a first direction orthogonal to the thickness direction, the at least one semiconductor element has a first switching element bonded to the first conductive section and a second switching element bonded to the second conductive section, the control terminal has a first control terminal for controlling the first switching element and a second control terminal for controlling the second switching element, and the terminal carrier has a first carrier section carrying the first control terminal and a second carrier section carrying the second control terminal. REFERENCE MARK (Reference symbol for the first aspect) A1, A11, A12, A13, A14, A15, A2: Semiconductor device 10A: First semiconductor element 10B: Second semiconductor element 101: Front element surface 102: Rear element surface 11: First front surface electrode 12: Second front surface electrode 121: Gate finger 13: Third front surface electrode 15: Rear surface electrode 17: Thermistor 19: Conductive bonding material 3: Support substrate 301: Support surface 302: Bottom surface 31: Insulating layer 32: Carrier conductor 32A: First conductive section 32B: Second conductive section 321: First bonding layer 33: Rear surface metal layer 41: First terminal 42: Second terminal 43: Third terminal 44: Fourth terminal 45: Control terminal 451: Holder 452: Metal pin 453: Tubular section 453a: First outer surface 453b: First inner surface 454: First flanged section 454a: First surface 454b: Second surface 455: Second flanged section 459: ConductiveBonding material 46A, 46B, 46C, 46D, 46E: First control terminal 47A, 47B, 47C, 47D: Second control terminal 48: Control terminal carrier (terminal carrier) 48A: First carrier section 48B: Second carrier section 481: Insulating layer 482: First metal layer 482A: First section 482B: Second section 482C: Third section 482D: Fourth section 482E: Fifth section 482F: Sixth section 483: Second metal layer 49: Bonding material 5: First conductive component 51: Main section 514: First opening 52: First bonding section 53: Second bonding section 59: Conductive bonding material 6: Second conductive component 602: First stepped section 603: Second Stepped section 61: Third bonding section 611: Flat section 612: First inclined section 64: First path section 641: First strip section 643: First extension section 649: Recess 65: Second path section 651: Second strip section 653: Second extension section 659: Recess 66:Third path section 669: Recess 67: Fourth path section 69: Conductive bonding material 71: 72, 73, 74: Wire 8: Sealing resin 81: Front resin surface 810: First recess 811: Recess inner surface 812: Recess bottom surface 813: Recess end edge 814: Cylindrical inner surface 815: Tapered inner surface 82: Rear resin surface 831, 832: Side resin surface 832a: Recess 833, 834: Side resin surface 851: Projection 851a: Projection end surface 851b: Recess 851c: Inner wall surface 852: First projection 852a: Top projection surface 89: First resin fill section L1: First dimension L2: Second dimension (Reference symbol for the second aspect) B1, B11, B12, B13, B14, B15: Semiconductor device 11: Substrate 111: Insulating layer 112: Carrier conductor 1120: Front surface 1121: First conductive section 1122: Second conductive section 113: Back surface metal layer 13: Power terminal 14: First power terminal 15: Second power terminal 16: Third power terminal 21: Semiconductor element 21A: First element (First switching element) 218: Second element (Second switching element) 211: First electrode 212: Second electrode 213: Third electrode 214: Fourth electrode 22: Thermistor 23: Conductive bonding layer 31: First conductive component 310: Through hole 311: Main body 312: First bonding section 313: Second bonding section 32: Second conductive component 321: Main body 322: Third bonding section 324: Fourth bonding section 326: Intermediate section 327: Side beam section 328: Floating section 33: First conductive bonding layer 34: Second conductive bonding layer 35: ThirdConductive bonding layer 36: Fourth conductive bonding layer 41: First wire 42: Second wire 43: Third wire 44: Fourth wire 45: Control terminal (terminal) 451: Holder 452: Metal pin 453: Tubular section 454: First flange section 454a: First surface 455: Second flange section 459: Conductive bonding layer 46A, 46B, 46C: First control terminal 47A, 47B, 47C, 47D: Second control terminal 48: Control terminal carrier (terminal carrier) 48A: First carrier section 48B: Second carrier section 481: Insulating layer 482: First metal layer 482A: First section 482B: Second section 482C: Third section 482D: Fourth section 482E: Fifth section 483: Second metal layer 49: Bonding layer 50: Sealing resin 51: Front resin surface 511: First recess 512: First recess inner surface 513: First edge 514: Second edge 515: Beveled section 517: Second recess 518: Second recess bottom surface 52: Rear resin surface 531:532, 533, 534: Lateral resin surface 531a: Recess 55: First resin part 91: Shape 911: Tubular pin 915: Rounded section 919: Cavity

Claims

Semiconductor device (B1) comprising: a substrate (11) having an insulating layer (111), a carrier conductor (112) and a back surface metal layer (113), wherein the carrier conductor (112) has a front surface (1120) facing one side (z1) of a thickness direction (z); at least one semiconductor element (21) arranged on the front surface (1120); at least one control terminal (45) for controlling the at least one semiconductor element (21); a control terminal carrier (48) arranged between the substrate (11) and the at least one control terminal (45) in the thickness direction (z) to support the control terminal (45); and a sealing resin (50) with a front resin surface (51) facing one side (z1) of the thickness direction (z), wherein the sealing resin (50) covers at least a part of the support substrate (11),wherein the control connection (45) has an electrically conductive cylindrical holder (451) and a metal pin (452) inserted into the holder (451), wherein the control connection (45) projects in the direction of one side (z1) of the thickness direction (z) with respect to the front resin surface (51), the sealing resin (50) is formed with at least one first recess (511) which is recessed in the direction of an opposite side (z2) of the thickness direction (z) from the front resin surface (51), the at least one first recess (511) having a first recess inner surface (512) which has a first end edge (513) which is held in contact with the control connection carrier (48), and the control connection (45) is arranged in the at least one first recess (511) such that the control connection (45) is completely exposed by the sealing resin (50),wherein the semiconductor device (B1) further comprises: a first power terminal (14) and at least one second power terminal (15) arranged on one side (x1) of a first direction (x) relative to the support substrate (11), the first direction (x) being perpendicular to the thickness direction (z); and at least one third power terminal (16) arranged on an opposite side (x2) of the first direction (x) relative to the support substrate (11), wherein the first power terminal (14) and the at least one second power terminal (15) each have a section covered by the sealing resin (50) and another section exposed by the sealing resin (50), and the at least one third power terminal (16) has a section covered by the sealing resin (50) and another section exposed by the sealing resin (50). Semiconductor device (B1) according to claim 1, wherein the holder (451) has a tubular section (453) extending in the thickness direction (z), a first flange section (454) connected to an end of the tubular section (453) on one side (z1) of the thickness direction (z), and a second flange section (455) connected to an end of the tubular section (453) on the opposite side (z2) of the thickness direction (z), and the holder (451) is completely exposed from the sealing resin (50). Semiconductor device (B1) according to claim 2, wherein the first recess (511) overlaps the holder (451) in its entirety when viewed in the thickness direction (z). Semiconductor device (B1) according to claim 2, wherein the at least one control terminal (45) has a plurality of control terminals (45) and the at least one first recess (511) has a plurality of first recesses (511), the plurality of control terminals (45) are each positioned according to the plurality of first recesses (511), each of the plurality of first recesses (511), viewed in the thickness direction (z), overlaps the holder (451) of a corresponding plurality of control terminals (45) in its entirety. Semiconductor device (B1) according to claim 1, wherein the first recess inner surface (512) is inclined in the thickness direction (z) such that its inner diameter decreases towards the opposite side (z2) of the thickness direction (z). Semiconductor device (B1) according to claim 1, wherein the first recess inner surface (512) has a first end edge (513) arranged on the opposite side (z2) of the thickness direction (z) and a second end edge (514) arranged on one side (z1) of the thickness direction (z), wherein the second end edge (514) surrounds the first end edge (513) viewed in the thickness direction (z). Semiconductor device (B1) according to claim 1, wherein the at least one first recess (511) has a chamfered section (515) which is provided between the front resin surface (51) and the first recess inner surface (512). Semiconductor device (B1) according to claim 1, wherein the control connection (45) is a pin-shaped connection for controlling the operation of the semiconductor element (21). Semiconductor device (B1) according to claim 1, wherein the at least one control terminal (45) has a plurality of control terminals (45) and the at least one first recess (511) has a plurality of first recesses (511), and the plurality of control terminals (45) are each positioned according to the plurality of first recesses (511). Semiconductor device (B1) according to claim 1, wherein the at least one control terminal (45) has a plurality of control terminals (45), and the plurality of control terminals (45) are arranged in the at least one first recess (511). Semiconductor device (B1) according to one of claims 1 to 10, which further comprises a first resin part (55) which is filled into the first recess (511). Semiconductor device (B1) according to claim 1, wherein the at least one second power terminal (15) has two second power terminals (15) spaced apart from each other in a second direction (y) perpendicular to the thickness direction (z) and the first direction (x), and the two second power terminals (15) are each arranged on one side (y1) and an opposite side (y2) of the second direction (y), whereby the first power terminal (14) is sandwiched between them. Semiconductor device (B1) according to claim 1, wherein the control terminal carrier (48) has an insulating layer (481) and a metal layer (482) arranged on a surface of the insulating layer (481) which faces one side (z1) of the thickness direction (z), wherein the control terminal (45) is provided upright on the metal layer (482). Semiconductor device (B1) according to claim 1, wherein the sealing resin (50) covers a part of the control connector carrier (48). Method for manufacturing a semiconductor device (B1) comprising: a support substrate (11) with a front surface (1120) facing one side (z1) of a thickness direction (z); at least one semiconductor element (21) arranged on the front surface (1120); at least one control terminal (45) arranged on the front surface (1120) to control the at least one semiconductor element (21); a control terminal carrier (48) arranged between the support substrate (11) and the at least one control terminal (45) in the thickness direction (z) to support the control terminal (45); a sealing resin (50) with a front resin surface (51) facing one side (z1) of the thickness direction (z), wherein the sealing resin (50) covers at least a part of the support substrate (11); a first power connection (14) and at least one second power connection (15),which are arranged on one side (x1) of a first direction (x) relative to the carrier substrate (11), wherein the first direction (x) is perpendicular to the thickness direction (z); and at least one third power connection (16) which is arranged on an opposite side (x2) of the first direction (x) relative to the carrier substrate (11), wherein the control connection (45) projects in the direction of one side (z1) of the thickness direction (z) with respect to the front resin surface (51), wherein the method comprises a sealing resin formation step for forming the sealing resin (50) by forming it in such a way that the sealing resin (50) covers at least a part of the carrier substrate (11), a part of the control connection carrier (48), a part of each of the first power connection (14) and of the at least one second power connection (15), and a part of each of the at least one third power connection (16),wherein the sealing resin formation step comprises carrying out the molding with a mold (91) which is pressed against the control port carrier (48) in a state in which the control port (45) is not placed on the control port carrier (48), such that a first recess (511) is formed in the sealing resin (50), wherein the control port (45) has an electrically conductive cylindrical holder (451) and a metal pin (452) inserted into the holder (451), and the control port (45) is arranged in the at least one first recess (511) such that the control port (45) is completely exposed by the sealing resin (50). Method for manufacturing a semiconductor device (B1) according to claim 15, wherein in the sealing resin formation step the front resin surface (51) and the first recess (511) are formed, wherein the first recess (511) is recessed from the front resin surface (51) in the direction of an opposite side (z2) of the thickness direction (z) and has a shape corresponding to the shape (91), wherein the first recess (511) has a first recess inner surface (512) extending in the thickness direction (z), the first recess inner surface (512) being inclined such that its inner diameter decreases towards the opposite side (z2) of the thickness direction (z). Method for manufacturing a semiconductor device (B1) according to claim 16, wherein in the sealing resin formation step the forming is carried out such that the first recess (511) has a chamfered section (515) between the front resin surface (51) and the first recess inner surface (512). Method for manufacturing a semiconductor device (B1) according to claim 17, wherein in the sealing resin formation step the forming is carried out such that each of a plurality of first recesses (511) is arranged such that it overlaps with a corresponding control connection (45) as seen in the thickness direction (z). Method for manufacturing a semiconductor device (B1) according to claim 15, wherein in the sealing resin formation step the forming is carried out such that the first recess (511) is arranged so that it overlaps with a plurality of control terminals (45,) seen in the thickness direction (z). Method for manufacturing a semiconductor device (B1) according to claim 15, which further comprises a step for forming an insulating layer (481) for the control terminal carrier (48) and a resist layer prior to the sealing resin formation step, wherein the resist layer is formed in a region of a front surface of the insulating layer (481) in which no first metal layer (482) is formed. Method for manufacturing a semiconductor device (B1) according to claim 15, wherein the shape (91) has a lower end consisting of a damping material. Method for manufacturing a semiconductor device (B1) according to one of claims 15 to 21, which further comprises a control connection insertion step for inserting the control connection (45) into the first recess (511) after the sealing resin formation step. Method for manufacturing a semiconductor device (B1) according to claim 22, wherein in the control terminal insertion step a plurality of control terminals (45) are inserted accordingly into a plurality of first recesses (511). Method for manufacturing a semiconductor device (B1) according to claim 22, wherein in the control terminal insertion step a plurality of control terminals (45) are inserted into the at least one first recess (511). Method for manufacturing a semiconductor device (B1) according to claim 22, which further comprises a step of filling a first resin part (55) into the first recess (511) after the control connection insertion step.

Images