Light-emitting semiconductor element and method for producing a light-emitting semiconductor element

Abstract

A dry etching technique is used as a mesa formation technique for a substrate-bound light-emitting semiconductor device, which also provides a light-emitting semiconductor device with a high reverse voltage (Vr). The light-emitting semiconductor device comprises a reflective layer, an interelectrode layer, a first-conductor layer, an active layer, and a second-conductor layer in that order on a substrate. The interelectrode layer consists of a dielectric section and a conductor section, with one edge of this layer being the dielectric section. The dielectric section extends further outward as a side surface from the first-conductor layer to the second-conductor layer.The angle between a side surface of the layer of a first conduction type and the dielectric section is not less than 70° and not more than 85°, and there is no indentation on a semiconductor laminate side surface.

Description

TECHNICAL AREA

[0001] The present disclosure relates to a light-emitting semiconductor element and a method for manufacturing a light-emitting semiconductor element. BACKGROUND

[0002] The diversification of LED applications has led to an increasing demand for high-power, long-wavelength LEDs (emission wavelength: 1000 nm to 2000 nm) for use as light-emitting sections in blood glucose and humidity sensors. In InP-based LEDs with an emission wavelength of 1000 nm to 2000 nm, the use of aluminum in an active layer to improve light emission efficiency is an established technique.

[0003] For example, patent document (PTL) 1 discloses a surface emission-type semiconductor element comprising a semiconductor laminate formed from an n-type InP substrate, an n-type InP layer stacked on the n-type InP substrate, an active InGaAlAs layer stacked on the n-type InP layer, and a p-type InP layer stacked on the active InGaAlAs layer, and also comprising a reflective element covering the semiconductor laminate. Similarly, PTL 2 discloses a light-emitting semiconductor element containing InGaAlAs in an active layer. DOCUMENT LISTPatent documents PTL 1: JP 2018-182154 A PTL 2: JP 2021-77885 A PTL 3: JP 2022-101468 A SUMMARY (Technical Problem)

[0004] However, in substrate-bound light-emitting semiconductor devices, a problem existed in that the deposition of a dielectric on a side surface of an active layer during mesa formation led to poor reverse bias characteristics in the light-emitting semiconductor device. PTL 3 discloses an infrared device with an inclined mesa; however, PTL 3 investigates the mesa angle for an emission wavelength in the infrared range, and the exposure of a dielectric layer by etching in a substrate-bound device has not been previously disclosed.

[0005] One objective of the present disclosure is the use of a dry etching technique as a mesa formation technique for a substrate-bound light-emitting semiconductor element, while also providing a light-emitting semiconductor element with a high blocking voltage (Vr). (Solution to the problem)

[0006] In a situation where mesa formation is carried out by dry etching in a substrate-bound light-emitting semiconductor device, a dielectric, such as SiO2, is exposed at the end of the etching process. As a result of extensive and careful research to solve the aforementioned problem, the inventor found that a high degree of over-etching, as described below, tends to be observed in devices with a low Vr, and that its influence persists and negatively affects blocking bias characteristics even when a protective film is formed from above using SiO2 or the like. The inventor found that by limiting the over-etching rate and adjusting a mesa angle within a specific range under dry-etching conditions, a light-emitting semiconductor device with reduced current leakage and a high Vr can be obtained.

[0007] In particular, the main configurations of the present disclosure are given below. (1) Light-emitting semiconductor element comprising: a reflective layer formed on a support substrate; an intermediate electrode layer formed on the reflective layer; a first-type conduction layer formed on the intermediate electrode layer; an active layer formed on the first-type conduction layer; and a second-type conduction layer formed on the active layer, wherein the intermediate electrode layer is formed from a dielectric section and a conduction section, and an edge thereof is the dielectric section, the dielectric section being located further outward than a side surface of a semiconductor laminate comprising the first-type conduction layer, the active layer, and the second-type conduction layer, and in a cross-section of the semiconductor element, if a first straight line,which is externally tangential to a side surface of the layer of a first conduction type and a side surface of the layer of a second conduction type near the active layer, and a second line, parallel to the first line and contacting a side surface of the active layer, is drawn, the second line being further outward than the first line, the separation distance between the first line and the second line being zero or the second line being further inward than the first line with a separation distance between them of 10 nm or less, and a third line connecting a contact point of the interelectrode layer and the side surface of the layer of a first conduction type to a contact point on one side of the layer of a first conduction type of the first line, at an angle of not less than 70° and not more than 85° relative to an upper surface of the interelectrode layer on one side,in which the layer of a first conductor type is arranged. (2) Light-emitting semiconductor element according to (1) above, wherein the active layer contains one or two or more of Al, Ga and In as Group III elements and one or two or more of As, Sb and P as Group V elements, and the layer of a first conduction type contains one or two or more of Al, Ga and In as Group III elements and one or two or more of As, Sb and P as Group V elements. (3) Light-emitting semiconductor element according to (1) or (2) above, wherein a blocking voltage when a blocking current of 0.1 µA is applied is 20 V or more. (4) Light-emitting semiconductor element according to any of the preceding (1) to (3), wherein a line along the side surface of the layer of a first conduction type connecting a top end and a bottom end of the side surface has a curvature of not less than 0 and not more than 0.11. (5) Light-emitting semiconductor element according to any of the preceding (1) to (4) wherein the dielectric section is SiO2 or SiN. (6) Light-emitting semiconductor element according to any of the preceding (1) to (5), wherein a weight fraction of Si atoms on a side surface from an interface between the dielectric section and the layer of a first conduction type to a thickness center of the layer of a second conduction type is 2.5 wt.% or less. (7) Light-emitting semiconductor element according to any of the preceding (1) to (6), wherein the dielectric section is SiO2 and the weight fraction of O atoms on a side surface from an interface between the dielectric section and the layer of a first conduction type to a thickness center of the layer of a second conduction type is 7.5 wt.% or less. (8) A method for producing a light-emitting semiconductor device, comprising: a step of forming an etch stop layer on a growth substrate; a step of forming a layer of a second conduction type on the etch stop layer; a step of forming an active layer on the layer of a second conduction type; a step of forming a layer of a first conduction type on the active layer; a step of forming an intermediate electrode layer, comprising a dielectric section and a conductor section and having a border which is the dielectric section, on the layer of a first conduction type; a step of forming a reflective layer on the intermediate electrode layer; a step of forming a metal compound layer on a support substrate; a step of joining the reflective layer and the metal compound layer; and a step of removing the growth substrate.wherein the method further comprises a mesa formation step of removing a semiconductor laminate from the layer of a second conductor type to the layer of a first conductor type by dry etching along a planned chip parting line, thereby forming a side surface of the semiconductor laminate, and in a cross-section of the semiconductor device, where a first straight line, externally tangential to a side surface of the layer of a first conductor type and a side surface of the layer of a second conductor type near the active layer, and a second straight line, parallel to the first straight line and contacting a side surface of the active layer, are drawn, the second straight line being located further outward than the first straight line, a separation distance between the first straight line and the second straight line being zero, or the second straight line being located further inward than the first straight line with a separation distance between them of 10 nm or less,and a third straight line, which connects a contact point of the interelectrode layer and the side surface of the layer of a first conduction type and a contact point on a side of the layer of a first conduction type of the first straight line, forms an angle of not less than 70° and not more than 85° relative to an upper surface of the interelectrode layer on a side where the layer of a first conduction type is arranged. (9) Method for producing a light-emitting semiconductor element according to (8) above, wherein the over-etch rate during dry etching is not less than 1% and not more than 9%. (10) Method for producing a light-emitting semiconductor element according to (8) or (9) above, wherein the weight fraction of Si atoms on a side surface from an interface between the dielectric section and the layer of a first conduction type to a thickness center of the layer of a second conduction type immediately after the mesa formation step is 2.5 wt.% or less. (Beneficial effect)

[0008] According to the present disclosure, a dry etching technique can be used as a mesa formation technique for a substrate-bound light-emitting semiconductor element, while also providing a light-emitting semiconductor element with a high blocking voltage (Vr). BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In the attached drawings: Fig.Figure 1 is a schematic cross-sectional view showing the structure of a light-emitting semiconductor element according to the present disclosure; Fig. Figure 2A is a schematic cross-sectional view to describe a method for manufacturing a light-emitting semiconductor element according to the present disclosure; Fig. 2B is a schematic cross-sectional view, which is based on the Fig. 2A follows, describing the process for manufacturing a light-emitting semiconductor element; Fig. 2C is a schematic cross-sectional view, which is based on the Fig. 2B follows, to describe a state prior to dry etching in the process for manufacturing a light-emitting semiconductor element; Fig. 2D is a schematic cross-sectional view, which is based on the Fig.2C follows, to describe a state after dry etching in the process for manufacturing a light-emitting semiconductor element; Fig. Figure 3A is a first drawing showing SEM cross-sectional images of a light-emitting semiconductor element according to Example 1; Fig. Figure 3B is a second drawing showing a SEM image of a side surface of a semiconductor laminate in the light-emitting semiconductor element according to Example 1; Fig. Figure 4 is a drawing showing SEM cross-sectional images of a light-emitting semiconductor element according to Example 2; Fig. Figure 5 is a drawing showing SEM cross-sectional images of a light-emitting semiconductor element according to Example 3; Fig. Figure 6 is an explanatory drawing for an indentation and an angle θ using SEM cross-sectional images of a light-emitting semiconductor element according to comparison example 1; Fig.Figure 7A is a first drawing showing SEM cross-sectional images of a light-emitting semiconductor element according to comparison example 2; Fig. Figure 7B is a second drawing showing a SEM image of a side surface of a semiconductor laminate in the light-emitting semiconductor element according to comparison example 2; Fig. Figure 8 is a drawing showing SEM cross-sectional images of a light-emitting semiconductor element according to comparison example 3; Fig. Figure 9A is a first drawing showing SEM cross-sectional images of a light-emitting semiconductor element according to comparison example 4; and Fig. Figure 9B is a second drawing showing a SEM image of a side surface of a semiconductor laminate in the light-emitting semiconductor element according to comparison example 4. DETAILED DESCRIPTION

[0010] Before describing embodiments according to the present disclosure, the following points are addressed in advance using Fig. 6 described according to a comparative example. <einbuchtung>

[0011] The term "indentation," as used in a present embodiment, refers to a depression in a side surface of a semiconductor laminate formed because an active layer is etched faster than other layers. If a first straight line (A in the drawing), externally tangential to a side surface of a layer of a first conduction type and a side surface of a layer of a second conduction type near an active layer, and a second straight line (B in the drawing), parallel to the first straight line and contacting a side surface of the active layer, are drawn, a state is formed in which the second straight line is located further inward than the first straight line (i.e.,, the second line is on the side of the semiconductor laminate), the separation distance between the first line and the second line is more than 10 nm, and the side surface of the active layer is significantly indented relative to the side surface of the layer of a first conductor type and the side surface of the layer of a second conductor type, is considered a state in which an indentation is present. An indentation is considered absent in a case where the second line is further outward than the first line, in a case where the separation distance between the first line and the second line is zero, and in a case where the second line is further inward than the first line with a separation distance of 10 nm or less. In the . Fig. In section 6, where a dimple is present, the second straight line, separated by a distance of approximately 400 nm, lies further inward than the first straight line. The presence of a dimple can lead to the formation of a shortcut for current between the layer of a first conductor type and the layer of a second conductor type, and to a reduction in the reverse voltage. It should be noted that "near the active layer" refers to a region extending in one thickness direction from an interface between the active layer and the layer of a first conductor type, or between the active layer and the layer of a second conductor type, by a factor of three times the thickness of the active layer.In a configuration where a recess is absent, as described above, a case where the second line is located further outward than the first line is preferred as a shape that does not cause a shortcut for current between the layer of a first conductor type and the layer of a second conductor type, and a case where the separation distance between the first line and the second line is zero is also preferred. In a case where the second line is located further outward than the first line, the separation distance between the two lines can be any distance as long as it is unlikely that the active layer will be damaged, and can, for example, be 400 nm or less. <Winkel θ>

[0012] The term ‘angle θ’, as used in a present embodiment, refers to an angle formed by a third straight line (C in the drawing) connecting a contact point of an intermediate electrode layer (dielectric section of the intermediate electrode layer) and a layer of a first conduction type and a contact point of the aforementioned first straight line (A in the drawing), with a side surface of the layer of a first conduction type relative to a top surface of the intermediate electrode layer (dielectric section of the intermediate electrode layer) on a side where the layer of a first conduction type is located. <Krümmung>

[0013] The term “curvature”, as used in a present embodiment, refers to the curvature of a line along a side surface connecting a contact point of an intermediate electrode layer (dielectric section of the intermediate electrode layer) and a side surface of a layer of a first conduction type and a contact point of the aforementioned first straight line (A in the drawing) with the side surface of the layer of a first conduction type (contact point of the side surface of the layer of a first conduction type and a side surface of the aforementioned active layer in a case where an indentation is absent).The curvature is calculated using image measurement software to determine a circular arc along three points, including the two contact points described above and an intermediate point equidistant between these contact points, and then calculating the radius of the corresponding circle. <Over-etch rate>

[0014] The term “over-etch rate”, as used in a present embodiment, refers to a value determined by dividing the over-etch time by the etch time, with the proviso that a point at which a layer of a first conductor type in a part of a street area has disappeared according to a spectroscopic plasma emission detection device provided with a dry etching apparatus (i.e., a point at which the plasma emission intensity is no more than a predetermined value and also at a time when the exposure of part of a dielectric section begins) is defined as an end time, and a period for which etching is carried out after the end time is defined as the over-etch time.

[0015] The angle θ and curvature described above are evaluated in a present embodiment using a focused ion beam (FIB) or the like related to a light-emitting semiconductor element to form a cross-section, acquiring a cross-sectional SEM (scanning electron microscope) image, and measuring the angle and curvature of the acquired image. The cross-sectional SEM image was acquired at an accelerating voltage of 5 kV using a JSM7000F FE-SEM manufactured by JEOL Ltd., and the angle θ and curvature were measured using the IC Measure image measurement software manufactured by The Imaging Source.

[0016] In a present embodiment, the mass percentage and atomic percentage of elements in each layer on a side surface of a semiconductor laminate are measured by energy-dispersive X-ray spectroscopy (EDS) performed on the side surface of the semiconductor laminate. This allows confirmation of the presence or absence of deposition on the side surface near an active layer. The EDS analysis was performed at an accelerating voltage of 10 kV using the aforementioned FE-SEM JSM7000F, manufactured by JEOL Ltd.

[0017] The reverse voltage Vr was measured in a present embodiment using an LED tester (model number: LX4730A) manufactured by YAC Garter Co., Ltd. A wafer prior to element singulation was inserted into a probe device, a probe was positioned against a contact electrode on the top side of an element, and the reverse voltage (Vr) was measured by conducting a 0.1 µA reverse current. Approximately 5000 measurements were taken, and an average value was used as the reverse voltage (Vr) value.

[0018] The term “InGaAlAs”, as used in a present embodiment, stands for In a Ga b Al 1-a-b As, wherein the composition ratios of In, Ga, and Al are a, b, and 1 - a - b, respectively. Values ​​of the In composition ratio a and the Ga composition ratio b in the InGaAlAs composition ratio in a present embodiment are determined from wavelengths investigated by photoluminescence measurements taken on the surface of each layer after that layer has been grown. The In composition ratio a and the Ga composition ratio b are not less than 0 and not more than 1 and satisfy 0 ≤ 1 - a - b ≤ 1 unless otherwise specified. EDS can, for example, be used as a method for determining the In composition ratio and the Ga composition ratio from a cross-section of a light-emitting semiconductor device.

[0019] In this description, a layer is referred to as "undoped" if a specific dopant, such as Si, S, or Zn, is not intentionally added to it. An undoped layer may contain a dopant that is unavoidably mixed in during the manufacturing process.

[0020] One embodiment of the present disclosure is described below. (Light-emitting semiconductor element)

[0021] A light-emitting semiconductor element obtained according to a present embodiment is described below.

[0022] As it is in the Fig. As shown in Figure 1, a light-emitting semiconductor element 1 according to the present embodiment comprises a reflective layer 91 formed on a support substrate 190, a metal compound layer 92 formed on the reflective layer 91, an intermediate electrode layer 80 formed on the metal compound layer 92, a layer of a first conduction type 60 formed on the intermediate electrode layer 80, an active layer 50 formed on the layer of a first conduction type 60, and a layer of a second conduction type 40 formed on the active layer 50. The intermediate electrode layer 80 is formed from a dielectric section 82 and a conductor section 81. An edge of the intermediate electrode layer 80 is the dielectric section 82.

[0023] The light-emitting semiconductor element 1, which is located in the Fig. The semiconductor element shown in Figure 1 has the following features. In the light-emitting semiconductor element 1, the dielectric section 82 is located further outward than a side surface of a semiconductor laminate 200, which comprises the first-conductor layer 60, the active layer 50, and the second-conductor layer 40. Consequently, in a cross-section of the element, the dielectric section of the interelectrode layer is located further outward than a contact point between the interelectrode layer and a side surface of the first-conductor layer (i.e., further toward a side where the first-conductor layer is not present). When viewed from above, the semiconductor laminate 200 has a shape such that an upper surface of the dielectric section 82 is visible further outward than a perimeter of the semiconductor laminate 200.Furthermore, the angle θ described above, which the side surface of the layer of a first conduction type 60 forms relative to the dielectric section 82, is not less than 70° and not more than 85°. In the present description, there is no indentation such as that already described, and if a first straight line, which is externally tangential to a side surface of the layer of a first conduction type 60 and a side surface of the layer of a second conduction type 40 near the active layer, and a second straight line, which is parallel to the first straight line and contacts a side surface of the active layer, are drawn, the second straight line is located further outwards than the first straight line, with a separation distance between the first straight line and the second straight line being zero, or the second straight line is located further inwards than the first straight line, with a separation distance between them being 10 nm or less.

[0024] As a result of the light-emitting semiconductor element 1 having the configuration specified above, the light-emitting semiconductor element 1 exhibits a reverse voltage of 20 V or more when a reverse current of 0.1 µA is applied.

[0025] The layer of a first conductor type 60 can comprise a layer such as an electron-blocking layer, a cladding layer, or a contact layer. Similarly, the layer of a second conductor type 40 can also comprise a layer such as a cladding layer or a contact layer. Furthermore, an undoped layer, referred to as a spacer layer, can be included between the active layer 50 and the layer of a first conductor type 60 or between the active layer 50 and the layer of a second conductor type 40. The layer of a first conductor type 60 and the layer of a second conductor type are preferably layers with a larger band gap than the active layer 50.

[0026] The active layer 50 preferably contains one or two or more of Al, Ga, and In as elements of group III and preferably contains one or two or more of As, Sb, and P as elements of group V. Furthermore, the layer of a first conductor type 60 preferably contains one or two or more of Al, Ga, and In as elements of group III and preferably contains one or two or more of As, Sb, and P as elements of group V. The use of a layer that results in a light emission wavelength of 1000 nm or more is preferred.

[0027] The angle θ is preferably not less than 70° and not more than 85°, more preferably not less than 76° and not more than 85°, and particularly preferably not less than 77° and not more than 84°. This is because with an angle θ of less than 70° it becomes necessary to increase the lane width and decrease the number of chips per wafer in order to create an area where the layer of a first conductor type 60 is absent, with a width that does not impede splitting, whereas an angle θ of more than 85° leads to a reduced blocking voltage.Furthermore, the curvature of a line along the side surface of the layer of a first conductor type 60, connecting an upper end and a lower end of the side surface, is preferably not less than 0 and not more than 0.11, more preferably not less than 0 and not more than 0.09 and particularly preferably not less than 0.01 and not more than 0.08.

[0028] The dielectric section 82 is preferably SiO2 or SiN, and more preferably SiO2. Furthermore, on a side surface from an interface between the dielectric section 82 and the layer of a first conductor type 60 to a thickness center of the layer of a second conductor type 40 (hereinafter also referred to as a main side surface), it is preferred that the weight fraction of Si atoms is 2.5 wt.% or less and the proportion of Si atoms is 5% or less. The weight fraction of Si atoms is more preferably not less than 0.1 wt.% and not more than 2.5 wt.%, and particularly preferably not less than 1.0 wt.% and not more than 2.5 wt.%. In a case where the dielectric section 82 is SiO2, the weight fraction of O atoms is preferably not less than 0.3 wt.% and not more than 7.5 wt.%. It should be noted that, although a protective film 70 is present in the Fig. As shown in Figure 1, the protective film 70 can be omitted. The proportion of the number of Si atoms and the weight fraction of Si or O atoms on the main side surface are preferably measured in a state in which the protective film 70 is not formed on the side surface.

[0029] Details of each configuration are described below, including an embodiment of a manufacturing process for obtaining the light-emitting semiconductor element 1 and the steps in that manufacturing process. (Method for manufacturing a light-emitting semiconductor element)

[0030] The Fig. Figures 2A to 2D are process diagrams of a method for producing the light-emitting semiconductor element 1 described above. These drawings each schematically show a partial cross-section of a growth substrate. To facilitate the description, the interelectrode layer and electrodes are simplified, and the ratios of the lengths and widths of the substrate and each layer are exaggerated without considering their actual proportions. As shown in Fig. As shown in Figures 2A to 2D, a method for fabricating a light-emitting semiconductor element 1 according to the present disclosure comprises first depositing each semiconductor layer on a growth substrate 10 by epitaxial growth and then forming an intermediate electrode layer 80. Next, the intermediate electrode layer 80 and a support substrate 190 are joined by a metal compound layer 92 and a reflective layer 91, which has been formed on one side corresponding to the growth substrate 10. The growth substrate is then removed. Next, an ohmic electrode of the upper surface is formed, and then mesa formation is carried out by dry etching. <halbleiterschichten>

[0031] The growth substrate 10 can be a composite substrate, such as GaAs, InP, or InAs, and can be a substrate fabricated according to a standard process. The growth substrate 10 is preferably n-type doped and preferably has a thickness of not less than 200 µm and not more than 900 µm. The element with which the growth substrate 10 is doped can be S or the like. A brief description of each semiconductor layer is given below.

[0032] First, a buffer layer 20 can be grown epitaxially on the growth substrate 10. The buffer layer 20 serves to facilitate a lattice mismatch between the growth substrate 10 and an etch stop layer 30 described below. The buffer layer 20 can be formed, for example, by metal-organic chemical vapor deposition (MOCVD). The buffer layer 20 preferably has a thickness of not less than 0.01 µm and not more than 0.5 µm and is preferably n-type doped. The element with which the buffer layer 20 is doped can be silicon or the like. Next, an etch stop layer 30 is stacked on top of the buffer layer 20. It is preferred that the etch stop layer 30 is not etched under conditions that etch the growth substrate 10 and the buffer layer 20, and has a composition that allows lattice matching with a layer of a second conductor type 40.The thickness of the etch stop layer 30 is preferably not less than 0.01 µm and not more than 0.1 µm, and more preferably not less than 0.02 µm and not more than 0.05 µm. Furthermore, the etch stop layer 30 is preferably n-type doped. The element with which the etch stop layer 30 is doped can be silicon or the like. Next, a layer of a second conductor type 40 is stacked on the etch stop layer 30. The thickness of the layer of the second conductor type 40 should be sufficient for the delivery of carriers and is, for example, preferably not less than 2 µm and not more than 10 µm. The layer of the second conductor type 40 is preferably n-type doped. The element with which the layer of the second conductor type 40 is doped can be silicon or the like.

[0033] An active layer 50 is stacked on top of a layer of a second conductor type 40. As described above, the active layer 50 preferably contains one or two or more of Al, Ga, and In as elements of Group III and preferably contains one or two or more of As, Sb, and P as elements of Group V. The active layer 50 can be a single-layer structure, a double hetero (DH) structure, or a multiple quantum well structure in which a plurality of barrier layers and well layers are stacked alternately. Drawings for the present embodiment show a multiple quantum well structure as an example.

[0034] Next, a layer of a first conduction type 60 is stacked on the active layer 50. The layer of a first conduction type 60 may include an electron-blocking layer on one side corresponding to the active layer 50. As described above, the layer of a first conduction type 60 preferably contains one or two or more of Al, Ga, and In as elements of Group III and preferably contains one or two or more of As, Sb, and P as elements of Group V. The thickness of the layer of a first conduction type 60 is preferably not less than 0.4 µm and not more than 5 µm, and more preferably not less than 1 µm and not more than 3 µm. Furthermore, the layer of a first conduction type 60 is preferably p-type doped. The element with which the layer of a first conduction type 60 is doped may be Zn or the like.Semiconductor layers stacked above the etch stop layer 30 on the growth substrate 10 (i.e., layers from the layer of a second conduction type 40 to the layer of a first conduction type 60) are referred to as semiconductor laminate 200. <zwischenelektrodenschicht>

[0035] An intermediate electrode layer 80 is formed on a layer of a first conductor type 60. First, a photoresist is preferably applied to the entire surface of the layer of the first conductor type 60. The photoresist is structured with a specific shape by photolithography, such that a semiconductor layer of the layer of the first conductor type 60 is exposed only in an area where a conductor section 81, as described below, is to be formed. Next, a metal film is preferably vapor-deposited onto the layer of the first conductor type 60, including onto the structured photoresist. The metal used can be AuZn or the like. By removing the photoresist and the metal film on the photoresist by peeling, a conductor section 81 with a desired structure is formed on the layer of the first conductor type 60.The conductor section 81 is preferably subjected to heat treatment by RTA (rapid thermal annealing). It should be noted that a contact layer, obtained by doping in the layer of a first conductor type 60 at a high concentration, can be structured and arranged on one side of the conductor section 81 where the layer of a first conductor type 60 is located.

[0036] Next, a dielectric section 82 is formed at an edge of the conductor section 81 on the layer of a first conductor type 60. An insulating film is preferably gas-phase deposited on the layer of a first conductor type 60, including on the conductor section 81. The insulating film used here is preferably SiO2 or SiN. After deposition of the insulating film, the dielectric section 82 can be formed by removing the insulating film on the conductor section 81 by etching using a mask structure with a photoresist and subsequently removing the remaining photoresist by peeling. The method by which the metal film and the insulating film mentioned above are deposited can be a conventional method, such as sputtering or plasma CVD. The thickness of the interelectrode layer 80 is not limited, but can, for example, be increased.not less than 300 nm and not more than 1300 nm, and may more preferably be set to not less than 350 nm and not more than 800 nm, and even more preferably to not less than 430 nm and not more than 640 nm. <Bildung der reflektierenden Schicht>

[0037] As it is in the Fig. As shown in Figure 2B, a reflective layer 91 is formed on the intermediate electrode layer 80. The reflective layer 91 can comprise a plurality of metal layers. Examples of metals that can form the reflective layer 91 include not only Au, but also Al, Pt, Ti, Ag, etc. For example, the reflective layer 91 can be a single layer composed only of Au, or it can comprise two or more Au metal layers. The composition of the reflective layer 91 preferably comprises 50 wt% or more Au. Furthermore, to reliably perform a connection with a metal compound layer 92 in a subsequent step, an outermost layer of the reflective layer 91 (surface on a side opposite the intermediate electrode layer 80) is preferably an Au metal layer.

[0038] For example, the reflective layer 91 can be formed by depositing each of the metals Al, Au, Pt, and Au in that order onto the intermediate electrode layer 80. The thickness of Au at an outermost surface of the reflective layer 91 can be adjusted, for example, to not less than 400 nm and not more than 2000 nm, and the thickness of a metal layer formed from a metal other than Au can be adjusted, for example, to not less than 5 nm and not more than 200 nm. The reflective layer 91 can be deposited and formed using a typical technique, such as vapor deposition.

[0039] A metal compound layer 92 is formed on a support substrate 190 by stacking a metal, such as Ti, Pt, or Au, a metal (Sn, etc.) forming a eutectic alloy with Au, or a solder. For example, the metal compound layer 92 can be formed by stacking Ti with a thickness of not less than 400 nm and not more than 800 nm, Pt with a thickness of not less than 5 nm and not more than 20 nm, and Au with a thickness of not less than 700 nm and not more than 1200 nm, in that order, from the surface of the support substrate 190. To reliably facilitate bonding with the reflective layer 91 described above, an outermost surface of the metal compound layer 92 (the surface on a side opposite the support substrate) is preferably also an Au metal layer. In this case, bonding between the Au components can be carried out by Au-Au diffusion. <Verbinden mit dem Trägersubstrat>

[0040] The following describes the connection to the carrier substrate 190 with reference to the Fig. 2B described. The semiconductor laminate 200 and the interelectrode layer 80 are connected to the support substrate 190 by the reflective layer 91 and the metal compound layer 92. The connection can be carried out by arranging the metal compound layer 92 and the reflective layer 91 opposite each other and then performing a hot press joining at a temperature not lower than 250 °C and not higher than 500 °C with a surface pressure of not less than 5 kN and not more than 15 kN for not less than 20 minutes and not more than 40 minutes.

[0041] The support substrate 190 is described below. The support substrate 190 should be a different type of substrate from the growth substrate 10 and can be a semiconductor substrate, such as that described above, a metal substrate, a mounting base substrate in which a ceramic substrate serves as the base, or the like. Since the joining method described above is used, the support substrate 190 may exhibit a lattice mismatch with the semiconductor layers formed in the present embodiment. It should be noted that, although the support substrate 190 may be an electrically insulating substrate depending on the application, an electrically conductive substrate is preferred.The use of a silicon substrate allows for a significant reduction in the thickness of the support substrate 190 compared to that which is conventionally used, and is also suitable for assembly in combination with various types of semiconductor devices. Furthermore, a silicon substrate also offers advantages with regard to heat dissipation. <Entfernung des Wachstumssubstrats>

[0042] The removal of the growth substrate 10 is described below with reference to the Fig. 2C described. The growth substrate 10 is removed after bonding the support substrate 190. In a case where the growth substrate 10 is an InP substrate, the growth substrate 10 can be wet-etched, for example, using dilute hydrochloric acid. Alternatively, the growth substrate 10, the buffer layer 20, and part of the etch-stop layer 30 can be ground away.

[0043] After removal of the growth substrate 10, an Ohmic electrode (not shown) is preferably formed on an upper surface (surface on a side opposite the support substrate 190) of the semiconductor layers. The Ohmic electrode can be formed using a metal such as Au, Ge, Ni, or Ti, a metal (Sn, etc.) forming a eutectic alloy with Au, or a solder. The Ohmic electrode can be deposited and formed using a typical technique such as vapor deposition. The thickness of the Ohmic electrode is not limited, but can be, for example, not less than 300 nm and not more than 1300 nm, and can more preferably be set to not less than 350 nm and not more than 800 nm.

[0044] After the formation of the ohmic electrode, a contact electrode is preferably formed on the ohmic electrode. The contact electrode can be formed using a metal such as Ti or Au, a metal (Sn, etc.) that forms a eutectic alloy with Au, or a soldering material. The contact electrode can be formed using a typical technique, such as vapor deposition.

[0045] After the formation of the contact point electrode, the surface of the ohmic electrode, except for the contact point electrode, undergoes surface roughening. This surface roughening is performed to increase light extraction efficiency. Surface roughening of the ohmic electrode can be carried out using a typical technique, such as selective etching with a mask. The ohmic electrode and the contact point electrode that do not undergo surface roughening are used in combination as an upper surface ohmic electrode and a contact point electrode 170. <mesa-bildungsschritt>

[0046] A section of the semiconductor laminate 200 is removed by dry etching, so that a side surface of the semiconductor laminate 200 is formed, as described in the Fig. The process is shown in 2D. The dry etching method is preferably reactive ion etching (RIE), and an inductively coupled plasma (ICP) can, for example, be used as the plasma source. The dry etching is performed, viewed from above, with respect to a lane region of a fixed width along a planned chip division line. The lane width is the width required to perform a chip division without negatively affecting the active layer, etc., and can, for example, be 40 µm to 100 µm. The lane region can be provided with a grid configuration. The contact electrode formed as described above and the conductor section 81 of the intermediate electrode layer 80 are arranged, viewed from above, in a region distinct from the lane region.Dry etching of the gas region is carried out after a mask (for example, a SiO2 mask) has been formed on the semiconductor laminate 200 (on the layer of a second conductor type 40) that has a lower etch rate than the semiconductor laminate 200 during dry etching and that does not disappear until the end of the etching of the gas region, so that the semiconductor laminate 200 is exposed in the gas region described above. The etching conditions for dry etching are set such that the etching is carried out until the dielectric section 82 of the interelectrode layer 80 is exposed on the outside of the side surface of the semiconductor laminate 200.Furthermore, the dry etching conditions are optimized such that the angle θ formed by the dielectric section 82 and the layer of a first conduction type 60 is not less than 70° and not more than 85°, and so that no indentation is formed on the side surface of the active layer 50. Preferred dry etching conditions are a table temperature of not less than 180 °C and not more than 200 °C, a SiCl4 / Ar mixed gas, a pressure of not less than 0.2 Pa and not more than 1.0 Pa, a bias power of not less than 50 W and not more than 150 W, and an ICP power of not less than 190 W and not more than 400 W.More preferred conditions are a table temperature of not less than 190 °C and not more than 200 °C, a pressure of not less than 0.2 Pa and not more than 0.6 Pa, a bias power of not less than 70 W and not more than 150 W, and an ICP power of not less than 190 W and not more than 250 W. Furthermore, the over-etch rate is preferably not less than 1% and not more than 9%, more preferably not less than 3% and not more than 7%, and more preferably 6% or less. With an over-etch rate of zero to less than 1%, it is not possible to produce an area without the layer of a first conductor type 60 that has a width that does not affect the cutting process, and there are concerns that this could lead to a larger lane width and a lower number of chips per wafer.

[0047] Although the SiO2 of the mask and the SiO2 of the dielectric section 82 have a low etch rate, they do not remain completely unetched. Since virtually no Si or oxygen atoms carried away from the SiO2 of the mask reach the side surface of the semiconductor laminate 200 due to an exhaust stream within a dry etching device, problems caused by the adhesion of Si or oxygen atoms to the side surface of the semiconductor laminate 200 have not occurred in a conventional case where a dielectric section 82 is not present, or in a case where etching is not carried out far enough to expose the dielectric section 82.In the present configuration, where dry etching is carried out until SiO2 of the dielectric section 82 is exposed, a problem has arisen in that Si atoms or oxygen atoms carried out by SiO2 of the dielectric section 82 during over-etching collide with the side surface of the semiconductor laminate 200.It is assumed that limiting the over-etch rate and adjusting the angle θ formed by the intermediate electrode layer 80 (dielectric section 82 of the intermediate electrode layer 80) and the layer of a first conduction type 60 to not less than 70° and not more than 85°, as is the case in the present disclosure, has enabled a reduction in the extent of collisions with the side surface near the active layer of the semiconductor laminate 200 due to a relationship between the extent of erosion and the angle of erosion of SiO2 of the dielectric section 82.

[0048] The dry etching conditions are preferably adjusted such that, in an EDS analysis of a side surface from an interface between the dielectric section 82 and the layer of a first conductor type 60 to a thickness center of the layer of a second conductor type 40 (i.e., a main side surface), the weight fraction of Si atoms is 2.5 wt.% or less, and the number of Si atoms is 5% or less. The weight fraction of Si atoms is more preferably not less than 0.1 wt.% and not more than 2.5 wt.%, and particularly preferably not less than 1.0 wt.% and not more than 2.5 wt.%. Furthermore, in a case where the dielectric section 82 is SiO₂, the weight fraction of O atoms is preferably not less than 0.3 wt.% and not more than 7.5 wt.%.The proportion of the number of Si atoms and the weight fraction of Si or O atoms on the main side surface are preferably measured in a state in which a protective film 70 described below is not formed on the side surface.

[0049] After mesa formation, a protective film 70 is preferably formed by plasma CVD or the like. The protective film used at this stage can be SiO2, SiN, or the like. The SiO2 of the mask in the mesa formation step can be used as part of the protective film 70. Furthermore, the protective film 70 preferably does not cover an upper surface of the contact electrode. The thickness of the protective film 70 is preferably not less than 50 nm and not more than 500 nm. Next, the thickness of the support substrate 190 is preferably adjusted by grinding or etching such that the overall thickness of a light-emitting semiconductor element is set. Although there are no limitations regarding the overall thickness of a light-emitting semiconductor element in the present embodiment, the thickness is preferably not less than 2.4 µm and not more than 15 µm.Next, a rear surface ohmic electrode 160 is preferably formed on a rear surface of the support substrate 190. The rear surface ohmic electrode 160 can be formed using a metal such as Ti, Pt, or Au, a metal (Sn, etc.) forming a eutectic alloy with Au, or a soldering agent. The rear surface ohmic electrode 160 can be deposited and formed using a typical technique such as vapor deposition. The thickness of the rear surface ohmic electrode 160 is not limited, but can, for example, be not less than 300 nm and not more than 1300 nm, and can more preferably be set to not less than 350 nm and not more than 800 nm. The rear surface ohmic electrode 160 that has been formed is preferably heat-treated by RTA.Finally, a division is preferably carried out using a division device or a scoring device to achieve singulation of light-emitting semiconductor elements.

[0050] The inventor has found that, in the present disclosure, it is crucial to optimize the over-etch time in the etching conditions during mesa formation such that the shape of the main side surface, the angle θ, and the curvature are maintained within specific ranges. Setting the angle 0 to 85° or less prevents current leakage. This may be because, when dry etching is performed under conditions resulting in an angle θ of 85° or less, the over-etch rate is low, leading to low deposition on the side surface of the active layer, preventing deposition-induced leakage current, and improving the blocking bias characteristics.

[0051] The side surface of the semiconductor laminate 200 after the mesa formation step is preferably not subjected to any surface roughening treatment. This is because surface roughening can lead to the formation of an indentation. The surface roughening is preferably carried out with respect to an upper surface of the semiconductor laminate 200. The area in which the surface roughening is carried out with respect to the upper surface of the semiconductor laminate 200 more preferably excludes the gas area, the ohmic electrode of the upper surface, and the contact point electrode 170 and their surroundings.

[0052] The present revelation is described in more detail below by means of examples. However, the present revelation is in no way limited by the following examples. EXAMPLES (Example 1)

[0053] An n-type InP buffer layer (thickness: 0.1 µm; Si-doped; dopant concentration: 5.0 × 10⁻⁶) 17 / cm 3 ), an n-type in 0,57 Ga 0,43 As etch stop layer (thickness: 0.02 µm; Si-doped; dopant concentration: 5.0 × 10 17 / cm 3 ) and an n-type InP sheath layer (thickness: 3.5 µm; Si-doped; dopant concentration: 5.0 × 10 17 / cm 3 ) were grown in this order by MOCVD on an n-type InP growth substrate (thickness: 600 µm; S-doped; dopant concentration: 2.0 × 10 18 / cm 3 ). Next, a multiple quantum well structure is formed, consisting of undoped In 0,42 Ga 0,42 Al 0,16 As-blocking layers and undoped InGa 0,195 Al 0,04 As-sulfur trough layers are formed, creating an active layer. After deposition of an In 0,42 Ga 0,42 Al 0,16 An 8 nm thick acetylene barrier layer was used to create an InGa 0,195 Al 0,04 As trough layer with a thickness of 10 nm and an In 0,42 Ga 0,42 Al 0,16 An 8 nm thick arsenic barrier layer was formed alternately for 10 layers at a time, resulting in a multiple quantum well structure consisting of 10.5 groups, including the first barrier layer. An undoped in 0,522 Al 0,478 As electron blocking layer (thickness: 0.02 µm) and a p-type InP shell layer (thickness: 2.4 µm; Zn-doped; dopant concentration: 7.0 × 10 17 / cm 3 The dopants are formed on the last barrier layer. The thickness and dopant concentration of each semiconductor layer referred to here are design parameters for the growth of each layer.

[0054] Next, a photoresist was applied to the entire surface of the p-type InP cladding layer. The photoresist was patterned with a specific design using photolithography, and then the photoresist was removed, exposing the p-type InP cladding layer in the area where a conductor section was to be formed. AuZn (thickness: 550 nm) was vapor-deposited onto the p-type InP cladding layer, including the photoresist, by sputtering. The photoresist and the AuZn on the photoresist were then removed by peeling. Finally, a heat treatment (condition: 300 °C) was performed using RTA. This enabled the formation of a conductor section of an interelectrode layer.

[0055] Next, an insulating film (thickness: 700 nm) formed from SiO2 was deposited onto the p-type InP cladding layer, including the conductor section, using plasma CVD. A dielectric section was then formed by applying a photoresist to the deposited SiO2 insulating film, using a mask structure created by the photoresist to remove the SiO2 insulating film from the conductor section by etching, and subsequently removing the remaining photoresist by peeling. This enabled the formation of an interelectrode layer consisting of a dielectric section and a conductor section, with one edge forming the dielectric section. It should be noted that a gap of a specific width is formed between the dielectric section and the conductor section, and that the thickness of the dielectric section is greater than the thickness of the conductor section.

[0056] A reflective layer (Ti (thickness: 2 nm) / Au (thickness: 650 nm) / Pt (thickness: 100 nm) / Au (thickness: 900 nm)) was formed on the interelectrode layer by vapor deposition. Additionally, a metal compound layer (Ti (thickness: 650 nm) / Pt (thickness: 20 nm) / Au (thickness: 900 nm)) was formed on a support substrate (Si substrate) by vapor deposition. The reflective layer and the metal compound layer were positioned opposite each other and subjected to hot press bonding at 350 °C with a surface pressure of 10 kN for 30 minutes.Although not shown, cavities are formed at an interface between the reflective layer and the metal compound layer due to depressions in the reflective layer that are located at positions corresponding to and near the conductor section as a result of the gap being formed between the dielectric section and the conductor section, and as a result of the thickness of the dielectric section being greater than the thickness of the conductor section.

[0057] Next, the growth substrate and buffer layer were removed by wet etching using dilute hydrochloric acid, exposing the etch stop layer. A mask was then formed by photolithography on the etch stop layer at one location where the top-surface Ohm electrode and the contact electrode, described below, were to be formed in that order, leaving the etch stop layer as the contact layer. The etch stop layer was removed at other locations by wet etching using an aqueous mixture of tartaric acid and hydrogen peroxide.

[0058] After removing the mask to expose the etch stop layer, Au (thickness: 10 nm) / Ge (thickness: 30 nm) / Au (thickness: 60 nm) / Ni (thickness: 30 nm) / Au (thickness: 800 nm) / Ti (thickness: 100 nm) / Au (thickness: 1000 nm) were deposited onto it by vapor deposition, forming an ohmic electrode on the upper surface. Next, a contact electrode (Ti (thickness: 150 nm) / Pt (thickness: 100 nm) / Au (thickness: 2500 nm)) was deposited onto the ohmic electrode of the upper surface by vapor deposition. The electrode structure was removed by a photoresist lifting process.

[0059] Next, a photoresist mask was created by photolithography such that a lane region along a planned chip division line, as well as the top-surface Ohm electrode and the contact point electrode, were covered. A light extraction surface from the n-type InP cladding layer, distinct from the masked region, underwent top-surface roughening by wet etching. Since the lane region is covered by the mask and does not undergo surface roughening, the lane region covered by the mask becomes a dam-like unetched area surrounding a recessed section that has undergone surface roughening, as described in the Fig. Figure 3A is shown. The formation of this unetched area is preferred because a mask exposure area can be formed along a subsequently described planned chip division line on an upper flat surface of the area, which makes it possible to prevent meandering or anomalies of a mesa shape due to dry etching.

[0060] Next, SiO2 was formed across the entire surface using plasma CVD. A SiO2 mask, shaped to expose the gas region along the planned chip division line, was then fabricated by masking and etching using a photoresist. The width of the gas region exposed by the mask structure is 55 µm. Dry etching (ICP-RIE) was performed to expose the dielectric section at the edge of the interelectrode layer within the gas region and also to expose a side surface from the p-type InP cladding layer to the n-type InP cladding layer. The etching conditions were set to dry etching with a table temperature of 200 °C, a pressure of 0.2 Pa, a bias power of 150 W, an ICP power of 190 W, an over-etch rate of 5%, and a gas ratio of SiCl4:Ar = 4:8.

[0061] After mesa formation, the SiO₂ mask present on the top surface of the ohmic electrode and the contact electrode was removed. SiN was then deposited as a protective film over the entire surface (including the top surface of the remaining SiO₂ mask, the exposed side surface of the semiconductor laminate, and the gas region) using plasma-CVD. A photoresist mask was then used to remove the SiN from the top surface of the contact electrode by etching, and the photoresist was subsequently removed. The SiN thickness is 190 µm. Next, a rear surface of the support substrate was ablated by grinding or etching, resulting in a total thickness of 150 µm for the light-emitting semiconductor device.Next, a rear-surface Ohm electrode (Ti (thickness: 10 nm) / Pt (thickness: 50 nm) / Au (thickness: 200 nm)) was formed on the rear surface of the support substrate by vapor deposition and subjected to a 60-second heat treatment at 300 °C using RTA. Finally, individual square elements with a chip size of 250 µm × 250 µm were separated by laser sectioning, thus producing a light-emitting semiconductor element according to Example 1. (Example 2)

[0062] A light-emitting semiconductor element according to Example 2 was obtained in the same way as in Example 1, except that the etching conditions for mesa formation were set as dry etching with a table temperature of 200 °C, a pressure of 0.2 Pa, a bias power of 150 W, an ICP power of 190 W, an over-etch rate of 5 % and a ratio of the type of gas used of SiCl4:Ar = 7:14. (Example 3)

[0063] A light-emitting semiconductor element according to Example 3 was obtained in the same way as in Example 1, except that the etching conditions for mesa formation were set as dry etching with a table temperature of 200 °C, a pressure of 0.25 Pa, a bias power of 100 W, an ICP power of 190 W, an over-etch rate of 5 % and a ratio of the type of gas used of SiCl4:Ar = 9:20. (Comparative example 1)

[0064] A light-emitting semiconductor element according to Comparative Example 1 was obtained in the same manner as in Example 1, except that the etching process for mesa formation was set to wet etching with Br-MeOH as the etchant and an immersion time of 20 minutes, and that the top surface and the side surface of the semiconductor laminate were subjected to surface roughening by wet etching immediately after mesa formation without performing the top surface roughening described above. (Comparative example 2)

[0065] A light-emitting semiconductor element according to Comparative Example 2 was obtained in the same way as in Example 1, except that the etching conditions for mesa formation were set as dry etching with a table temperature of 200 °C, a pressure of 0.25 Pa, a bias power of 100 W, an ICP power of 190 W, an over-etch rate of 10 % and a ratio of the gas used of SiCl4:Ar = 9:20. (Comparative example 3)

[0066] A light-emitting semiconductor element according to Comparative Example 3 was obtained in the same way as in Example 1, except that the etching conditions for mesa formation were set as dry etching with a table temperature of 200 °C, a pressure of 0.2 Pa, a bias power of 150 W, an ICP power of 190 W, an over-etch rate of 15 % and a ratio of the gas used of SiCl4:Ar = 7:14. (Comparative example 4)

[0067] A light-emitting semiconductor element according to Comparative Example 4 was obtained in the same manner as in Example 1, except that the etching conditions for mesa formation were set to dry etching with a table temperature of 200 °C, a pressure of 0.25 Pa, a bias power of 100 W, an ICP power of 190 W, an over-etch rate of 15%, and a gas ratio of SiCl4:Ar = 9:20. The etching procedure and conditions for mesa formation in Examples 1 to 3 and Comparative Examples 1 to 4 are shown below in Table 1. [Table 1] Etching process in mesa formation Table temperature Pressure [Pa] Preload power [W] ICP[W] Over-etch rate [%] Gas type (SiCl4:Ar) Example 1 Dry etching 200 °C 0,2 150 190 5 4:8 Example 2 Dry etching 200 °C 0,2 150 190 5 7:14 Example 3 Dry etching 200 °C 0,25 100 190 5 9:20 Comparative example 1 Wet sets Etching agent: Br-MeOH, immersion time: 20 min Comparative example 2 Dry etching 200 °C 0,25 100 190 10 9:20 Comparative example 3 Dry etching 200 °C 0,2 150 190 15 7:14 Comparative example 4 Dry etching 200 °C 0,25 100 190 15 9:20

[0068] A cross-sectional SEM image was acquired for each of examples 1 to 3 and comparison examples 1 to 4. In each cross-sectional SEM image, the shape of a principal side surface, the angle θ, the curvature, the presence or absence of an indentation on a side surface of the active layer, and the separation distance between a first straight line and a second straight line were measured. Fig. 3A to 5 correspond to examples 1 to 3 and the Fig. Examples 6 to 9B correspond to comparison examples 1 to 4. The acquisition of the cross-sectional SEM image was performed by acquiring an image at an accelerating voltage of 5 kV using a FE-SEM JSM7000F, manufactured by JEOL Ltd., as described above. Fig. 3A, Fig. 4, Fig. 5, Fig. 6, Fig. 7A, Fig. 8 and Fig. Figure 9A are SEM cross-sectional images of completed elements. In addition, the angle θ and curvature were measured using the image measurement software "IC Measure," produced by The Imaging Source, as described above. Furthermore, for elements after mesa formation and before protective film formation in Example 1, Example 3, Comparison Example 2, and Comparison Example 4, a SEM image of a major side surface of the semiconductor laminate was acquired, as described in the Fig. 3B, Fig. 7B and Fig. Figure 9B shows that an FE-SEM JSM7000F was used to perform an EDS analysis of the main side surface at an accelerating voltage of 10 kV. In the EDS analysis, 10 equally spaced locations along one thickness direction of the main side surface were measured. Of these measurement points, those located within half the thickness of a second conductor type layer on one side of the active layer were excluded, and average wt% values ​​of silicon atoms and oxygen atoms were calculated for measurement points from within the first conductor type layer to half the thickness of a second conductor type layer on one side of the active layer, including the side surface of the active layer. Furthermore, the amount of deposition on the side surface of the active layer was evaluated using the wt% of silicon atoms as determined by the EDS analysis.Furthermore, using an LED tester (model number: LX4730A) manufactured by YAC Garter Co., Ltd., as described above, a wafer was inserted into a probe / testing device prior to singulation. A probe was positioned against a contact electrode on the top side of the element, and a current of 0.1 µA was applied to measure the reverse voltage (Vr). 5000 measurements were taken, and an average value was used as the reverse voltage (Vr) value. Results of the above are shown in Table 2. [Table 2] indentation EDS surface analysis Reversing current characteristics Presence of an indentation Separation distance [µm] Deposition on the surface on the side of the active layer From the p-type mantle layer to the center of the n-type mantle layer (average value) Vr (at 0.1 µA)[V] Etching process in mesa formation Mesaform angle θ[°] Curvature [µm] -1 ] Number of Si atoms Si atoms [wt.%] O atoms [wt.%] Example 1 Dry etching Normal cone 77,0 0,015 No 0,00 Small amount 4,1 2,0 5,4 21,0 Very good Example 2 Dry etching Normal cone 83,1 0,048 No +0,17 Small amount - - - 20,7 Good Example 3 Dry etching Normal cone 80,3 0,074 No 0,00 Small amount 4,9 2,5 7,1 20,9 Good Comparative example 1 Wet sets Normal cone 81,5 0,249 Yes -0,43 No No No Unknown 14,0 Very bad Comparative example 2 Dry etching Normal cone 85,2 0,210 No +0,13 Low to medium 5,5 2,8 7,9 19,8 Bad Comparative example 3 Dry etching Slightly perpendicular 89,6 0,100 No +0,17 Strong - - - 18,8 Bad Comparative example 4 Dry etching Inverted cone 91,5 0,127 No +0,17 Strong 7,3 4,1 11,2 18,2 Bad

[0069] As shown in Table 2, when a first line, externally tangential to the side surface of the layer of a first conductor type and the side surface of the layer of a second conductor type near the active layer, and a second line, parallel to the first line and contacting the side surface of the active layer, were drawn in the SEM cross-sectional images of Examples 1 to 3 and Comparison Examples 1 to 4, and the separation distance between the first line and the second line was confirmed, in Comparison Example 1 ( Fig. 6) The second line, with a separation distance of 430 nm, is located further inward than the first line. However, in examples 1 to 3 and comparison examples 2 to 4, the second line was located further outward than the first line or had a separation distance of zero. It should be noted that the separation distance is given as a negative value when the second line is located further inward than the first line and a depression is formed, whereas the separation distance is given as a positive value when the second line is located further outward than the first line and a protrusion is formed.

[0070] Table 2 confirms that when mesa formation and surface roughening are performed by wet etching, the side surface of the active layer is significantly etched, resulting in indentation and poor reverse current characteristics in a light-emitting semiconductor device. Conversely, it confirms that although an indentation does not form when mesa formation is not performed by dry etching and surface roughening of a major side surface, this alone is insufficient to improve the poor reverse current characteristics of a light-emitting semiconductor device. If the over-etching time is short, the etching time for exposed SiO₂ is short, side etching on the substrate side progresses, and an angle θ of not less than 70° and not more than 85° is obtained.In contrast, if the over-etch time is long, the etch time for exposed SiO2 is also long, side etching on the substrate side progresses, and the angle θ becomes nearly perpendicular. Table 2 confirms that the angle θ is closer to perpendicular and the deposition rate increases when the over-etch time is increased under dry etching conditions. It has been confirmed that a light-emitting semiconductor device with a high reverse voltage (Vr) can be fabricated to optimize the over-etch time (rate) by setting the angle θ to no less than 70° and no more than 85°. [Table 3] Number of measured chips Average value (V) Standard deviation (V) Example 1 5046 21,0 0,49 Example 2 5045 20,7 0,40 Example 3 5045 20,6 0,24 Comparative example 1 - - - Comparative example 2 5031 19,8 1,20 Comparative example 3 5045 18,8 1,01 Comparative example 4 5044 18,2 1,59

[0071] Table 3 shows the number of chips measured, the mean value (V), and the standard deviation (V) for the reverse voltage (Vr) when a reverse current of 0.1 µA was applied to the light-emitting semiconductor elements of Examples 1 to 3 and the comparison examples 2 to 4. It was confirmed that Examples 1 to 3 not only exhibit a mean value greater than 20 V but also a low standard deviation. This demonstrates that high-yield production is possible when etching during mesa formation is carried out under the conditions described in this disclosure. REFERENCE MARK LIST 1 Light-emitting semiconductor element 10 Growth substrate 20 Buffer layer 30 Etch stop layer 40 layers of a second conductor type 50 Active shift 60 layers of a first conductor type 70 protective film 80 Inter-electrode layer 81 ladder section 82 Dielectric section 91 Reflective layer 92 Metal compound layer 160 Ohm electrode of the rear surface 170 Ohm electrode of the upper surface and contact point electrode 190 carrier substrate 200 semiconductor laminate QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2018-182154 A

[0003] JP 2021-77885 A

[0003] JP 2022-101468 A

[0003] < / zwischenelektrodenschicht> < / halbleiterschichten> < / einbuchtung>

Claims

[1] Light-emitting semiconductor element comprising: a reflective layer formed on a support substrate; an intermediate electrode layer formed on the reflective layer; a layer of a first conduction type formed on the intermediate electrode layer; an active layer formed on top of a first conductor type layer; and a layer of a second conductor type formed on the active layer, wherein the intermediate electrode layer is formed from a dielectric section and a conductor section, and an edge of it is the dielectric section, the dielectric section is located further outwards than a side surface of a semiconductor laminate comprising the layer of a first conduction type, the active layer and the layer of a second conduction type, and in a cross-section of the semiconductor element, If a first line is drawn that is externally tangential to a side surface of a layer of a first conduction type and a side surface of a layer of a second conduction type near the active layer, and a second line is drawn that is parallel to the first line and contacts a side surface of the active layer, and the second line is located further outwards than the first line, the separation distance between the first line and the second line is zero, or the second line is located further inwards than the first line with a separation distance between them of 10 nm or less, and a third straight line connecting a contact point of the interelectrode layer and the side surface of the layer of a first conduction type and a contact point on a side of the layer of a first conduction type of the first straight line, forming an angle of not less than 70° and not more than 85° relative to a top surface of the interelectrode layer on a side where the layer of a first conduction type is located. [2] Light-emitting semiconductor element according to claim 1, wherein the active layer contains one or two or more of Al, Ga and In as elements of group III and one or two or more of As, Sb and P as elements of group V, and the layer of a first conductor type contains one or two or more of Al, Ga and In as elements of group III and contains one or two or more of As, Sb and P as elements of group V. [3] Light-emitting semiconductor element according to claim 1, wherein a blocking voltage when a blocking current of 0.1 µA is applied is 20 V or more. [4] Light-emitting semiconductor element according to claim 1, wherein a line along the side surface of the layer of a first conductor type, connecting an upper end and a lower end of the side surface, has a curvature of not less than 0 and not more than 0.

11. [5] Light-emitting semiconductor element according to claim 1, wherein the dielectric section is SiO2 or SiN. [6] Light-emitting semiconductor element according to claim 1, wherein the weight fraction of Si atoms on a side surface from an interface between the dielectric section and the layer of a first conduction type to a thickness center of the layer of a second conduction type is 2.5 wt.% or less. [7] Light-emitting semiconductor element according to claim 1, wherein the dielectric section is SiO2 and the weight fraction of O atoms on a side surface from an interface between the dielectric section and the layer of a first conduction type to a thickness center of the layer of a second conduction type is 7.5 wt.% or less. [8] Method for producing a light-emitting semiconductor element, comprising: a step in the formation of an etch stop layer on a growth substrate; a step in forming a layer of a second conductor type on the etch stop layer; a step in forming an active layer on top of the layer of a second conductor type; a step in forming a layer of a first conductor type on the active layer; a step of forming an intermediate electrode layer, which consists of a dielectric section and a conductor section, and has an edge which is the dielectric section, on the layer of a first conductor type; a step in the formation of a reflective layer on the interelectrode layer; a step in the formation of a metal compound layer on a support substrate; a step of joining the reflective layer and the metal compound layer; and a step of removing the growth substrate, whereby The process further comprises a mesa formation step of removing a semiconductor laminate from the layer of a second conductor type to the layer of a first conductor type by dry etching along a planned chip division line, thereby forming a side surface of the semiconductor laminate, and in a cross-section of the semiconductor element, if a first line, which is externally tangential to a side surface of the layer of a first conduction type and a side surface of the layer of a second conduction type near the active layer, and a second line, which is parallel to the first line and contacts a side surface of the active layer, are drawn, the second line is located further outwards than the first line, the separation distance between the first line and the second line is zero, or the second line is located further inwards than the first line with a separation distance between them of 10 nm or less, and a third straight line connecting a contact point of the interelectrode layer and the side surface of the layer of a first conduction type and a contact point on a side of the layer of a first conduction type of the first straight line, forming an angle of not less than 70° and not more than 85° relative to a top surface of the interelectrode layer on a side where the layer of a first conduction type is located. [9] Method for producing a light-emitting semiconductor element according to claim 8, wherein the over-etch rate during dry etching is not less than 1% and not more than 9%. [10] Method for producing a light-emitting semiconductor element according to claim 8, wherein the weight fraction of Si atoms on a side surface from an interface between the dielectric section and the layer of a first conductor type to a thickness center of the layer of a second conductor type immediately after the mesa formation step is 2.5 wt.% or less.

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