TDI LINE SENSOR AND METHOD FOR OPERATING A TDI LINE SENSOR

Description

[0001] The invention relates to a TDI line sensor and a method for operating a TDI line sensor.

[0002] Particularly in the field of high-resolution satellite remote sensing, TDI CCD sensors currently represent the best technology for meeting the requirements of low ground resolution, high scanning speed, and high signal-to-noise ratio. A key aspect is time-delay integration (TDI), i.e., the synchronous shifting of charges within the CCD to compensate for satellite motion. Until now, TDI CCD sensors were implemented using NMOS technology, but novel approaches in CMOS technology are opening up new possibilities in terms of integration density and sensor functionality. The sensor is controlled by CCD control signals. The CCD control signals include, among others, shift clocks for TDI charge transport and clocks for CCD readout (reset, transfer gate, summing well). These signals are generated in a digital unit that runs at a system period.The CCD control signals exhibit a periodicity, allowing continuous lines to be recorded. The period length is typically in the µs range, whereas the system period, derived from the system clock frequency (system frequency), is in the 10 ns range. The period of the CCD control signals is a multiple of the system period. Synchronous movement is ensured by adjusting the period of the CCD control signals. If the relative speed changes, for example, because the satellite changes its orbit, the control signal is adjusted, i.e., its period is changed. The edge or edge steepness is rigidly defined by an electrical circuit (e.g., an RC filter).

[0003] From US 2007 / 064135 A1 a TDI line sensor is known, wherein the TDI line sensor has n TDI lines, at least one readout electronics and a circuit arrangement for generating CCD control signals for the TDI lines, wherein the period of the CCD control signals is an integer multiple of a system period, wherein all TDI lines are controlled with the same CCD control signal.

[0004] The invention is based on the technical problem of creating an improved TDI line sensor and providing a corresponding method for operating a TDI line sensor.

[0005] The solution to the technical problem is provided by a TDI line sensor having the features of claim 1 and a method having the features of claim 7.

[0006] Further advantageous embodiments of the invention emerge from the subclaims.

[0007] For this purpose, the TDI line sensor comprises n TDI lines, at least one readout electronics, and a circuit arrangement for generating CCD control signals for the TDI lines, with the period of the CCD control signals being integer multiples of the system period. All TDI lines are controlled simultaneously with the same CCD control signal.The TDI line sensor is designed such that an optimal period of the CCD control signals is calculated based on the relative speed to an object to be observed. The optimal period is not an integer multiple of the system period. The period of the CCD control signals is changed as an integer multiple of the system period during integration across all n TDI lines in such a way that the arithmetic mean of the period of the CCD control signals over the n integration steps corresponds to the optimal period. The change in the period of the CCD control signals over the n integration steps is limited to one system period. This significantly improves the achievable image quality, especially with many TDI lines and with small periods.

[0008] In one embodiment, the TDI line sensor is configured to calculate a period pattern over x integration steps, whereby the arithmetic mean over the x integration steps corresponds to the optimal period, whereby the period pattern is repeatedly applied over the n integration steps. Here, x ≤ n applies. If, for example, the calculation of the optimal period shows that this should be 1,000.25 clock lengths of the system period, then, for example, a CCD drive signal with 1,000 clock lengths of the system period is generated three times, followed by a CCD drive signal with 1,001 clock lengths of the system period. In this case, x is 4. This pattern is then repeated. With 256 TDI lines, this corresponds to 64 times.

[0009] In a further embodiment, the circuit arrangement is configured to additionally vary the edge steepness of the CCD drive signals, with the edge steepness being reduced as the period increases. This further improves image quality because higher-contrast partial images are generated.

[0010] The adaptation of the edge steepness can also be used for state-of-the-art TDI sensors in which the period of the CCD control signals is constant over the n integration steps, but the respective period changes depending on the relative speed.

[0011] In one embodiment, the circuit arrangement is designed to generate linear edges (ramps), which has further advantages compared to the exponential edges (due to the RC elements) of the prior art, in particular with regard to the tracking of the edge steepness.

[0012] In one embodiment, the circuitry is implemented as an FPGA or ASIC, allowing for very fast tracking. The calculation of the CCD control signals is therefore performed entirely in hardware, without a microprocessor.

[0013] In another embodiment, a digital-to-analog converter is arranged at the output of the circuit arrangement. The digital-to-analog converter can be implemented as a separate component or integrated into the FPGA or ASIC.

[0014] The invention is explained in more detail below using a preferred embodiment. The figures show: Fig. 1 is a highly simplified block diagram of a TDI line sensor, Fig. 2a is a curve of a control signal for a first relative speed (prior art), Fig. 2b is a curve of a control signal for a second relative speed (prior art), Fig. 3a is a curve of a control signal according to the invention for a first relative speed, Fig. 3b is a curve of a control signal according to the invention for a second relative speed, Fig. 4 is a detailed representation of part of a control signal, Fig. 5 is a detailed representation of part of a control signal at a changed relative speed and Fig. 6 is a schematic representation of a circuit arrangement for generating the control signals.

[0015] In the Fig. 1is a highly simplified block diagram of a TDI line sensor 1 which has n TDI lines 2.1-2.n, at least one readout electronics 3 and a circuit arrangement 4 for generating CCD control signals TL (hereinafter referred to as control signals) for the n TDI lines 2.1-2.n, wherein the circuit arrangement 4 is operated with a system frequency f S or system period Ts and receives a relative speed V as an input variable.

[0016] Before the invention is explained in more detail, the state of the art will first be discussed with reference to Fig. 2a and 2b briefly explained. Fig. 2a a control signal for a first relative speed is shown, with the values ​​plotted on the x-axis Steps represent the clock lengths of the system period Ts. The edges of the control signal rise and fall exponentially (due to the RC filter). Fig. 2bthe control signal is shown for a second relative speed which is smaller than the first relative speed, so that the period of the control signal is longer, but the steepness of the edges remains the same.

[0017] In the Fig. 3a and 3b the control signals are shown in an embodiment according to the invention, wherein on the one hand the edges rise and fall linearly and on the other hand the edges rise or fall less steeply with longer periods of the control signals.

[0018] An algorithm implemented in the circuit arrangement is intended to generate the waveform depending on the period T of the control signal itself, which can now be determined using the Fig. 4 and 5explained. If the period changes from T to T1, Ox and Ex should adjust accordingly. The period T represents the length in cycles of the system period Ts. This period T does not have to be an integer. A fixed-point representation is permitted, which creates digital jitter, which, in the context of desynchronization, greatly improves the system's performance, which will be explained in more detail later. Oy is the start level in digital numbers (DN). Gy is the change in the level over the ramp runtime in DN. Ox represents the start point of the ramp over the period. Since the period can change, a relative measure must be defined here. Ox should have a fixed-point representation with values ​​in [0,1]. The start time is then the product of the period and this value. EX defines the end time of the ramp. Just like Ox, this value is defined relative to the period, i.e., the value must be in the range [0,1]. The following applies: Ex 1 = T 1 T ⋅ Ex as well as Ox 1 = T 1 T ⋅ Ox .

[0019] The time axis is divided into discrete units, the clock cycles, of the system period Ts. Only the case of a rising ramp is discussed here; the subsequent falling edge is covered by the same algorithm, but with adjusted parameters.

[0020] The algorithm is characterized by a particularly good implementability in hardware structures, such as FPGA or ASIC. The basic structure is in Fig. 6shown. A new output value, the ramp value, must be calculated per clock cycle. Due to the high speed and the hardware implementation, this algorithm does not use true multiplications. These would require a lot of space, i.e., area in the FPGA or ASIC, and also reduce speed. Multiplication and integer division by powers of 2 are permitted, since these are not operations in hardware due to the binary representation, meaning they can be implemented entirely without additional effort.

[0021] Period T, Level Oy, Level Change Gy, Oy and Ex represent the five initialization values.

[0022] The following digital integer hardware representations are derived from these five values. Two bases must be defined: Period_Basis and Point_Basis. These define the accuracy of the ramp representation. Unlike the initialization parameters, which can be changed at runtime, the bases cannot be changed at runtime. They are fixed by the hardware. The calculation of these values ​​also involves multiplication and division, which is acceptable, however, since these values ​​only need to be calculated for configuration purposes. The calculation itself can be performed on a processor that is located upstream of the CCD control. Period_N = Period * 2^ Period_basis StartPoint_N = 2^ Point_basis / Ox StopPoint_N = 2^ Point_basis / StopPoint Level_N = 2^ Point_basis * Gy / (Ex-Ox)

[0023] Additionally, the following variables are required: variable remark Init value State defines the current state (0, 1, 2) 0 Level defines the current output value 0 ErrorPeriod Residual errors in the period 0 ErrorStart Residual error at the starting point 0 ErrorStop Residual error at the endpoint 0 ErrorLevel Residual errors in the level 0

[0024] The output value Level is now calculated per clock cycle using the following algorithm ErrorPeriod += 2**Period_Basis ErrorStart += StartPoint_N*2**Period_Basis ErrorStop += StopPoint_N*2**Period_Basis ErrorLevel += Level_N*2**Point_Basis if state == 0: level = Oy if ErrorStart > Period_N*2**Point_Basis: ErrorLevel = 0 state = 1 if state == 0 or state == 1: if ErrorStop > Period_N*2**Point_Basis: state = 2 ErrorStop = 0 if state == 1: if ErrorLevel > Period_N*2**Period_Basis: ErrorLevel -= Period_N*2**Period_Basis level += 1 if state == 2: level = Oy+Gy if ErrorPeriod > Period_N: ErrorPeriod -= Period_N state = 0 ErrorStart = 0 ErrorStop = 0 ErrorLevel = 0 level = Oy

[0025] The algorithm only works if the ramp is no steeper than 45°, i.e., Ex-Ox > Gy. If this cannot be met by the application, the ramp can also be adjusted by an additional scaling S so that the above inequality is always satisfied: Gy -> Gy / S.

[0026] The algorithm can also be used for the pure generation of digital levels, i.e., 0, 1. Then Gy is only 1, and the ramp changes abruptly from 0 to 1 or vice versa.

[0027] In the Fig. 6 the circuit arrangement 4 is shown, wherein the circuit arrangement 4 has a module 5 for implementing the algorithm and a digital-analog converter 6, at the output of which the control signals TL for the TDI lines 2.1-2.n (see Fig. 1). The variables and register values ​​V / R are fed back from the output of block 5 to the input. The block also receives the five initial values, the system frequency f S (system clock with system period TS ), and, if necessary, a reset signal.

[0028] Finally, the effect of digital jitter on the period or control clock will be explained.

[0029] In case of uniform smearing, the degradation MTF is defined by: MTF k = sinc πk Δ x

[0030] With Δ x the offset of the recording. If Δ x = 0, no desynchronization takes place and the MTF is frequency-independent and equal to 1. In the case that Δ x = g where g is the Ground Sampling Distance, the Nyquist frequency of k n = 1 2 g MTF k n = sinc πk n g = sinc π 2 = 2 π ≈ 63.7 %

[0031] This is the well-known degradation of non-TDI sensors in remote sensing.

[0032] In the case of a focal plane, the integration time is limited in resolution by the internal clock generation. Clocks in the range of 10 ns to 40 ns are expected. This limits the accuracy of the CCD control signals.

[0033] In general, in the case of a uniform speed deviation with TDI sensors, the following applies: MTF k = sinc πk v − v D T

[0034] With T the real integration time, ie the number of TDI stages multiplied by the "real" line period TL , as well as the object speed v and the TDI speed v D The line period corresponds to the period of the control signals discussed above. MTF k = sinc πk v − v D N T L

[0035] The velocities can now be expressed by the line period (all in the detector plane): MTF k = sinc πkp 1 T L − 1 T D N T L MTF k = sinc πkp 1 − T L T D N

[0036] With p the pixel pitch and TDthe adjustable line period. Due to the limitation of the line period's accuracy, the difference will not cancel itself out in most cases. The "true" line period TL can be expressed by the row period and a correction term: T L = T D − ϵ

[0037] Where ε is within the range of the FPA clock period. This change results in: MTF k = sinc πkpN ϵ T D

[0038] To avoid significant desynchronization, the sinc term should not be greater than 0.1 (TBC). This results in ε : ϵ T D < 0.1 2 πN

[0039] At N=256, the maximum TDI levels, the limit would be 2.5E-4. Combined with the maximum line frequency of, for example, 150kHz, i.e., a line period of 6.6µs, this results in an accuracy of less than 1.6ns. This is technically not feasible in an FPGA.

[0040] Therefore, a method is proposed in which the line period TDis not fixed. Rather, the period is varied from cycle to cycle so that the total error ε always remains smaller than one system period. In a simplified model, one can assume that the offset Δ x composed of many, not necessarily identical, offsets of the individual bars. This results in: MTF k = sinc πk Δ x MTF k = sinc πk Δ x 0 + . . + Δ x k MTF k = sinc πk v − v D 0 + ⋯ + v − v Dk T L MTF k = sinc πk Nv − v D 0 + ⋯ + v Dk T L MTF k = sinc πk Nv − p 1 T D 0 + ⋯ + 1 T Dk T L

[0041] The distribution of TD is now carried out in such a way that, on average, they have the smallest possible deviation from the required line period across the N TDI stages. Nevertheless, a residual error of ϵ N . This gives the MTF: MTF k = sinc πk Nv − p 1 T L + ϵ 1 + ⋯ + 1 T L + ϵ k T L

[0042] There ε small opposite TL is, the result can be approximated by: MTF k = sinc πk Nv − p T L 1 − ϵ 1 T L + ⋯ + 1 − ϵ k T L T L MTF k = sinc πkp N − N − ϵ 1 T L − ⋯ − ϵ k T L MTF k = sinc πkpN 1 T L < ϵ >

[0043] As already described above, the residual error of < ε > at ϵ N .This results in: MTF k = sinc πkp 1 T L ϵ

[0044] To avoid significant desynchronization, the sinc term should not be greater than 0.1. This gives ε : ϵ T L < 0.1 2 π

[0045] Regardless of the TDI level, a maximum line frequency of 150 kHz, i.e., a line period of 6.6 µs, results in an accuracy of better than 420 ns. This is technologically feasible. With an acceptable MTF degradation of 1%, this value would drop to 42 ns, which can still be achieved in the FPGA.

[0046] With this approach, the resolution of the line period is no longer specified in multiples of the system period Ts, but rather by the system period Ts divided by the TDI steps. This ensures that < TL > can be adjusted with the desired accuracy. Example

[0047] TDI steps = 256 at 100 MHz (10 ns). This allows the mean line period to be set with an accuracy of 39 ps. The integration time thus has an error of 10 ns at TDI-256, as expected.

[0048] However, if fewer TDI steps are set in this system, the residual error remains at 10 ns. It cannot be reduced further because this is the smallest physical resolution. While it is possible to set a higher accuracy, the averaging only runs over the number of TDI steps, so this would not result in any additional gain in accuracy.

[0049] In the worst case, TDI=1, the increased accuracy would be completely lost. The residual error over the integration time would again be 10 ns.

Claims

1. A TDI line sensor (1), wherein the TDI line sensor (1) has n TDI lines (2.1-2.n), at least one readout electronics unit (3) and a circuit arrangement (4) for generating CCD control signals (TL) for the TDI lines (2.1-2.n), wherein the period of the CCD control signals (TL) is an integer multiple of a system period (TS), wherein all TDI lines (2.1-2.n) are controlled with the same CCD control signal (TL), characterised in that the TDI line sensor (1) is configured such that an optimum period of the CCD control signals (TL) is calculated on the basis of the relative velocity (V), wherein the optimum period is not an integer multiple of the system period, wherein the period of the CCD control signals (TL) is changed as an integer multiple of the system period (TS) during the integration over all n TDI lines (2.1-2.n) so that the arithmetic mean of the period of the CCD control signals (TL) over the n integration steps corresponds to the optimum period, wherein the change in the period of the CCD control signals over the n integration steps is limited to one system period (TS).

2. The TDI line sensor (1) according to claim 1, wherein the TDI line sensor (1) is configured so as to calculate a period pattern over x integration steps, wherein the arithmetic mean value over the x integration steps corresponds to the optimum period, wherein the period pattern is applied repeatedly over the n integration steps.

3. The TDI line sensor (1) according to claim 1 or 2, wherein the circuit arrangement (4) is configured so as to additionally change an edge steepness of the CCD control signals (TL), wherein the edge steepness is reduced as the period of the CCD control signals (TL) increases.

4. The TDI line sensor (1) according to any one of the preceding claims, wherein the circuit arrangement (4) is configured so as to generate CCD control signals (TL) with linear edges.

5. The TDI line sensor (1) according to any one of the preceding claims, wherein the circuit arrangement (4) is configured as an FPGA or as an ASIC.

6. The TDI line sensor (1) according to any one of the preceding claims, wherein a digital-to-analogue converter (6) is arranged at the output of the circuit arrangement (4).

7. A method for operating a TDI line sensor (1), wherein the TDI line sensor (1) has n TDI lines (2.1-2.n), at least one readout electronics unit (3) and a circuit arrangement (4) for generating CCD control signals (TL) for the TDI lines (2.1-2.n), wherein the period of the CCD control signals (TL) is an integer multiple of a system period (TS), wherein all TDI lines (2.1-2.n) are controlled with the same CCD control signal (TL), characterised in that the TDI line sensor (1) calculates an optimum period of the CCD control signals (TL) on the basis of the relative velocity (V), wherein the optimum period is not an integer multiple of the system period (TS), wherein the period of the CCD control signals (TL) is changed as an integer multiple of the system period (TS) during the integration over all n TDI lines (2.1-2.n) so that the arithmetic mean of the period of the CCD control signals over the n integration steps corresponds to the optimum period, wherein the change in the period of the CCD control signals over the n integration steps is limited to one system period (TS).

8. The method according to claim 7, wherein the TDI line sensor (1) calculates a period pattern over x integration steps, wherein the arithmetic mean value over the x integration steps corresponds to the optimum period, wherein the period pattern is applied repeatedly over the n integration steps.

9. The method according to claim 7 or 8, wherein, in addition, the circuit arrangement (4) changes an edge steepness of the CCD control signals (TL), wherein the edge steepness is reduced as the period of the CCD control signals (TL) increases.

10. The method according to any one of claims 7 to 9, wherein the circuit arrangement generates CCD control signals (TL) with linear edges.