METHOD FOR PROTECTING ACTIVE LAYERS OF ELECTRONIC CHIPS

Description

technical field

[0001] The invention relates to the technical field of protection of active layers of electronic chips.

[0002] The invention finds its application in particular in the protection of active layers made of type III-V material(s) for image sensors. State of the art

[0003] A chip-to-plate transfer process (“ Die-to-Wafer (in English), known from the prior art, allows for obtaining a stacking comprising successively: a support substrate; a hybrid bonding interface, having a metallic material and a dielectric material; electronic chips, assembled to the support substrate via the hybrid bonding interface, and each comprising successively an active layer, a dielectric layer and an initial substrate. US2023 / 018706 / A1 discloses a process of this type comprising the steps of forming a first encapsulation layer around the electronic chips, and of performing a grinding in such a way as to remove a part of the initial substrate of each of the electronic chips.

[0004] The transfer of an electrical signal is enabled by the hybrid bonding interface. The process then proceeds conventionally with the removal of the initial substrate, usually by grinding.

[0005] However, such removal of the initial substrate by grinding is not entirely satisfactory insofar as it is likely to: (i) degrade the active layer (in particular the flanks); (ii) leave residues of the initial substrate.

[0006] In particular, leaving residues of the original substrate can be detrimental to the performance of electronic chips in image sensor applications. Indeed, these residues will lead to spectral absorption problems. Description of the invention

[0007] The invention aims to remedy, in whole or in part, the aforementioned drawbacks. To this end, the invention relates to a method for protecting the active layers of electronic chips, comprising the following successive steps: a) using a stack comprising successively: a support substrate; a hybrid bonding interface, having a metallic material and a dielectric material; electronic chips, assembled to the support substrate via the hybrid bonding interface, and each comprising successively an active layer, a dielectric layer and an initial substrate; b) forming a first encapsulation layer around the electronic chips, the first encapsulation layer being made of a first dielectric material; c) performing a grinding so as to remove a part of the initial substrate from each of the electronic chips and retain a remaining part of said initial substrate; d) forming a second encapsulation layer around the electronic chips, the second encapsulation layer being made of a second dielectric material;e) perform a directional etch of a portion of the second encapsulation layer, extending over the remaining portion of the initial substrate of each of the electronic chips, so as to: superficially expose the remaining portion of the initial substrate of each of the electronic chips; retain the second encapsulation layer extending over the sides of the electronic chips; f) perform a selective chemical etch of the remaining portion of the initial substrate of each of the electronic chips; step f) being carried out with a chemical etching agent allowing selective etching of the remaining portion of the initial substrate with respect to the second encapsulation layer and with respect to the dielectric layer.

[0008] Thus, such a process according to the invention makes it possible to effectively protect the active layer during the removal of the initial substrate, while significantly reducing the amount of residues of the initial substrate.

[0009] The protection of the active layer against grinding performed in step c) is initially ensured by the first encapsulation layer formed in step b). The grinding performed in step c) generally leads to degradation of the edges of the first encapsulation layer. The second encapsulation layer formed in step d) effectively protects the edges of the electronic chips (and therefore the edges of the active layer) again for the subsequent steps of the process according to the invention, in particular step f).

[0010] Step e) exposes the remaining portion of the initial substrate for selective chemical etching. Step e) is a directional etching designed to preserve the second encapsulation layer to protect the edges of the electronic chips (and therefore the edges of the active layer) during step f).

[0011] Step f) allows for the efficient removal of the remaining portion of the initial substrate (less residue compared to the prior art) while keeping the active layer intact. This is because the upper part of the active layer is protected by the dielectric layer, which acts as a firestop layer. The lateral parts of the active layer are protected by the second encapsulation layer, which also acts as a firestop layer.

[0012] The method according to the invention may include one or more of the following characteristics.

[0013] According to one feature of the invention, the process includes a step g) flattening the stack obtained at the end of step f), step g) being preferably carried out by mechano-chemical polishing or by grinding.

[0014] Thus, one advantage provided is the removal of the protruding parts of the second encapsulation layer (relative to the free surface of the remaining part of the initial substrate) appearing at the end of step e).

[0015] According to one feature of the invention, the first encapsulation layer formed during step b) has a thickness between 500 nm and 2 µm.

[0016] Thus, one advantage obtained is to achieve a satisfactory compromise between protection effectiveness and operating time.

[0017] According to one feature of the invention, the first and second dielectric materials of the first and second encapsulation layers formed respectively during steps b) and d) are selected from a polyepoxide, silicon dioxide, a multilayer material comprising silicon nitride and silicon dioxide.

[0018] According to one feature of the invention, the first and second dielectric materials of the first and second encapsulation layers formed respectively during steps b) and d) are identical.

[0019] Thus, one advantage provided is the simplification of the implementation of the process.

[0020] According to one feature of the invention, the second dielectric material of the second encapsulation layer formed during step d) is identical to the dielectric layer material of the electronic chips of the stack used during step a).

[0021] Thus, one advantage is the increased options for choosing an etching agent that allows selective etching of the remaining portion of the initial substrate relative to the second encapsulation layer and the dielectric layer. In other words, the etching agent simply needs to allow selective etching between a first material (initial substrate) and a second material (second encapsulation layer and dielectric layer).

[0022] According to one feature of the invention, the electronic chips of the stack used in step a) are selected from image sensors and radio frequency chips. Other applications are of course conceivable.

[0023] According to one feature of the invention, the active layer comprises a plurality of semiconductor sublayers, each semiconductor sublayer preferably being made of a type III-V material.

[0024] According to one feature of the invention, the directional engraving carried out during step e) is a dry plasma engraving.

[0025] Thus, one advantage provided is the simplicity of implementing the process.

[0026] According to one feature of the invention: the initial substrate of the electronic chips of the stack used in step a) is made of silicon; the dielectric layer of the electronic chips of the stack used in step a) is made of silicon dioxide; the second dielectric material of the second encapsulation layer formed in step d) is silicon dioxide; the chemical etching agent with which step f) is carried out is tetramethylammonium hydroxide. Definitions

[0027] By "active layer," we mean a layer that performs the main function of the electronic chip, for example, the photosensitivity function in the case of an image sensor. By "layer," we mean a single layer or a plurality of sublayers of the same type. By "electronic chip" (" die " Or " chip In English, a substrate is an electronic component comprising a substrate (called the initial substrate) that has undergone technological steps to form said electronic component. A "substrate" is a self-supporting physical structure made of a base material from which a device can be formed for any type of application, including electronic, mechanical, and optical applications. A substrate can be a "wafer," also called a "plate" (" wafer(in English), which is generally in the form of a disc cut from an ingot of crystalline material. "Successively" means that the stacking elements are arranged one on top of the other in a defined order from bottom to top under normal operating conditions, that is, along the normal to the surface of the substrate receiving the electronic chips. "Hybrid bonding interface" refers to a contact area between the substrate and the active layer, designed to allow both direct metal-to-metal and direct dielectric-to-dielectric bonding. The contact area may include: (i) a first interconnect structure, formed on the free surface of the substrate; (ii) a second interconnect structure, on which the electronic chips are formed.

[0028] The hybrid bonding interface is then the contact surface between the first and second interconnection structures. By "interconnection structure," we mean a stack of interconnection levels, including metallic traces embedded in a dielectric material. The term "grinding" is designated by the term " grindingIn English, "directional etching" refers to anisotropic etching performed along a preferred direction, in this case, along the normal to the surface of the substrate receiving the electronic chips. "Flanges" refers to the lateral parts of the electronic chips. Each electronic chip has opposing upper and lower parts, connected by the lateral parts. "Selective etching" means that the portion of the initial substrate to be etched (i.e., the remaining portion of the initial substrate retained during step c)) can be etched during step f) without damaging the second encapsulation layer and the dielectric layer.In practice, the etching agent is generally chosen so that the etching rate of the part to be etched of the initial substrate is at least 3 times greater (preferably at least 5 times greater, more preferably at least 10 times greater) than the etching rate of the second encapsulation layer and the dielectric layer. By "chemical-mechanical polishing" (CMP for ". Chemical Mechanical PolishingIn English, "polishing" refers to a polishing process using: (i) a polishing pad, brought into contact with the free surface of the stack, the polishing pad and the free surface of the stack generally rotating about parallel axes of rotation (mechanical interaction); and (ii) a polishing solution, generally abrasive and corrosive, impregnating the polishing pad (chemical interaction). "Thickness" refers to a dimension along the normal to the surface of the substrate receiving the electronic chips. "Identical materials" refers to materials composed of the same material, although the thicknesses of these identical materials may differ. "Type III-V material" refers to a binary alloy of elements located in Group III and Group V of the periodic table of elements, respectively.The values ​​X and Y, expressed using the phrases "between X and Y" or "between X and Y", are included in the defined range of values. Brief description of the drawings

[0029] Other features and advantages will become apparent in the detailed description of different embodiments of the invention, the description being accompanied by examples and references to the accompanying drawings. Figure 1 is a schematic cross-sectional view, illustrating step a) of a process according to the invention. Figure 2 is a schematic cross-sectional view, illustrating step b) of a process according to the invention. Figure 3Figure 1 is a schematic cross-sectional view illustrating step c) of a method according to the invention. This figure represents the case where the grinding performed in step c) has completely removed lateral portions of the first encapsulation layer extending over the lateral parts of the electronic chips. In practice, the grinding performed in step c) may leave a portion of the lateral parts of the first encapsulation layer extending over the lateral parts of the electronic chips. Figure 4 is a schematic cross-sectional view, illustrating step d) of a process according to the invention. Figure 5 is a schematic cross-sectional view, illustrating step e) of a process according to the invention. Figure 6 is a schematic cross-sectional view, illustrating step f) of a process according to the invention. Figure 7 is a schematic cross-sectional view, illustrating step g) of a process according to the invention.

[0030] It should be noted that the drawings described above are schematic and not necessarily to scale for the sake of readability and to simplify understanding. In particular, the interconnection structures shown are simplified and do not depict the actual interconnections of the metallic traces. The cross-sections are perpendicular to the surface of the substrate receiving the electronic chips. The dashed lines represent the hybrid bonding interface. Detailed description of the implementation methods

[0031] Identical elements or elements performing the same function will bear the same references for the different embodiments, for the sake of simplification.

[0032] One object of the invention is a method for protecting active layers 1 of electronic chips P, comprising the following successive steps: a) using a stack comprising successively: a support substrate S1; a hybrid bonding interface IC, having a metallic material and a dielectric material; electronic chips P, assembled to the support substrate S1 via the hybrid bonding interface IC, and each comprising successively an active layer 1, a dielectric layer 2 and an initial substrate S2; b) forming a first encapsulation layer E1 around the electronic chips P, the first encapsulation layer E1 being made of a first dielectric material; c) performing a grinding so as to remove a part of the initial substrate S2 from each of the electronic chips P and retain a remaining part S20 of said initial substrate S2; d) forming a second encapsulation layer E2 around the electronic chips P, the second encapsulation layer E2 being made of a second dielectric material;e) perform a directional etch of a portion of the second encapsulation layer E2, extending over the remaining portion S20 of the initial substrate S2 of each of the electronic chips P, so as to: superficially expose the remaining portion S20 of the initial substrate S2 of each of the electronic chips P; retain the second encapsulation layer E2 extending over the sides of the electronic chips P; f) perform a selective chemical etch of the remaining portion S20 of the initial substrate S2 of each of the electronic chips P; step f) being carried out with a chemical etching agent allowing a selective etch of the remaining portion S20 of the initial substrate S2 with respect to the second encapsulation layer E2 and with respect to the dielectric layer 2. Step a)

[0033] The stacking used in step a) comprises successively: a support substrate S1; a hybrid bonding interface IC, having a metallic material and a dielectric material; electronic chips P, assembled to the support substrate S1 via the hybrid bonding interface IC, and each comprising successively an active layer 1, a dielectric layer 2 and an initial substrate S2.

[0034] As a non-limiting example, the support substrate S1 can be made of silicon.

[0035] The hybrid bonding interface (IC) is a contact area between the support substrate S1 and the active layer 1 of each of the electronic chips P. The contact area is designed to allow both direct metal-to-metal and direct dielectric-to-dielectric bonding. The contact area may include: a first interconnection structure I1, formed on the free surface of the support substrate S1; a second interconnection structure I2, on which the electronic chips P are formed.

[0036] The hybrid bonding interface IC is then the contact surface between the first and second interconnection structures I1, I2. As a non-limiting example, the metallic material of the hybrid bonding interface IC can be copper. As a non-limiting example, the dielectric material of the hybrid bonding interface IC can be silicon dioxide.

[0037] As a non-limiting example, the electronic chip P, equipped with the second interconnection structure I2, can have a thickness of around 775 µm during step a).

[0038] The active layer 1, the dielectric layer 2 and the initial substrate S2 of each of the electronic chips P are advantageously derived from an advanced semiconductor-on-insulator (SeOI) substrate for " Semiconductor-on-Insulator " in English), which can notably be obtained by the technique called Smart-Cut ™< .

[0039] P-type electronic chips can be image sensors, particularly infrared sensors. The active layer 1 advantageously comprises a plurality of semiconductor sublayers, each semiconductor sublayer preferably being made of a type III-V material. By way of non-limiting example, the active layer 1 of each P-type electronic chip can successively comprise a first sublayer of indium phosphide (InP), a second sublayer of gallium arsenide (GaAs), and a third sublayer of indium phosphide (InP).

[0040] P-type electronic chips can also be radio frequency (RF) chips. Other applications are of course conceivable. Step b)

[0041] The first encapsulation layer E1 is formed in step b) around the electronic chips P. The term "around" means that the first encapsulation layer E1 extends over the top and sides of the electronic chips P. Step b) is performed using a deposition technique that allows the first encapsulation layer E1 to follow the surface topography of the electronic chips P. The deposition technique does not need to produce a so-called conformal deposit (100% conformity). In other words, the deposition technique is chosen to have a conformity ratio (the ratio between the width of the sides of the first deposited encapsulation layer E1 and its surface thickness) that allows it to follow the surface topography of the electronic chips P.As a non-limiting example, the first encapsulation layer E1 can be formed during step b) by chemical vapor deposition.

[0042] The first encapsulation layer E1 is made of a first dielectric material. The first dielectric material is advantageously chosen from a polyepoxide, silicon dioxide, a multilayer material comprising silicon nitride and silicon dioxide.

[0043] The first encapsulation layer E1 formed during step b) advantageously has a thickness between 500 nm and 2 µm. Step c)

[0044] The grinding is carried out during step c) so as to remove a part of the initial substrate S2 from each of the electronic chips P and retain a remaining part S20 of said initial substrate S2.

[0045] As a non-limiting example, the electronic chip P, equipped with the second interconnection structure I2, can have a thickness of around 10 µm after step c). Step d)

[0046] The second encapsulation layer E2 is formed in step d) around the electronic chips P. The term "around" means that the second encapsulation layer E2 extends over the top and sides of the electronic chips P. If the grinding performed in step c) did not completely remove the sides of the first encapsulation layer E1 (extending over the sides of the electronic chips P), the second encapsulation layer E2 extends over the top of the electronic chips P and the sides of the first encapsulation layer E1. Step d) is performed using a deposition technique that allows the second encapsulation layer E2 to follow the surface topography of the electronic chips P. The deposition technique does not need to produce a conformal deposit (100% conformity).In other words, the deposition technique is chosen to exhibit a conformity rate (ratio between the width of the flanks of the second encapsulation layer E2 deposited and the surface thickness of the second encapsulation layer E2 deposited) allowing the surface topography of the electronic chips P to be followed. As a non-limiting example, the second encapsulation layer E2 can be formed in step d) by chemical vapor deposition.

[0047] The second encapsulation layer E2 is made of a second dielectric material. This second dielectric material is advantageously chosen from a polyepoxide, silicon dioxide, or a multilayer material comprising silicon nitride and silicon dioxide. The second dielectric material is advantageously identical to the first dielectric material. The second dielectric material is advantageously identical to the material of the dielectric layer 2 of the electronic chips P in the stack used in step a).

[0048] The second encapsulation layer E2 formed during step d) advantageously has a thickness between 500 nm and 2 µm. Step e)

[0049] The etching carried out in step e) is a directional etching of a part of the second encapsulation layer E2, said part extending over the remaining part S20 of the initial substrate S2 of each of the electronic chips P.

[0050] Directional engraving is performed during step e) in such a way as to: superficially expose the remaining part S20 of the initial substrate S2 of each of the electronic chips P; retain the second encapsulation layer E2 extending over the sides of the electronic chips P.

[0051] The directional engraving carried out in step e) is advantageously a dry plasma engraving. Stage f)

[0052] The etching carried out during step f) is a selective chemical etching of the remaining part S20 of the initial substrate S2 of each of the electronic chips P.

[0053] Step f) is performed with a chemical etching agent allowing selective etching of the remaining part S20 of the initial substrate S2 with respect to the second encapsulation layer E2 and with respect to the dielectric layer 2.

[0054] As a non-limiting example, the electronic chip P, equipped with the second interconnection structure I2, can have a thickness of between 4 µm and 5 µm after step f). Step g)

[0055] The process advantageously includes a step g) flattening the stack obtained at the end of step f). Step g) is preferably carried out by mechano-chemical polishing or by grinding. Step h)

[0056] The process advantageously includes a step h) forming electrical contact pads, electrically connected to the hybrid bonding interface IC. The electrical contact pads can be formed on the second interconnection structure I2. By way of non-limiting examples, the electrical contact pads can be made of aluminum or a Cu / Ni / Au alloy. Example of implementation

[0057] The initial substrate S2 of the electronic chips P in the stack used in step a) is made of silicon. The dielectric layer 2 of the electronic chips P in the stack used in step a) is made of silicon dioxide. The second dielectric material of the second encapsulation layer E2 formed in step d) is silicon dioxide. The chemical etching agent used in step f) is tetramethylammonium hydroxide.

[0058] The invention is not limited to the embodiments described, but is defined solely by the attached claims.

Claims

1. Method for protecting active layers (1) of electronic chips (P) including the following successive steps: a) using a stack comprising, successively: - a carrier substrate (S1), - a hybrid bonding interface (IC) having a metal material and a dielectric material, - electronic chips (P) assembled on the carrier substrate (S1) via the hybrid bonding interface (IC), each comprising successively an active layer (1), a dielectric layer (2) and an initial substrate (S2), b) forming a first encapsulating layer (E1) about the electronic chips (P), the first encapsulating layer (E1) being made of a first dielectric material, c) removing a part of the initial substrate (S2) from each of the electronic chips (P) by grinding and preserving a remaining part (S20) of said initial substrate (S2), d) forming a second encapsulating layer (E2) about the electronic chips (P), the second encapsulating layer (E2) being made of a second dielectric material, e) performing a directional etch of a part of the second encapsulating layer (E2) extending over the remaining part (S20) of the initial substrate (S2) of each of the electronic chips (P) to: - superficially expose the remaining part (S20) of the initial substrate (S2) of each of the electronic chips (P), - preserve the second encapsulating layer (E2) extending over the flanks of the electronic chips (P), f) performing a selective chemical etch of the remaining part (S20) of the initial substrate (S2) of each of the electronic chips (P), step f) being carried out with a chemical etchant that permits selective etching of the remaining part (S20) of the initial substrate (S2) with respect to the second encapsulating layer (E2) and with respect to the dielectric layer (2).

2. Method according to Claim 1, including a step g) of planarizing the stack obtained on completion of step f), step g) preferably being carried out by chemical mechanical polishing or by grinding.

3. Method according to Claim 1 or 2, wherein the first encapsulating layer (E1) formed during step b) has a thickness of between 500 nm and 2 µm.

4. Method according to one of Claims 1 to 3, wherein the first and second dielectric materials of the first and second encapsulating layers (E1, E2) formed respectively during steps b) and d) are chosen from a polyepoxide, silicon dioxide, a multilayer material comprising silicon nitride and silicon dioxide.

5. Method according to one of Claims 1 to 4, wherein the first and second dielectric materials of the first and second encapsulating layers (E1, E2) formed respectively during steps b) and d) are identical.

6. Method according to one of Claims 1 to 5, wherein the second dielectric material of the second encapsulating layer (E2) formed during step d) is identical to the material of the dielectric layer (2) of the electronic chips (P) of the stack used during step a).

7. Method according to one of Claims 1 to 6, wherein the electronic chips (P) of the stack used in step a) are chosen from image sensors and radio frequency chips.

8. Method according to one of Claims 1 to 7, wherein the active layer (1) includes a plurality of semiconductor sublayers, each semiconductor sublayer preferably being made of a III-V material.

9. Method according to one of Claims 1 to 8, wherein the directional etch carried out during step e) is a dry plasma etch.

10. Method according to one of Claims 1 to 9, wherein: - the initial substrate (S2) of the electronic chips (P) of the stack used during step a) is made of silicon, - the dielectric layer (2) of the electronic chips (P) of the stack used during step a) is made of silicon dioxide, - the second dielectric material of the second encapsulating layer (E2) formed during step d) is silicon dioxide, - the chemical etchant used to carry out step f) is tetramethylammonium hydroxide.