Procedure and support element for the manufacture of a wafer layer

Abstract

The invention relates to a method for producing a wafer layer, comprising the following steps: A. providing a support element; B. porossing the support element on at least one surface to create a separation layer; C. applying a wafer layer to the separation layer of the support element by epitaxy; and D. separating the wafer layer from the support element, wherein steps B to D are repeated at least once, preferably several times, with the support element. The invention is characterized in that step A comprises the additional steps A1. providing a support substrate; and A2. applying a seed layer to at least one surface and at least one side face of the support substrate by epitaxy to produce the support element, wherein the seed layer (3) is applied with a layer width (9) greater than the layer thickness (8). The invention also relates to a support element for producing a wafer layer and an intermediate product.

Description

[0001] The invention relates to a method for producing a wafer layer according to the preamble of claim 1 and a support element for producing a wafer layer according to claim 12.

[0002] For large-area electronic components such as large-area lighting elements or photovoltaic solar cells, but also for mass-produced products such as semiconductor diodes, there is a need for cost-effective semiconductor wafers with high electronic quality, since the material costs of the semiconductor wafer represent a significant portion of the overall product cost in such components. Methods for manufacturing semiconductor wafers are known in which semiconductor wafers are produced from silicon blocks ("ingots") using a sawing process. This allows for the production of high-quality, especially single-crystal, semiconductor wafers. However, the manufacturing costs are high, partly due to the material loss during the sawing of the silicon blocks.

[0003] Therefore, alternative methods were developed in which a wafer layer is deposited onto a support element and subsequently detached from the support element. The detached wafer layer thus represents the semiconductor wafer for the fabrication of the electronic component.

[0004] It is known from the prior art to form a porous separating layer on a partial area of ​​a support substrate and subsequently deposit a wafer layer onto the support substrate in an epitaxial process. To detach the wafer layer from the support substrate, separation cuts are made using a laser beam, which completely penetrate the semiconductor layer and extend at least partially into the separating layer or the support substrate.

[0005] However, it has proven disadvantageous that parts of the wafer layer remain on the substrate at its edges, and these are sometimes difficult to remove. Furthermore, the separation cuts also damage the substrate or the separation layer, meaning that the substrates often cannot be reused to produce another wafer layer or must undergo extensive reprocessing, thus limiting their reusability.

[0006] An optimization of the known method for producing a semiconductor layer is known, for example, from DE 102015118042 A1. In this method, a separating layer is formed over the entire surface of at least one processing side of a support substrate before the wafer layer is applied, and the wafer layer is applied overlappingly on the processing side and on at least one edge side of the support substrate, wherein the overlapping areas of the wafer layer are removed before the wafer layer is separated from the support substrate.

[0007] Document US2013 / 0137244 A1 discloses a method and arrangement for the reuse of a carrier substrate.

[0008] The overlapping application allows the wafer layer to be completely separated from the release layer or support substrate. For the support substrate to be reusable, it is crucial that it contains no wafer layer residue after separation. To ensure this, the support substrate must also be trimmed and a few micrometers removed when separating the overlapping areas, thus reducing its lateral dimensions after each use. Once the support substrate falls below a minimum dimension, it can no longer be used for producing further wafer layers.

[0009] For industrial use, a reduction in the cost of manufacturing wafer layers is necessary, particularly through the reusability of support substrates.

[0010] The present invention is therefore based on the objective of increasing the reusability of carrier substrates and achieving a cost reduction in the production of a wafer layer.

[0011] The present invention further aims to improve the quality in the production of a wafer layer, in particular to reduce defects induced by the support substrate or the separating layer.

[0012] These and other problems are solved by a method for producing a wafer layer according to claim 1, by a support element for producing a wafer layer according to claim 12, and by an intermediate product according to claim 15. Advantageous embodiments of the method are found in claims 2 to 11; advantageous embodiments of the support element for producing a wafer layer are found in claims 13 to 14.

[0013] The inventive method for producing a semiconductor layer comprises the following process steps: A first process step A includes providing a support element. In a process step B, the support element is porosified on at least one surface to create a separating layer. In particular, the separating layer can also be formed at least partially along one or more side faces of the support element by means of porosification. In a process step C, a wafer layer is deposited onto the separating layer of the support element by epitaxy. In a further process step D, the wafer layer is detached from the support element. The method is further characterized by the fact that process steps B to D are repeated at least once, preferably several times, with the support element.

[0014] These process steps are known from the prior art. The detached wafer layer is used in particular in the manufacture of electronic components and is especially used for the production of photovoltaic solar cells.

[0015] The method according to the invention is characterized in that process step A comprises the further process steps A1 and A2, wherein in process step A1 a carrier substrate is provided and in process step A2 a seed layer is applied to at least one surface and at least one side surface of the carrier substrate by means of epitaxy to produce the carrier element, wherein the seed layer is applied with a greater layer width than layer thickness.

[0016] In particular, it has been shown that with the inventive method the support element can be used several times for the production of wafer layers without any loss in the quality of the wafer layer.

[0017] In particular, the method according to the invention enables more frequent use of the carrier substrate compared to the prior art, since the epitaxial seed layer and the separation layer on the carrier substrate can be reconstructed. Provided that a minimum dimension of the carrier element is achieved, wherein the minimum dimension of the carrier element corresponds at least to the dimensions of the carrier substrate, the seed layer can be reapplied to the carrier substrate by epitaxy and the carrier element can be reprocessed. This is made possible in particular by the fact that the quality and properties of the carrier substrate, especially its dimensions, remain unchanged or are only altered to a minimal extent during the entire process.

[0018] Furthermore, the inventive method enables the carrier element, in particular the epitaxial seed layer, to be adapted to the necessary properties for subsequent process steps such as porosification. Thus, no special, often expensive, carrier substrates are required, which, due to their specific properties, often exhibit lower quality.

[0019] In particular, the epitaxial seed layer exhibits higher quality and homogeneity, especially with regard to the crystal structure and electronic properties, compared to a support substrate produced in a zone melting or crystal growth process.

[0020] The frequent use of a support substrate in the fabrication of a variety of wafer layers allows for the use of particularly high-quality support substrates, especially with regard to crystal quality and surface finish. Defects in the crystal structure and / or surface of the support substrate directly affect the quality of the epitaxial seed layer and the wafer layer. In particular, further defects in the crystal structure of the seed layer and wafer layer can be induced by defects in the crystal structure and / or surface of the support substrate.

[0021] High-quality support substrates thus allow for higher quality in the deposition of further layers via epitaxy and enable a higher process yield. In particular, the higher costs for high-quality support substrates are amortized through the frequent use and reprocessing of the support elements based on them for the production of wafer layers, so that an overall cost reduction in wafer layer production can be achieved.

[0022] Advantageously, process steps B to D are carried out with a support element at least 10 times, preferably at least 20 times, particularly preferably at least 30 times.

[0023] In particular, a support element comprising a support substrate and an epitaxial seed layer can be used to produce wafer layers until a predetermined minimum dimension of the support element is reached or slightly undershot, particularly preferably by less than 10 µm, particularly preferably by less than 5 µm, most preferably by less than 3 µm.

[0024] The minimum dimension refers to the dimension of the support element in the lateral direction and, in particular, preferably also in the vertical direction.

[0025] In particular, the dimension of the support substrate in the lateral and especially preferably in the vertical direction can represent a minimum dimension for the support element.

[0026] Advantageously, the support element can be reprocessed when it reaches or falls below the minimum dimension and then used again as a support element for the production of wafer layers.

[0027] Preferably, the carrier element is reprocessed by carrying out process step A2 with the previously used carrier substrate.

[0028] Before repeating process step A2 on a previously used carrier element, this carrier element or the carrier substrate can be subjected to an initial preparation, so that the formation of a high-quality seed layer on the previously used carrier element can again be made possible.

[0029] In particular, the carrier element or carrier substrate provided for reuse can be prepared by mechanical treatment such as polishing or grinding or chemical treatment such as etching or a combination of chemical and mechanical treatment before process step A2, so that it has a high-quality surface on which the seed layer is subsequently applied.

[0030] Reprocessing the support element allows for significantly more frequent use of the original support substrate in wafer layer production. In particular, this more frequent use enables the utilization of higher-quality support substrates, thereby simultaneously improving the quality of the wafer layers. While higher costs are associated with a higher-quality support substrate, the cost of producing each individual wafer layer is reduced due to the more frequent use of the support substrate, especially through the reprocessing of the support element itself.

[0031] The epitaxy of the seed layer and the wafer layer is preferably performed in the same epitaxy device. Alternatively, the seed layer and the wafer layer can also be performed in different epitaxy devices.

[0032] Preferably, a support substrate is used in a support element for the production of at least 50, preferably at least 100, particularly preferably at least 150 wafer layers.

[0033] In particular, the carrier substrate can have a smooth, ground, or polished surface. This can further improve the quality of the epitaxial seed layer and the wafer layer.

[0034] Overall, the inventive method can improve the quality of the wafer layers, particularly with regard to the crystal structure and electronic properties, while simultaneously reducing manufacturing costs through the reusability and reproducibility of the support element.

[0035] The epitaxial seed layer and the epitaxial wafer layer are deposited by chemical or physical vapor deposition or combinations thereof. In particular, the seed layer and wafer layer are preferably deposited by chemical vapor deposition. Epitaxy enables the production of high-quality layers, especially with regard to crystal structure and the low incorporation of impurities.

[0036] The separating layer is preferably formed as a porous layer in a manner known per se. In particular, to produce the separating layer, the support substrate is advantageously porosified in a manner known per se, especially by means of an etching process, as described for example in DE 102013219839 A1.

[0037] In a preferred embodiment of the process, the seed layer is applied to completely encase one surface and all side surfaces of the carrier substrate.

[0038] Thus, a uniform, especially homogeneous, surface made of one material can be provided as a nucleation layer for the production of the wafer layer, and defect-causing areas outside the seed layer, especially on the support substrate, can be avoided.

[0039] Furthermore, inhomogeneities during porosification in process step B can be avoided by coating the support substrate on at least one surface and all side surfaces.

[0040] In particular, the seed layer can be applied to all surfaces and sides of the carrier substrate, completely encasing it. The carrier substrate is thus entirely surrounded by the seed layer.

[0041] It has also proven advantageous that by coating the carrier substrate on at least one surface and all sides, the carrier substrate can be protected from damage, thus further increasing its reusability.

[0042] An advantageous embodiment of the process is characterized by the fact that the carrier substrate and the seed layer are or become made of silicon, germanium or gallium arsenide.

[0043] Silicon is available in high quality and large quantities, even for large-area applications, making it particularly suitable for use as a support substrate. Preferably, the seed layer on a silicon-based support material is also made of silicon, thus creating a single-material support element.

[0044] Preferably, the support substrate is only weakly doped.

[0045] Weakly doped support substrates can be produced with high quality because, due to weak doping, only a small amount of foreign substances is introduced alongside the actual doping element, which can lead in particular to errors in the lattice structure of the support substrate and induce further errors in the structure of the epitaxial seed layer.

[0046] According to an alternative embodiment of the method, the support substrate is n-doped or p-doped, wherein the doping concentration is in the range of less than 5 x 10 19 < cm -3 < , preferably in the range of less than 1 x 10 18 < cm -3 < , particularly preferably in the range of less than 1 x 10 17 < cm -3 < , most preferably in the range of 5 x 10 15 < cm -3 < .

[0047] A low doping concentration of the carrier substrate in the aforementioned range allows for a positive influence on the properties of the seedbed, especially if the seedbed is doped with the same doping element, but usually with a higher doping concentration.

[0048] The carrier substrate, due to the lower doping concentration, also has a lower concentration of other impurities, so that the seed layer and the wafer layer also have a lower impurity concentration and thus a higher layer quality.

[0049] Advantageously, the doping elements boron, phosphorus, gallium or arsenic are used to dope a support substrate made of silicon or germanium.

[0050] The conductivity of the carrier substrate is preferably below 10 ohm-cm. Preferably, the conductivity of the carrier substrate is in a range between 2 mOhm-cm and 3000 mOhm-cm, more preferably in a range of 10 mOhm-cm to 200 mOhm-cm, and particularly around 100 mOhm-cm.

[0051] A preferred embodiment of the method is characterized in that the seed layer is applied to the at least one surface of the carrier substrate with a layer thickness in the range of 10 µm to 250 µm, preferably in the range of 25 µm to 100 µm, particularly preferably in the range of 40 µm to 80 µm.

[0052] Alternatively or additionally, the seed layer is applied to at least one side surface of the carrier substrate with a layer width in the range of 10 µm to 600 µm, preferably in the range of 25 µm to 400 µm, particularly preferably in the range of 50 µm to 250 µm.

[0053] When the wafer layer is detached from the support element, particularly through trimming the wafer layer to be detached and porosity of the support element, a reduction in layer thickness and width can occur. A sufficient layer thickness allows for numerous cycles of process steps B to D to produce a wafer layer with the same support element until the minimum dimensions of the support element are reached.

[0054] For the support element to be reused, it is necessary that the previously applied wafer layer is completely removed before the next wafer layer is formed. To ensure complete removal of the wafer layer from the support element, it is therefore usually necessary to trim the support element slightly, particularly in the range of 2 µm to 20 µm, each time the wafer layer is removed.

[0055] Each time a wafer layer is removed from the support element, the support element's dimensions are slightly reduced, particularly in the range of 2 µm to 20 µm. However, it has been shown that the layer width is usually reduced more than the layer thickness during wafer layer removal. A greater layer width therefore allows for a greater number of cycles in process steps B to D until the minimum dimensions are reached for both layer width and layer thickness.

[0056] A greater layer width than layer thickness also makes it possible to trim the edges of the wafer layer, in order to separate material extending beyond the support element even before the wafer layer is detached, with a greater tolerance and correspondingly more cost-effective equipment.

[0057] According to an alternative embodiment of the method, the seed layer is n-doped or p-doped during application with a doping concentration in the range of 1 x 10 16< cm -3< to 5 x 10 19< cm -3< , preferably in the range of 1 x 10 17< cm -3< to 3 x 10 19< cm -3< , particularly in the range of 1 x 10 18< cm -3< to 1 x 10 19< cm -3< .

[0058] Doping the seed layer during epitaxy can improve its quality due to the high purity of the dopants. In particular, compared to a substrate element cut from a block produced using zone melting or crystal growth processes such as the Czochralski method, the introduction of impurities, especially metals, can be reduced by a factor of more than 10, and often by more than 50. This reduced impurity leads to increased quality of the seed layer and, consequently, of the wafer layer.

[0059] Furthermore, foreign substances can also influence the formation of the separating layer and the porosification process, so that a small amount of foreign substances also has a positive effect, especially on the uniformity of the formation of the separating layer on the surface.

[0060] Furthermore, doping the seed layer enables good electrical contact between the seed layer and the support element during porosification, which has a beneficial effect on the etching process.

[0061] Advantageously, the doping elements boron, phosphorus, gallium or arsenic are used to dope a seed layer of silicon or germanium.

[0062] The conductivity of the seedbed is preferably in a range between 2 mOhmcm and 500 mOhmcm, preferably in a range of 5 mOhmcm to 25 mOhmcm, and in particular around 15 mOhmcm.

[0063] Preferably, a contact layer is applied, formed or arranged on the surface of the carrier substrate facing away from the seed layer before, during or after the application of the seed layer.

[0064] The contact layer allows for good, and especially dry, contact with the support element, which is particularly important for the porosification process. The properties of the contact layer can be adapted to the specific conditions, independent of the properties of the support element, the support substrate, and / or the seed layer. Preferably, the contact layer has metallic or metal-like electrical properties.

[0065] An advantageous embodiment of the method is characterized by the fact that the contact layer is formed by diffusion from a diffusion layer on the surface of the carrier substrate facing away from the seed layer into the carrier substrate, wherein the diffusion layer is formed in particular by a holding element for holding the carrier substrate during process step A2 or is applied to the surface of the carrier substrate facing away from the seed layer before process step A2.

[0066] Solid-state diffusion enables the cost-effective formation of a contact layer during the production of the seedbed. Therefore, no further process steps, such as separately arranging or applying the contact layer, are necessary.

[0067] Another advantageous embodiment of the method is characterized by the fact that the contact layer is or is formed from polycrystalline semiconductor material, in particular from poly-silicon.

[0068] A polycrystalline material offers the advantage of cost-effective and good dry contacting of the support element.

[0069] Preferably, impurities, especially from the carrier substrate, can be gettered or immobilized by a polycrystalline or a highly doped contact layer, particularly one doped with the dopant element phosphorus. The quality of the seedbed can thus be further improved.

[0070] Alternatively or additionally, the contact layer is formed or arranged to protrude beyond the carrier substrate.

[0071] Preferably, the contact layer has a thickness in the range of 0.1 to 20 µm, particularly in the range of 1 to 12 µm. The thickness of the contact layer depends in particular on its function and properties; in particular, the preferred thickness of the contact layer enables good contact with the substrate element and sufficient stability.

[0072] An alternative embodiment of the method is characterized by the fact that the seed layer is applied to the carrier substrate with an inhomogeneous layer thickness, wherein, in particular, the layer thickness preferably increases or decreases towards at least one, preferably two, opposite side surfaces of the carrier substrate.

[0073] Preferably, the change in layer thickness towards the side surfaces can occur continuously from the center of the seed layer.

[0074] By creating an inhomogeneous layer thickness, inhomogeneities during the porosification process, especially inhomogeneities with respect to the applied current and the electric field, can be counteracted.

[0075] The present invention further relates to a support element for the production of a wafer layer according to claim 12.

[0076] The support element comprises a support substrate, which is formed in particular from silicon, germanium or gallium arsenide, and an epitaxial seed layer, which is applied to at least one surface and at least one side surface of the support substrate, as well as a separating layer, formed by the porosification of the at least one surface of the epitaxial seed layer, wherein the seed layer has a greater layer width than layer thickness.

[0077] Preferably, the seed layer coats one surface and all side surfaces of the carrier substrate.

[0078] In particular, the seed layer can be applied to all surfaces and all side surfaces of the carrier substrate and completely encase the carrier substrate.

[0079] The carrier substrate can thus be protected from external influences that affect the reusability of the carrier substrate.

[0080] An advantageous embodiment of the carrier element is characterized by the fact that the seed layer on at least one surface of the carrier substrate has a layer thickness in the range of 10 µm to 250 µm, preferably in the range of 25 µm to 100 µm, particularly preferably in the range of 40 µm to 80 µm.

[0081] Alternatively or additionally, the seed layer on at least one side surface of the carrier substrate has a layer width in the range of 10 µm to 600 µm, preferably in the range of 25 µm to 400 µm, particularly preferably in the range of 50 µm to 250 µm.

[0082] When the wafer layer is detached from the support element, particularly by trimming the wafer layer to be detached and by porosity of the support element, a reduction in layer thickness and width can occur. A sufficient layer thickness of the support element allows for a large number of cycles of process steps B to D to produce a wafer layer with the same support element until the minimum dimensions of the support element are reached. Advantageously, a contact layer, preferably made of polycrystalline semiconductor material, especially polysilicon, is arranged on the surface of the support substrate facing away from the seed layer.

[0083] The contact layer can be formed, in particular, by solid-state diffusion from a holding element that supports the carrier element during the production of the seed layer, or from a dopant-containing layer applied to the surface of the carrier substrate facing away from the seed layer, into the carrier substrate. This allows for cost-effective production of the contact layer without a separate process step for applying or arranging the contact layer on the carrier element.

[0084] The contact layer allows for good contact with the support element, especially during porosification.

[0085] The support element according to the invention is preferably used in the production of a semiconductor layer according to the method according to the invention, in particular an advantageous embodiment thereof.

[0086] The present invention further relates to an intermediate product in the course of manufacturing a wafer layer according to claim 15.

[0087] The intermediate product comprises a support element according to the invention as described above, in particular an advantageous embodiment of the support element, and an epitaxial wafer layer arranged on the separating layer.

[0088] The intermediate product is preferably used in the production of a semiconductor layer according to the inventive method, in particular an advantageous embodiment thereof.

[0089] Further advantageous features and designs are explained below with reference to exemplary embodiments and the figures. These show: Figures 1a to 1b show an embodiment of a method according to the invention for producing a wafer layer; Figure 2 shows an embodiment of a support element according to the invention; Figures 3a and 3b show further embodiments of a support element according to the invention;

[0090] All figures are schematic and not to scale. Within the figures, identical reference symbols denote identical or equivalent elements. Figures 1 to 3 The surface of a carrier substrate 2 or a carrier element 1, onto which a seed layer 3 is applied, is always located on top.

[0091] In the Figures 1a) to 1d ) is a method according to the invention for producing a wafer layer.

[0092] As in Figure 1aAs shown in Figure 1, a seed layer 3 was deposited on a carrier substrate 2, provided in process step A1, in process step A2 by means of epitaxy to form a carrier element 1, which is used to produce a wafer layer 5. The seed layer 3 completely encases the carrier substrate 2 on its upper surface and side surfaces. The lower side of the carrier substrate 2, facing away from the upper surface, is not covered by the seed layer 3.

[0093] The substrate 2 is a semiconductor, in particular silicon, produced using a zone melting or crystal growth process. The thickness of the substrate 2 ranges from 250 µm to 1000 µm. The substrate 2 has a square base shape with side dimensions of 100 mm to 300 mm, particularly 140 mm to 170 mm. In addition to a square base shape, the substrate 2 can also have a pseudo-square shape with chamfered / rounded corners, or a round, oval, or rectangular shape.

[0094] The carrier substrate 2 has a lateral dimension 12, to which the layer width 9 of the seed layer 3 adjoins on the side surfaces of the carrier substrate 2, so that the carrier element 1 has a total lateral dimension 11.

[0095] The seed layer 3 is applied to the surface of the carrier substrate 2 with a layer thickness of 8. The layer thickness 8 is, as in Figure 1a ) shown, essentially identical to layer width 9.

[0096] The seed layer 3 was deposited onto the support substrate 2 by epitaxy, in particular by chemical vapor deposition. Epitaxy allows for the formation of high-quality layers, which is a crucial starting point for the production of correspondingly high-quality seed layers 3. In particular, epitaxy allows the seed layer 3 to be adapted to the necessary requirements, especially with regard to crystal quality and electrical properties, for a subsequent process.

[0097] In process step B following the manufacture of the carrier element 1, a porous separating layer 4 is formed on the surface and at least partially on the side edges of the carrier element 1, and thus on the surface and at least partially on the side edges of the seed layer 3, as shown in Figure 1b The separating layer 4 has a thickness of up to 3 µm, in this case approximately 2 µm. The formation of the separating layer 4 on the support element 1 is achieved by etching, in particular porosification, and can be carried out, for example, as described in DE 10 2013 219 886 A1. The described method enables the complete formation of the separating layer 4 on the surface of the support element 1.

[0098] In a further process step C, an epitaxial wafer layer 5 is deposited on the separation layer 4 of the support element 1. The wafer layer 5 partially overlaps the side surfaces of the support element 1 and can also extend further over a portion of the side surfaces of the support element 1. The widened shape of the wafer layer 5 ensures high quality of the wafer layer 5 almost to its edge. This is in Figure 1c ) shown.

[0099] The product comprising the carrier element 1 and the wafer layer 5 is also referred to as intermediate product 10.

[0100] In a further process step, the intermediate product 10 thus produced, consisting of carrier element 1 and wafer layer 5, is trimmed at the side surfaces of the carrier element 1. This trimming removes any parts 7 of the wafer layer 5 that protrude beyond the carrier element 1, as well as any further parts of the wafer layer 5 that may be adhering to the side surfaces of the carrier element 1, as shown in Figure 1d ) shown.

[0101] Trimming is performed using a laser beam. Alternatively, trimming can also be carried out by mechanical processing such as sawing or grinding. In particular, trimming removes parts of the wafer layer 5 adhering to the carrier element 1, thus enabling reuse of the carrier element 1. However, this usually requires minimal removal of material from the side surfaces of the carrier element 1 as well, resulting in a lateral dimension 11' that is smaller than the original lateral dimension 11 after process step A.

[0102] After trimming the intermediate product 10, in a process step D the wafer layer 5 is detached from the support element 1.

[0103] After the wafer layer 5 has been detached, the carrier element 1 again goes through process steps B to D, as described in the Figures 1b to 1d ) shown, to create another wafer layer 5.

[0104] A smaller lateral dimension 11' of the support element 1 does not negatively affect the production of the wafer layer 5, provided that the support element 1 is free of residues from a previously applied wafer layer 5 and that the smaller lateral dimension 11' of the support element 1, and preferably also the thickness of the support element 11, does not fall below a minimum dimension. Therefore, a cycle of process steps B to D is repeated as often as necessary until the minimum dimensions of the support element 1 are reached or slightly undercut.

[0105] A lower limit for the minimum dimension is the lateral dimension 12 and also the thickness of the carrier substrate 2. As soon as the lateral dimension 11' approaches the lateral dimension 12 or the corresponding thickness of the carrier element 1 approaches the thickness of the carrier substrate 2, the carrier element 1 is prepared by carrying out process step A2 and the resulting reapplication of a seed layer 3 onto the carrier element 1 or the carrier substrate 2.

[0106] Before repeating process step A2 on a previously used carrier element 1, this carrier element 1 or the carrier substrate 2 can undergo initial preparation so that the formation of a high-quality seed layer 3 on the previously used carrier element 1 can again be achieved. For this purpose, the carrier element 1 or the carrier substrate 2 prepared for reuse can be treated before process step A2 by mechanical treatment such as polishing or grinding, or chemical treatment such as etching, or a combination of chemical and mechanical treatment, so that it has, in particular, a high-quality surface onto which the seed layer 3 is subsequently applied.

[0107] Provided that the dimension 11' of the support element 1 essentially corresponds to the dimensions 12 of the support substrate 2, a seed layer 3 is formed again on the previously used support substrate 2 for the reprocessing of the support element 1, so that it becomes a support element 1 with its original lateral dimension 11, as in Figure 1a ) is reprocessed. This reprocessed support element 1 is then used for the production of wafer layers 5 without having to use a new support substrate 2. By reprocessing the support element 1, a support substrate 2 can thus be used at least 50 times for the production of wafer layers 5, as shown in the Figures 1b) to 1d ) shown, used.

[0108] The layer thickness 8 and the layer width 9 of the seed layer 3 are in the range of 10 µm to 250 µm, preferably in the range of 25 µm to 100 µm, and particularly preferably in the range of 40 µm to 80 µm. A layer thickness 8 and a layer width 9 of the seed layer 3, as mentioned above, has the advantage of producing a high-quality seed layer 3, which can also be produced in a time that is acceptable for the process.

[0109] Depending on the specified parameters such as quality for the production of the wafer layer 5, the carrier substrate 2 as well as the seed layer 3 can contain doping or do without doping.

[0110] In particular, the support substrate 2 has n-doping or p-doping with a doping concentration in the range of less than 5 x 10¹⁹ cm⁻³, preferably less than 1 x 10¹⁸ cm⁻³, particularly preferably less than 1 x 10¹⁷ cm⁻³, and most preferably less than 5 x 10¹⁵ cm⁻³, in the present case p-doping using boron as the dopant with a doping concentration of 1.5 x 10¹⁶ cm⁻³. The production of doped support substrates 2 by zone melting or crystal growth processes is accompanied by the introduction of foreign substances into the crystal structure, in particular metallic, oxide, nitridic, or carbide foreign substances, as well as the formation of agglomerates, which ultimately reduces the overall quality and purity of the support substrate 2 due to foreign substances and an uneven distribution of the dopants.

[0111] The starting point for high-quality layers is already high-quality support substrates 2 and seed layers 3. Therefore, high-quality, and thus usually also high-priced, substrates should be used as support substrates 2, since the quality of the support substrate 2 ultimately has a decisive influence on the quality of the wafer layer 5. Therefore, only support substrates 2 with a low doping concentration will be used preferentially. If doped, the support substrates 2 have p-type doping, in particular with the element boron.

[0112] Due to the much more frequent use of a support substrate 2 up to 150 times or more, the higher initial costs for a higher quality support substrate 2 do not matter in the production of the large number of wafer layers 5, so that a further reduction in the costs for the production of a wafer layer 5 is achieved with improved quality.

[0113] However, it is particularly advantageous in process step B for the formation of the separating layer 4 if the support element 1 is doped. This is made possible in the present case by doping, in particular by p-doping, the seeding layer 3 on which the separating layer 4 is formed by porosity. The seeding layer has a doping concentration in the range of 1 x 1016 cm-3 to 5 x 1019 cm-3, preferably in the range of 1 x 1017 cm-3 to 3 x 1019 cm-3, and in particular in the range of 1 x 1018 cm-3 to 1 x 1019 cm-3. The present case features p-doping with boron as the dopant at a concentration of 5 x 1018 cm-3.

[0114] The epitaxial formation of seed layer 3 results in more uniform doping of the seed layer with the dopant and a significantly reduced, up to a factor of 100, introduction of foreign substances, since the dopant elements or dopants are present in a particularly high purity during epitaxy. Furthermore, the introduction of oxygen, which is partly responsible for induced stacking defects in wafer layer 5, into the crystal structure is also reduced by up to a factor of 20 due to epitaxy. The uniform doping also leads to a more uniform formation of the separation layer 4 on seed layer 3, which in turn has a positive effect on the quality of the wafer layer 5 produced on it.

[0115] In Figure 2A special embodiment of the carrier element 1 is shown. The carrier element 1 in turn has a carrier substrate 2 and a seeding layer 3, wherein the seeding layer 3 was applied to the carrier substrate 2 with a greater layer width 9 compared to the layer thickness 8.

[0116] After each production process of a wafer layer 5 in process steps B to D, the lateral dimension 11 of the support element 1 as well as the layer thickness 8 of the seed layer are reduced. The lateral dimensions 11' of the support element 1 decrease particularly due to the trimming of the wafer layer 5 or the support element 1 to ensure the complete removal of the wafer layer 5 before the production of another wafer layer 5. The layer thickness 8 of the seed layer 3 also decreases with each etching process in process step B.

[0117] Due to trimming, the lateral dimension 11 of the carrier element 1 decreases more with each wafer layer 5 than the layer thickness 8 of the seed layer 3 decreases due to porosification. In particular, the trimming of the side surfaces of the carrier element is subject to greater variation and also depends on the trimming device used. To reduce the manufacturing costs for a wafer layer 5, trimming devices are used that have a larger tolerance with regard to the material removal on the side surfaces of the carrier element 1, which is in the range of 2 µm to 20 µm, in this case approximately 5 µm. To enable the maximum possible number of cycles for producing a wafer layer 5 with a single carrier element 1 before its processing, a greater thickness 9 of the seed layer 3 compared to its layer thickness 8 is therefore advantageous.

[0118] In the Figures 3a) and 3b) each shows a carrier element 1 which has a contact layer 6 on the surface of the carrier substrate 1 facing away from the seed layer 3.

[0119] The contact layer 6 is applied to or bonded to the carrier substrate 2 by means of vapor deposition or diffusion before the application of the seed layer 3. However, applying the contact layer 6 during or after the application of the seed layer 3 is also within the scope of the invention. The application of the contact layer 6 takes place before process step B, since good contact with the carrier element 1 is important for the porosification process in process step B.

[0120] The contact layer 6 is formed from a polycrystalline semiconductor material, in particular polysilicon, which enables good dry contactability during the porosification of the support element 1. For good contactability, especially good dry contactability, the contact layer 6 exhibits electrical properties that are at least similar to those of a metal.

[0121] The lateral dimension of the contact layer 6 corresponds approximately to the lateral dimension 12 of the support substrate 2 or even exceeds the lateral dimension 12 of the support substrate 2. In particular, the lateral dimension of the contact layer 6 can also be smaller than the lateral dimension 11 of the support element 1. The thickness of the contact layer 6 is in the range of 0.1 to 20 µm, in this case approximately 10 µm, and thus significantly less than the thickness of the support substrate 2 and also less than the layer thickness 8.

[0122] As in Figure 3a As shown in the figure, the contact layer 6 has a larger lateral dimension than the support substrate 2, which is identical to the lateral dimension 11 of the support element 1. This also results in a significantly larger layer width 9 compared to the layer thickness 8. During one cycle of process steps B to D, the lateral reduction due to the trimming of the support element 1 and the subsequent detachment of the wafer layer 5 is greater than the reduction in layer thickness 8. Therefore, it is advantageous to deposit the support element 1 on the support substrate 1 with a larger layer width 9 compared to the layer thickness 8.

[0123] The full-surface formation of the contact layer 6 ensures good, and in particular dry, contact at all times, regardless of the reduction in the lateral dimensions 11 of the support element 1 after the removal of a wafer layer 5. Reference symbol list

[0124] 1 Carrier element 2 Carrier substrate 3 Seed layer 4 Separation layer 5 Wafer layer 6 Contact layer 7 Part 8 Layer thickness 9 Layer width 10 Intermediate product 11, 11' Dimension of carrier element 12 Dimension of carrier substrate

Claims

1. Method of producing a wafer layer (5), comprising the method steps of: A providing a carrier element (1); B porosifying the carrier element (1) on at least one surface for generating a separation layer (4); C epitaxially applying a wafer layer (5) to the separation layer (4) of the carrier element (1); and D detaching the wafer layer (5) from the carrier element (1), wherein the method steps B to D are repeated at least once, preferably multiple times, with the carrier element (1); wherein the method step A comprises the further method steps of A1 providing a carrier substrate (2); and A2 epitaxially applying a seed layer (3) to at least one surface and at least one lateral face of the carrier substrate (2) for the production of the carrier element (1); characterised in that the seed layer (3) is applied with a larger layer width (9) than layer thickness (8).

2. Method according to claim 1, characterised in that the seed layer (3) is applied which covers the one surface and all lateral faces of the carrier substrate (2).

3. Method according to any one of the preceding claims, characterised in that the carrier substrate (2) and the seed layer (3) are formed or have been formed from silicon, germanium or gallium arsenide.

4. Method according to any one of the preceding claims, characterised in that the carrier substrate (2) is n-doped or p-doped, wherein the dopant concentration is in a range of less than 5 × 1019 cm-3, preferably in a range of less than 1 × 1018 cm-3, most preferably in a range of less than 1 × 1017 cm-3, still most preferably in a range of less than 5 × 1015 cm-3.

5. Method according to any one of the preceding claims, characterised in that the seed layer (3) is applied on the at least one surface of the carrier substrate (2) with a layer thickness (8) in a range of 10 µm to 250 µm, preferably in a range of 25 µm to 100 µm, most preferably in a range of 40 µm to 80 µm, and / or that the seed layer (3) is applied on the at least one lateral face of the carrier substrate (2) with a layer width (9) in a range of 10 µm to 600 µm, preferably in a range of 25 µm to 400 µm, most preferably in a range of 50 µm to 250 µm.

6. Method according to any one of the preceding claims, characterised in that the seed layer (3) is doped, in particular p-doped during the application with a dopant concentration in a range of 1 × 1016 cm-3 to 5 × 1019 cm-3, preferably in a range of 1 × 1017 cm-3 to 3 × 1019 cm-3, in particular in a range of 1 × 1018 cm-3 to 1 × 1019 cm-37. Method according to any one of the preceding claims, characterised in that a contact layer (6) is applied, formed or arranged on the surface of the carrier substrate (2) facing away from the seed layer (3) before, during or after the application of the seed layer (3).

8. Method according to claim 7, characterised in that the contact layer (6) is formed or has been formed from polycrystalline semiconductor material, in particular from polysilicium, and / or in that the contact layer (6) is formed or arranged to project beyond the carrier substrate (2).

9. Method according to any one of claims 7 or 8, characterised in that the contact layer (6) has a thickness in a range of 0.1 to 20 µm, in particular in a range of 1 to 12 µm.

10. Method according to any one of claims 7 to 9, characterised in that the contact layer (6) is formed by diffusion of a diffusion layer on the surface of the carrier substrate (2) facing away from the seed layer (3) into the carrier substrate (2), wherein the diffusion layer in particular is formed by a retaining element for retaining the substrate layer (2) during the method step A2, or is applied on the surface of the carrier substrate (2) facing away from the seed layer (3) before the method step A2.

11. Method according to any one of the preceding claims, characterised in that the seed layer (3) is applied to the carrier substrate (2) with an inhomogeneous layer thickness (8), wherein in particular the layer thickness (8) increases or decreases at least towards one, preferably two opposite lateral faces of the carrier substrate (2).

12. Carrier element (1) for the production of a wafer layer (5), comprising a carrier substrate (2), in particular from silicon, germanium or gallium arsenide; an epitaxial seed layer (3), which is applied to at least one surface and at least one lateral face of the carrier substrate (2), which preferably covers one surface and all lateral faces of the carrier substrate (2); and a separation layer (4), formed by porosifying the at least one surface of the epitaxial seed layer (3), characterised in that the seed layer (3) has a larger layer width (9) than layer thickness (8).

13. Carrier element (1) according to claim 12, characterised in that the seed layer (3) on the at least one surface of the carrier substrate (2) has a layer thickness (8) in a range of 10 µm to 250 µm, preferably in a range of 25 µm to 100 µm, most preferably in a range of 40 µm to 80 µm, and / or in that the seed layer (3) is applied on the at least one lateral face of the carrier substrate (2) with a layer width (9) in a range of 10 µm to 600 µm, preferably in a range of 25 µm to 400 µm, most preferably in a range of 50 µm to 250 µm.

14. Carrier element (1) according to any one of claims 12 or 13, characterised in that a contact layer (6), preferably made of polycrystalline semiconductor material, in particular polysilicium, is arranged on the surface of the carrier substrate (2) facing away from the seed layer (3).

15. Intermediate product (10), comprising a carrier element (1) according to any one of claims 12 to 14 and an epitaxial wafer layer (5), arranged on the separation layer (4), in particular from silicium.

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