Direct memory access circuit with masking conversions

FR3172684A1Pending Publication Date: 2026-09-04COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
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Patent Information

Application Number
FR2025002110
Authority / Receiving Office
FR · FR
Patent Type
Applications
Current Assignee / Owner
Filing Date
2025-03-03
Publication Date
2026-09-04

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Abstract

Direct Memory Access Circuit with Masking Conversions This description relates to a direct memory access circuit comprising at least one data path (Ch1, Ch2, Ch3, Chs) connecting an input port of a master interface to an output port of the master interface. The at least one data path includes a first data path (Ch1). The first data path (Ch1) has a pipelined structure. The first data path (Ch1) includes a first circuit (200, 200B) configured to apply a Boolean-to-arithmetic masking conversion and an arithmetic-to-Boolean masking conversion to the data propagated by the first data path (Ch1). Figure for the abstract: Fig. 2
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