Analog-digital scheme for joint clock recovery and frame alignment

Abstract

A receiver (20) includes (i) circuitry including a clock and data recovery (CDR) loop and (ii) a frame aligner (84). The circuit is configured to apply a CDR to a signal using a CDR loop, and buffer the CDR-passed signal in a memory buffer (60). The frame aligner is configured to align the signal cached in the memory buffer with frame boundaries between consecutive frames of the signal by applying one or more shifts to the CDR loop, each shift being equal to one symbol duration of the signal.

Description

(19) State Intellectual Property Office (12) Invention Patent Application (10) Application Publication Number (43) Application Publication Date (21) Application Number 202480054978.8 (22) Application Date 2024.04.30 (30) Priority Data 63 / 581,007 2023.09.07 US (85) PCT International Application Entering National Phase Date 2026.02.26 (86) PCT International Application Application Data PCT / US2024 / 026914 2024.04.30 (87) PCT International Application Publication Data WO2025 / 053877 EN 2025.03.13 (71) Applicant: Ritek Inc. Address: California, USA (72) Inventors: Orr Nadiri, Guy Dorman, Aaron Harrell (74) Patent Agency: Beijing Anxin Fangda Intellectual Property Agency Co., Ltd. 11262 Patent Attorney Shi Chenjie Zhang Kuiyan (51) Int.Cl. H03K 5 / 135 (2006.01) H03L 7 / 07 (2006.01) (54) Invention Title Analog-Digital Scheme for Combined Clock Recovery and Frame Alignment (57) Abstract A receiver (20) includes (i) a circuit including a clock and data recovery (CDR) loop and (ii) a frame alignmentr (84). The circuit is configured to apply a CDR to a signal using the CDR loop and to buffer the signal after the CDR in a memory buffer (60). The frame alignmentr is configured to align the signal buffered in the memory buffer with frame boundaries between consecutive frames of the signal by applying one or more shifts to the CDR loop, each shift being equivalent to one symbol duration of the signal. Claims 2 pages, Description 7 pages, Drawings 5 ​​pages, CN 121753256 A 2026.03.27 CN 1 21 75 32 56 A 1. A receiver, comprising: circuitry including a clock and data recovery (CDR) loop, the circuitry being configured to apply a clock-data recovery (CDR) loop to a signal and buffer the CDR-passed signal in a memory buffer; and a frame aligner, the frame aligner being configured to align the signal buffered in the memory buffer with frame boundaries between consecutive frames of the signal by applying one or more shifts to the CDR loop, each shift being equivalent to one symbol duration of the signal.2. The receiver of claim 1, wherein: the circuitry includes a processing chain configured to sample the signal according to a sampling clock, resample the sampled signal according to a resampling phase, and buffer the resampled signal in the memory buffer; the CDR loop includes (i) a first CDR loop configured to adjust the sampling clock, and (ii) a second CDR loop configured to adjust the resampling phase; and the frame aligner is configured to align the signal buffered in the memory buffer with the frame boundary by applying one or more shifts to both the first CDR loop and the second CDR loop. 3. The receiver of claim 2, wherein the first CDR loop has a first loop bandwidth, and wherein the second CDR loop has a second loop bandwidth greater than the first loop bandwidth. 4. The receiver of claim 2, wherein the circuitry includes a numerically controlled oscillator (NCO) configured to adjust the sampling phases of the first CDR loop and the second CDR loop, and wherein the frame aligner is configured to apply the shifts by controlling the NCO. 5. The receiver of any one of claims 1-4, wherein the circuitry is configured to detect a frame synchronization sequence in the signal when the signal buffered in the memory buffer is aligned with the frame boundary, and wherein the frame aligner is configured to continue applying the shifts until the frame synchronization sequence is detected. 6. The receiver of any one of claims 1-4, wherein the frame aligner is configured to apply each of the shifts during different frames of the signal. 7. The receiver of any one of claims 1-4, wherein the frame aligner is configured to insert a wait period after every N shifts, where N is a defined integer. 8. A method comprising: applying a clock and data recovery (CDR) loop to a signal; buffering the CDR-processed signal in a memory buffer; aligning the signal buffered in the memory buffer with frame boundaries between consecutive frames of the signal by applying one or more shifts to the CDR loop, each shift being equivalent to one symbol duration of the signal; and applying further processing to the aligned signal in the memory buffer. 9. The method of claim 8, wherein: applying the CDR loop comprises (i) adjusting the sampling clock of the signal through a first CDR loop, and (ii) adjusting the resampling phase of the signal through a second CDR loop; and aligning the signal comprises applying one or more shifts to both the first CDR loop and the second CDR loop.10. The method of claim 9, wherein the first CDR loop has a first loop bandwidth, and wherein the second CDR loop has a second loop bandwidth greater than the first loop bandwidth. 11. The method of claim 9, wherein aligning the signal comprises applying the shift to a numerically controlled oscillator (NCO), the NCO adjusting the sampling phase of the first CDR loop and the second CDR loop. 12. The method of any one of claims 8-11, wherein aligning the signal comprises continuing to apply the shift until a frame synchronization sequence is detected in the signal, the frame synchronization sequence indicating that the signal cached in the memory buffer is aligned with the frame boundary. 13. The method of any one of claims 8-11, wherein aligning the signal comprises applying each of the shifts during different frames of the signal. 14. The method of any one of claims 8-11, wherein aligning the signal comprises inserting a wait period after every N shifts, where N is a defined integer. Claims 2 / 2 Page 3 CN 121753256 A Analog-Digital Scheme for Joint Clock Recovery and Frame Alignment Cross-Reference to Related Applications

[0001] This application claims the benefit of U.S. Provisional Patent Application 63 / 581,007, filed September 7, 2023, the disclosure of which is incorporated herein by reference. Field of the Invention

[0002] The present invention relates generally to communication receivers, and more particularly to methods and systems for joint clock recovery and frame alignment. Background of the Invention

[0003] Communication receivers typically perform tasks such as clock and data recovery (CDR) and frame alignment. CDR typically involves recovering a clock signal from a received signal in order to set the appropriate timing for sampling the signal. Frame alignment typically involves identifying the timing of signal frames and aligning the storage of received signals in memory with frame boundaries for further processing. Summary of the Invention

[0004] Embodiments of the invention described herein provide a receiver comprising (i) circuitry including a clock and data recovery (CDR) loop and (ii) a frame alignmentr. The circuit is configured to apply a CDR to the signal using a CDR loop and buffer the signal after the CDR in a memory buffer. The frame alignment device is configured to align the signal buffered in the memory buffer with the frame boundaries between consecutive frames of the signal by applying one or more shifts to the CDR loop, each shift being equivalent to one symbol duration of the signal.

[0005] In some embodiments, the circuit includes a processing chain configured to sample a signal according to a sampling clock, resample the sampled signal according to a resampling phase, and buffer the resampled signal in a memory buffer; the CDR loop includes: (i) a first CDR loop configured to adjust the sampling clock and (ii) a second CDR loop configured to adjust the resampling phase; and a frame aligner configured to align the signal buffered in the memory buffer with a frame boundary by applying one or more shifts to both the first CDR loop and the second CDR loop.

[0006] In the disclosed embodiments, the first CDR loop has a first loop bandwidth, and the second CDR loop has a second loop bandwidth greater than the first loop bandwidth. In an example embodiment, the circuit includes a numerically controlled oscillator (NCO) configured to adjust the sampling phase of the first CDR loop and the second CDR loop, and a frame aligner configured to apply shifts by controlling the NCO.

[0007] Typically, the circuit is configured to detect a frame synchronization sequence in the signal when the signal cached in the memory buffer is aligned with a frame boundary, and the frame aligner is configured to continue applying shifts until the frame synchronization sequence is detected. In one embodiment, the frame aligner is configured to apply each shift during different frames of the signal. In one embodiment, the frame aligner is configured to insert a wait period after every N shifts, where N is a defined integer.

[0008] Additionally, according to an embodiment of the invention, a method is provided comprising applying a Clock and Data Recovery (CDR) loop to a signal. The signal after the CDR is cached in a memory buffer. The signal cached in the memory buffer is aligned with frame boundaries between consecutive frames of the signal by applying one or more shifts to the CDR loop, each shift being equivalent to one symbol duration of the signal. The aligned signal applied to the memory buffer is further processed.

[0009] The invention will be more fully understood from the following detailed description of embodiments of the invention, taken in conjunction with the accompanying drawings. Specification 1 / 7 pages 4 CN 121753256 A In the drawings: Brief Description of the Drawings

[0010] FIG1 is a block diagram according to an embodiment of the invention, schematically illustrating a receiver using joint CDR and frame alignment; FIG2 is a block diagram according to an embodiment of the invention, schematically illustrating the buffer in the receiver of FIG1 before and after frame alignment; FIG3 is a state diagram according to an embodiment of the invention, schematically illustrating the frame alignment process; and FIG4 and FIG5 are graphs of simulation results according to an embodiment of the invention, illustrating the operating characteristics of the CDR loop in the receiver of FIG1 during joint CDR and frame alignment.Detailed Description

[0011] The embodiments of the invention described herein provide methods and apparatus for joint clock and data recovery (CDR) and frame alignment in a communication receiver.

[0012] In the disclosed embodiments, the receiver receives a signal comprising a sequence of signal frames. The receiver processes the signal, including, among other tasks, recovering the signal clock using a CDR loop. The receiver buffers the CDR-processed signal in a memory buffer for further processing (e.g., carrier phase recovery and / or bit decoding).

[0013] Each frame of the signal includes a frame synchronization sequence, such as a start-of-frame (SOF) sequence, which is used by the receiver to detect frame boundaries. To simplify subsequent processing of the signal, it is necessary to align the signal with the frame boundaries in the buffer. In other words, the signal needs to be stored in the buffer such that the frame synchronization sequence is located at a fixed predetermined position (“target position”) in the buffer.

[0014] To meet this requirement, the receiver also includes a frame aligner that aligns the signal in the buffer by controlling the CDR loop. Typically, although not mandatory, the frame aligner is implemented in software. The frame aligner performs an iterative process that shifts the timing of the signal from one frame to another by one symbol duration (one unit interval – UI). As a result of the timing shift, the position of the frame synchronization sequence in the buffer shifts by one symbol position from frame to frame. This process continues until the frame synchronization sequence reaches the target position in the buffer.

[0015] In a given iteration of this process, the frame aligner shifts the timing of the signal by 1·UI by controlling the CDR loop to apply an additional phase shift equivalent to one symbol duration. In the example implementation described in detail herein, the CDR loop is a dual loop comprising (i) a slow CDR loop that adjusts the sampling clock used to sample the signal, and (ii) a fast CDR loop that adjusts the resampling phase used to resample the signal. A numerically controlled oscillator (NCO) generates a digital phase correction word specifying the resampling phase, which in turn generates the sampling clock after additional processing. Therefore, the NCO is considered to belong to both CDR loops. The frame alignment controller (NCO) applies an additional phase bias, which is equivalent to a timing shift of 1·UI in each iteration.

[0016] When using the disclosed technique, the same CDR loop is used for both clock recovery (implemented at sub-UI resolution with 1·UI ambiguity) and frame alignment (at integer multiples of 1·UI). As will be explained and demonstrated herein, these two operations are performed simultaneously with little or no cross-influence between them. This solution minimizes the additional hardware required for frame alignment. As a result, power consumption is significantly reduced, especially in highly parallelized receiver configurations.

[0017] The disclosed technique can also be considered as a circuit that converges to sample the received signal at two different resolutions at a suitable phase: (i) a sub-UI resolution with 1·UI ambiguity based on timing error estimation, and (ii) a resolution based on frame synchronization detection, in integer multiples of 1·UI.

[0018] The disclosed technique is demonstrated below using a receiver configuration that performs frequency domain processing. Receiver operations such as frame detection (FD) and buffering are performed in multiple parallel branches. Example simulation results of the disclosed technique in such a receiver are also provided.

[0019] System Description FIG1 is a block diagram of an embodiment of the invention, schematically illustrating a receiver 20 using joint CDR and frame alignment. Receiver 20 can be used for signal reception in any suitable communication system. In an example embodiment, receiver 20 implements an 800ZR coherent optical communication protocol.

[0020] Receiver 20 receives and processes analog input signals, for example, at baseband or some low intermediate frequency (IF). The input signal comprises a sequence of symbols modulated according to a specific modulation scheme. The symbol rate is denoted as Rs. The symbol duration (1 / Rs) is also referred to as the unit interval (UI). In the example implementation associated with the 800ZR coherent protocol, Rs = 120 GBaud, although any other suitable rate may be used.

[0021] The symbols of the received signal are formatted in a frame sequence. Each frame includes a frame synchronization sequence—a sequence of several predefined symbols whose positions indicate the boundaries of the frame. The frame synchronization sequence may include, for example, a start-of-frame (SOF) sequence, an end-of-frame (EOF) sequence, or any other suitable frame synchronization sequence located at any suitable position in the frame.

[0022] The following description primarily relates to the example 800ZR coherent implementation, where each frame comprises 7296 symbols and the frame synchronization sequence is an 11-symbol SOF sequence. Alternatively, any other suitable frame and frame synchronization sequence size may be used.

[0023] In the example of FIG1, receiver 20 includes processing chain 24, which includes the following modules: - Analog-to-digital converter (ADC) 28, which samples (digitizes) the analog input signal. ADC 28 samples the input signal according to sampling clock 32. The sampling rate of ADC 28 (i.e., the rate of sampling clock 32) is m / k times higher than the symbol rate Rs (where m and k are integers, and m>k). In other words, ADC 28 samples the signal at an oversampling rate of (m / k)>1.

[0024] - First digital signal processing (DSP1) block 36, which processes the digital signal generated by ADC 28. The processing tasks of DSP1 block may include, for example, in-phase / quadrature (I / Q) imbalance compensation and filtering.

[0025] - Digital resampler 40, which resamples the output of DSP1 block 36. Resampler 40 resamples the signal according to phase correction word 44 specifying the resampled phase. In this example, the resampling rate is equal to the original sampling rate, i.e., (m / k)Rs. However, the timing of the resampled signal (the output of resampler 40) can vary relative to the timing of the original sampled signal (the output of ADC 28).

[0026] - Second DSP (DSP2) block 48, which processes the resampled signal generated by resampler 40.

[0027] - Equalizer (EQ) 52, which filters the output of DSP2 block 48 and downsamples it from the oversampling rate of (m / k)Rs to the rate of Rs (i.e., one sample per symbol).

[0028] - Frame detector (FD) 56, which detects the frame synchronization sequence (SOF in this example) in the signal. In a typical embodiment, FD 56 includes a correlator that correlates the received symbols with a known sequence of SOFs. The output of processing chain 24 is cached in memory buffer 60 for further processing.

[0029] In addition to processing chain 24, receiver 20 also includes two CDR loops. One CDR loop (referred to herein as the “fast CDR loop”) includes a timing error detector (TED) 64, a loop filter 68, and a numerically controlled oscillator (NCO) 72. The other CDR loop (referred to herein as the “slow CDR loop”) includes an additional loop filter 76 and a voltage-controlled oscillator (VCO) 80 (in addition to TED 64, LF 68, and NCO 72). Therefore, TED 64, LF 68, and NCO 72 are considered to belong to two CDR loops.

[0030] In the fast CDR loop, TED 64 outputs a phase error signal within the interval [0, 1 / Rs), i.e., with an ambiguity of one unit interval (UI). Loop filter 68 filters the phase error signal. NCO 72 generates a digital phase correction word 44 based on the filtered phase error signal (see page 3 / 7 of CN 121753256 A) to control the resampling phase. In the slow CDR loop, loop filter 76 filters the output of NCO 72. VCO 80 generates a control signal based on the output of loop filter 76 to adjust the phase of sampling clock 32.

[0031] In the example embodiment, the loop bandwidth of the fast CDR loop is approximately 100 kHz, while the loop bandwidth of the slow CDR loop is approximately 5 MHz. However, typically, any other suitable bandwidth can be used.

[0032] The slow CDR loop adjusts the phase of sampling clock 32, which the ADC 28 uses to sample the signal. In parallel, the fast CDR loop adjusts the phase correction word 44, which the resampler 40 uses to resample the signal.In other words, the resampler 40 can be viewed as interpolating between the sampling points of the ADC 28, while the fast CDR loop can be viewed as setting the interpolation phase. Both loops are designed to minimize the timing error detected by the TED 64.

[0033] This dual-loop configuration achieves high loop bandwidth and high tracking performance using the fast CDR loop. Meanwhile, the slow CDR loop removes the average timing error and focuses the phase correction value generated by the NCO 72 near zero.

[0034] To simplify the processing of the signal buffered in the buffer 60, the buffered signal needs to be aligned with the frame boundary in the buffer. In other words, the signal needs to be stored in the buffer 60 such that the SOF is located in a fixed predefined position in the buffer. In some embodiments, the receiver 20 also includes a frame aligner 84 that performs this alignment. As will be explained in detail below, the frame aligner 84 aligns the buffered signal with the frame boundary by controlling the phase correction word 44 generated by the NCO 72, which in turn affects the receiver's fast CDR loop and slow CDR loop.

[0035] Frame alignment 84 performs frame alignment in response to the "SOF detection" signal generated by FD 56. FD 56 is configured to assert the "SOF detection" signal if the SOF of the current buffered frame is located at a desired predefined position in buffer 60 (i.e., if the buffered signal is aligned with the frame boundary). If the buffered frame is not located at the desired predefined position in the buffer (i.e., if the buffered signal is not aligned with the frame boundary), the "SOF detection" signal is deasserted.

[0036] In the example implementation, DSP1 block 36 performs a Fast Fourier Transform (FFT), and DSP2 block 48 performs an Inverse FFT (IFFT). TED 64 may include, for example, a Godard frequency-domain phase detector. Resampler 40 may include, for example, a frequency-domain equalizer (FDE) that modifies the linear slope of the sampled points based on the phase correction word generated by NCO 72. This implementation is applicable, for example, to receivers that process signals in the frequency domain, such as in optical links with high dispersion (CD) distortion. In such receivers, the FDE can jointly compensate for CD and timing by changing the phase of the frequency domain sampling points. Alternatively, DSP blocks 36 and 48 and TED 64 can be implemented in any other suitable manner.

[0037] The example buffer configuration includes a detectable symbol in the buffer 60 after the timing error has been corrected by the CDR loop and downsampled equalization has been performed by equalizer 52. In particular, the known symbols of the SOF sequence are detectable. At this stage, the correlator in FD 56 is able to correctly identify whether the buffered signal is aligned with the frame boundary (i.e., whether the SOF is in the correct position in buffer 60).

[0038] FIG2 is a block diagram according to an embodiment of the present invention, schematically showing the buffer 60 of the receiver 20. The top of the figure shows the state of the buffer 60 before frame alignment, and the bottom of the figure shows the state of the buffer after frame alignment.

[0039] In this example, some or all of the processing of the signal in the receiver 20 is performed in parallel. In particular, the equalizer 52 outputs the equalized signal through P parallel branches. The size of the buffer 60 is P symbols. The buffer includes P symbol positions numbered 0...(P-1). The P branches write P corresponding symbols in parallel to the P corresponding symbol positions in the buffer 60. In the example embodiment, P=128, although any other suitable value may also be used. Specification 4 / 7 pages 7 CN 121753256 A

[0040] Therefore, the frame size should be greater than or equal to P. Typically, the frame size is set to an integer multiple of P (K·P, where K is an integer). With this implementation, SOF occurs once every KP symbols in the signal. This characteristic will be used below.

[0041] For a buffer of size P, there are P possible positions for the SOF sequence (i.e., FD 56 has ambiguity for P symbols). One of these positions is predefined as the “target position”, which is considered aligned when the signal is located at that position. In some embodiments, in response to detecting SOF at the target position in the buffer, FD 56 activates the “SOF detection” signal. Without loss of generality, the description herein assumes that the target position is the beginning of the buffer (i.e., the first symbol of the SOF is stored in the first symbol position in buffer 60).

[0042] Figure 2 illustrates the beginning and end of the disclosed frame alignment process. As can be seen, before frame alignment (top of the figure), the SOF is located at an arbitrary position in buffer 60. After frame alignment (bottom of the figure), the SOF begins at the first symbol position in the buffer.

[0043] In the examples given herein, the frame synchronization sequence (e.g., SOF) is continuous, i.e., consists of a sequence of consecutive symbols. However, this choice is by no means mandatory. In alternative embodiments, the known symbols of the frame synchronization sequence can be distributed throughout the frame in any suitable manner (e.g., with uniform spacing between symbols). In these embodiments, the known symbols of the frame synchronization sequence are interleaved with other symbols of the frame. In this context, “aligning the frame synchronization sequence in the buffer with the frame boundary” can include aligning any symbol of the frame synchronization sequence (e.g., the first symbol) with any target location (e.g., the first location) in the buffer.

[0044] As shown in Figures 1 and 2, the configuration of receiver 20 and its various components is an example configuration chosen purely for conceptual clarity. In alternative embodiments, any other suitable configuration may be used.For clarity, elements not essential for understanding the principles of the invention have been omitted from the accompanying drawings.

[0045] Various elements of receiver 20 may be implemented in hardware (e.g., in one or more application-specific integrated circuits (ASICs) or FPGAs), in software, or using a combination of hardware and software elements. Buffer 60 may be implemented in any suitable memory (e.g., random access memory (RAM)).

[0046] In some embodiments, certain functions of receiver 20, such as some or all of the functions of frame aligner 84, may be implemented in a general-purpose processor programmed in software to perform the functions described herein. For example, the software may be downloaded electronically to the processor via a network, or alternatively or additionally, the software may be provided and / or stored on a non-transitory tangible medium (such as magnetic storage, optical storage, or electronic storage).

[0047] Combined CDR and Frame Alignment In some embodiments, frame aligner 84 performs an iterative process that controls phase correction word 44 generated by NCO 72 to align the signal buffered in buffer 60 with the frame boundary. Typically, each iteration is performed on a newly received frame. In each iteration, frame aligner 84 instructs NCO 72 to add an m / k bias to its generated phase correction word 44. This bias occurs in addition to the error signal generated by loop filter 68. The additional m / k bias is equivalent to a timing shift of one symbol duration (1·UI) in the resampled phase specified by phase correction word 44.

[0048] Therefore, in each iteration, frame aligner 84 shifts the resampled phase specified by control word 44 by 1·UI again. As a result, the position of the SOF sequence in buffer 60 moves one symbol position from one frame to the next. Frame aligner 84 continues this process until FD 56 detects that the SOF sequence has reached the target position in the buffer.

[0049] It is important to note that the frame alignment process is smooth and hitless. Because TED 64 has a 1·UI ambiguity, timing jumps that are integer multiples of 1·UI have no effect on the estimated timing error. The equalizer 52 will not experience performance degradation or be minimally affected by timing jumps.

[0050] In some embodiments, the frame aligner 84 inserts a wait period after every N iterations (after N UI timing shifts) to allow the slow CDR loop to converge. This feature reduces the dynamic range required by the NCO 72 at the cost of slightly slowing down the frame alignment process. In one exemplary embodiment, N=5, but any other suitable value can be used. Setting N allows for a trade-off between frame alignment time and NCO dynamic range.

[0051] FIG3 is a state diagram according to an embodiment of the invention, which schematically illustrates the disclosed frame alignment process.The process in Figure 3 is performed by frame aligner 84. As shown, frame alignment begins after both CDR loops have converged (marked as "CDR convergence") and after equalizer 52 has converged (marked as "EQ convergence").

[0052] Frame alignment begins when frame aligner 84 instructs NCO 72 to add an m / k bias to its generated digital phase correction word (marked as "UI shift"). This bias shifts the timing of the resampled signal (and thus the timing of the signal buffered in buffer 60) by 1·UI.

[0053] After the shift is applied, frame aligner 84 checks whether FD 56 detects SOF. If SOF is detected, meaning the signal is frame aligned, the process terminates (marked as "end"). If SOF is not detected, the process continues.

[0054] Frame aligner 84 then checks whether the sequence of N iterations (applying a total timing shift of N·UI) has been completed. If so, frame aligner 84 waits for a certain waiting period to allow NCO 72 to converge (a state marked "NCO wait"). Alternatively, frame aligner 84 may monitor the value of phase correction word 44 and wait until that value drops below a defined low threshold.

[0055] If the sequence of N iterations has not yet been completed, or after waiting for the "NCO wait" period, frame aligner 84 waits for the next frame to be received and buffered (a state marked "waiting frame"). As described above, in some embodiments, the frame size is set to K·P symbols. In this case, waiting for the frame (K·P symbols) ensures that SOF is not missed. The process then returns to the "UI shift" state, in which frame aligner 84 applies another 1·UI shift for the next iteration. Iteration continues until SOF is successfully detected.

[0056] Figures 4 and 5 are graphs of simulation results according to embodiments of the present invention, illustrating the operating characteristics of the slow CDR loop and the fast CDR loop during joint CDR and frame alignment. The simulations that produced these examples implemented the frequency domain receiver implementation described above.

[0057] In these two graphs, the horizontal axis represents the sampling point number (proportional to time), and the vertical axis represents the relative timing (in units of UI). Curve 90 shows the phase of sampling clock 32 (the phase of VCO 80 and ADC 28), i.e., the phase of the slow CDR loop. Curve 94 shows the phase specified by control word 44 (the phase of resampler 40), i.e., the phase of the fast CDR loop. Curve 98 shows the total phase applied to the received signal.

[0058] Figure 4 shows an example of a sequence of N=5 iterations (five 1·UI timing jumps) applied to the received signal. Short time gaps are inserted between adjacent iterations. The enlarged view in the lower right corner of the figure focuses on the time proximity region of the five timing jumps.

[0059] As shown in the figure, each 1.1 UI timing jump applied by NCO 72 is immediately reflected in the output of resampler 40 (see curve 94). The slow CDR loop of ADC 28 responds to the jump and begins to converge slowly to reduce the bias (see curve 90). The convergence speed and overshoot can be controlled by appropriately setting the loop bandwidth and damping factor of the slow CDR loop. The fast CDR loop (curve 94) responds to the adaptive adjustment of the slow CDR loop (curve 90) and compensates for it in the opposite direction.

[0060] The overall effect is that the 1.1 UI bias step is slowly transferred from digital sampling (via resampler 40) to analog sampling (via ADC 28). At the same time, the total timing phase (curve 98) is smooth and transparent to equalizer 52 and FD 56 (see the steep step in curve 98).

[0061] Figure 5 shows an example of a sequence of 32 iterations applied to the received signal (achieving a total timing correction of 32·UI), see specification page 6 / 7, CN 121753256 A, where a "wait NCO" period is inserted after every N=5 iterations. Curve 94 shows how the "wait NCO" period allows NCO 72 to converge to almost zero before starting the next N=5 iteration sequence.

[0062] It should be noted that the dynamic range of NCO 72 remains below m / k*N throughout the process. After finding the correct shift and allowing the second-order loop to fully converge, the output of NCO 72 depends on the overshoot, which in turn depends on the configured loop damping factor. Unlike the example in Figure 4, in this example, the overshoot is small due to the overdamped loop configuration. Finally, after completing the 32-iteration sequence, the slow CDR loop converges, and the analog signal is ideally sampled with the correct phase, which also achieves frame alignment.

[0063] It should be understood that the above embodiments are cited by way of example, and the invention is not limited to what has been specifically shown and described above. Rather, the scope of the invention includes combinations and sub-combinations of the various features described above, as well as variations and modifications of the invention that would be conceived by one of skill in the art upon reading the above description and that are not disclosed in the prior art. Documents incorporated herein by reference are considered part of this application, and the definitions in this specification should be considered only, unless any terms are defined in these incorporated documents in a manner that conflicts to some extent with the definitions expressly or implicitly made in this specification.Instruction manual, page 7 / 7, 10 CN 121753256 A, Figure 1; Instruction manual, Figure 1 / 5, page 11 CN 121753256 A, Figure 2; Instruction manual, Figure 2 / 5, page 12 CN 121753256 A, Figure 3; Instruction manual, Figure 3 / 5, page 13 CN 121753256 A, Figure 4; Instruction manual, Figure 4 / 5, page 14 CN 121753256 A, Figure 5; Instruction manual, Figure 5 / 5, page 15 CN 121753256 A.

Claims

1. A receiver, comprising: The circuit includes a clock and data recovery (CDR) loop, the circuit being configured to apply a clock-recovery (CDR) to a signal using the CDR loop, and to buffer the signal passing through the CDR in a memory buffer; and A frame aligner configured to align the signal cached in the memory buffer with frame boundaries between consecutive frames of the signal by applying one or more shifts to the CDR loop, each shift being equivalent to one symbol duration of the signal.

2. The receiver according to claim 1, wherein: The circuit includes a processing chain configured to sample the signal according to a sampling clock, resample the sampled signal according to a resampling phase, and buffer the resampled signal in the memory buffer. The CDR loop includes (i) a first CDR loop configured to adjust the sampling clock, and (ii) a second CDR loop configured to adjust the resampling phase; and The frame aligner is configured to align the signal cached in the memory buffer with the frame boundary by applying one or more shifts to both the first CDR loop and the second CDR loop.

3. The receiver according to claim 2, wherein, The first CDR loop has a first loop bandwidth, and the second CDR loop has a second loop bandwidth greater than the first loop bandwidth.

4. The receiver according to claim 2, wherein, The circuit includes a numerically controlled oscillator (NCO) configured to adjust the sampling phase of the first CDR loop and the second CDR loop, wherein the frame aligner is configured to apply the shift by controlling the NCO.

5. The receiver according to any one of claims 1-4, wherein, The circuit is configured to detect a frame synchronization sequence in the signal when the signal cached in the memory buffer is aligned with the frame boundary, and wherein the frame aligner is configured to continue applying the shift until the frame synchronization sequence is detected.

6. The receiver according to any one of claims 1-4, wherein, The frame aligner is configured to apply each of the shifts during different frames of the signal.

7. The receiver according to any one of claims 1-4, wherein, The frame aligner is configured to insert a wait period after every N shifts, where N is a defined integer.

8. A method comprising: Apply CDR to the signal using a clock and data recovery CDR loop; The signal passing through the CDR is buffered in the memory. By applying one or more shifts to the CDR loop, the signal cached in the memory buffer is aligned with the frame boundaries between consecutive frames of the signal, with each shift being equivalent to one symbol duration of the signal; and Further processing is applied to the aligned signals in the memory buffer.

9. The method according to claim 8, wherein: Applying the CDR loop includes (i) adjusting the sampling clock of the signal through a first CDR loop, and (ii) adjusting the resampling phase of the signal through a second CDR loop; and Aligning the signal includes applying one or more shifts to both the first CDR loop and the second CDR loop.

10. The method according to claim 9, wherein, The first CDR loop has a first loop bandwidth, and the second CDR loop has a second loop bandwidth greater than the first loop bandwidth.

11. The method according to claim 9, wherein, Aligning the signal includes applying the shift to a numerically controlled oscillator (NCO) that adjusts the sampling phase of the first CDR loop and the second CDR loop.

12. The method according to any one of claims 8-11, wherein, Aligning the signal includes continuing to apply the shift until a frame synchronization sequence is detected in the signal, the frame synchronization sequence indicating that the signal cached in the memory buffer is aligned with the frame boundary.

13. The method according to any one of claims 8-11, wherein, Aligning the signal includes applying each of the shifts during different frames of the signal.

14. The method according to any one of claims 8-11, wherein, Aligning the signal includes inserting a wait period after every N shifts, where N is a defined integer.

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