PROCEDURE FOR MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR DEVICE

Description

DESCRIPTION of the industrial invention entitled: “Process for manufacturing semiconductor devices and corresponding semiconductor device” by: STMicroelectronics International NV, nationality Dutch agent through head office and branch Switzerland located at Chemin du Champ-des-Filles 39, 1228 Plan-les-Ouates Geneva, Switzerland. Designated Inventors: Marco ROVITTO, Samuele ZALAFFI. Filed on: May 30, 2024 **** DESCRIPTION TEXT Technical field The description is for devices with semiconductor. One or more forms of implementation may be applied to semiconductor devices comprising circuits integrated circuits (IC), for example. Background Current manufacturing processes for devices semiconductor (integrated circuits, IC) can understand attaching a semiconductor die to a substrate (a leadframe, for example) and, subsequently, provide an electrically insulating package to the device. The package is provided by printing a compound for electrically insulating molding (an epoxy resin, for example) on the substrate having the semiconductor die stuck on it. Inadequate adhesion between the molding compound and the substrate (of metallic material in the case of a leadframe) can result in delamination of the package from the substrate. In certain cases, the degree of delamination is such that Moisture and contaminants can penetrate the package and reach the semiconductor die(s) in it, causing possibly reliability problems (detachment or die corrosion, for example). Documents such as US 7821113 B2, US 6329706 B1, US 20200127637 A1, US 20200020614 A1, US 20200211982 A1, US 20210217686 A1, US 20190182997 A1 and US 20180012848 A1 provide background information in the technology area relative. Purpose and summary One purpose of one or more embodiments is to overcome the drawbacks discussed above. According to one or more forms of implementation, this purpose is achieved by means of a process having the features set forth in the following claims. One or more forms of implementation are related to a semiconductor device (integrated circuit) corresponding. The claims are an integral part of the technical teaching provided with reference to the forms of implementation. In solutions as described here, raised formations are formed on a surface of a substrate for semiconductor devices in order to counteract a unwanted delamination of an encapsulation electrically insulating from the substrate surface. Solutions as described here may result in form raised formations using techniques additive manufacturing, such as induced direct transfer with laser, LIFT (“Laser Induced Forward Transfer”), for example. In solutions such as those described here, raised formations can be formed before and / or after the arrangement of a semiconductor die in a region of substrate die assembly. In solutions such as those described here, raised formations can be formed before and / or after the supply of electrically conductive formations for a semiconductor die arranged in a mounting region of the substrate die. Solutions as described here can be applied to semiconductor devices having a leadframe such as substrate, where raised formations can be provided in a die pad and / or in leads in the leadframe. Brief description of the figures One or more forms of implementation will now be described, pure example title, with reference to the figures annexes, in which: Figure 1 is a cross-sectional view of a semiconductor device illustrating possible problems in traditional semiconductor devices, Figures 2A to 2E are cross-sectional views illustrating a sequence of processing phases according to embodiments of this description, and Figures 3 and 4 are cross-sectional views illustrative of semiconductor devices according to shapes of implementation of this description, and Figures 5A through 5C are flowcharts illustrative of sequences of processing phases according to various forms of implementation of this description. The corresponding numbers and symbols in the different figures generally refer to parts corresponding unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the forms of implementation and are not necessarily drawn to scale. The edges of the features drawn in the figures do not necessarily indicate the end of the extension of the feature. Detailed description In the following description, one or more are illustrated specific details, in order to provide an understanding in-depth analysis of examples of implementation forms of this description. The embodiments can be obtained without one or more of the specific details, or with other processes, components, materials, etc. In other cases, Known operations, materials or structures are not illustrated or described in detail so that certain aspects the forms of implementation will not be made unclear. A reference to “a form of implementation” in the framework of this description intends to indicate that a particular configuration, structure, or feature described with reference to the form of implementation is included in at least one embodiment. Therefore, the phrases like “in an embodiment” or similar that may be present in one or more points of this descriptions do not necessarily refer to the actual to the same form of implementation. Furthermore, particular conformations, structures or features can be combined in a way suitable in one or more forms of implementation. The references used here are provided simply for convenience and therefore do not define the scope of protection or the scope of the forms of implementation. For simplicity and ease of explanation, in all this description, and unless the context indicates otherwise, similar parts or elements are indicated in the various figures with similar reference symbols and a corresponding description will not be repeated for each figure. Figure 1 is a cross-sectional view illustrative of a portion of a device semiconductor (integrated circuit, IC) 10 provided with a QFP package (Quad Flat Package). A device 10 as illustrated in Figure 1 comprehends: a semiconductor chip / die 14 (the terms chip and die are considered here as synonyms) attached in correspondence of the upper / anterior surface of a die pad 12A of a substrate such as a leadframe, e an electrically insulating package 20 that encapsulates the leadframe having the semiconductor die 14 attached thereto it. The designation “leadframe” (or “lead frame”) is used currently (see, for example, the USPC Consolidated Glossary of the United States Patent and Trademark Office) to indicate a metal frame that provides support for a chip or die of an integrated circuit as well as electrical leads to interconnect the integrated circuit in the die or chip to other contacts or components electric. Essentially, a leadframe comprises an array (“array”) of electrically conductive leads or formations (visible in Figures 2A, for example, and indicated there with reference 12B) which from a peripheral position extend inward in the direction of a die or a semiconductor chip 14 thus forming an array of electrically conductive formations from a 12A die pad configured to have at least one die attached to it semiconductor (integrated circuit, IC). This can be through traditional means such as an adhesive for die etching (a die etching film, for example, as illustrated in Figure 1 and indicated here by the DA reference). As illustrated here by way of example, a semiconductor device (integrated circuit) can also include electrically conductive formations 16 (wires, for example) that couple the semiconductor die 14 to the leads (which provide input / output signals, for example) and / or to die pad 12A (which provides a level of mass, for example). The manufacturing processes to obtain a semiconductor device as shown in Figure 1 they are traditional in technique, which makes it superfluous provide a more detailed discussion here. The electrically insulating package 20 can be provided by printing an electrically molding compound insulator (an epoxy resin, for example) on the leadframe having the semiconductor die 14 attached to it (on the top / front surface of die pad 12A). In a semiconductor as represented by example in Figure 1, possible problems may arise of reliability from a delamination of the package 20 from leadframe and / or cracks in package 20. Cracks in the molding compound 20 or a delamination of the molding compound 20 from surface of the die pad 12A or the leads 12B can cause that moisture or contaminants enter the package 20 and that eventually reach die 14 located on the die pad 12A and cause the device to malfunction. Delamination and / or cracks may start on the lower surface of the device (at points D and C illustrated in Figure 1, for example) and can progress along a delamination path (two possible crack / delamination paths are illustrated with dashed lines in Figure 1) in the package 20. According to a traditional approach, a delamination of the electrically insulating encapsulation 20 from leadframe surface can be contrasted forming a layer of a material that facilitates / promotes adhesion (“adhesion promoter”) to the surface of the leadframe. For example, so-called substances that promote non-chemically etched adhesion, NEAP (“Non- Etching Adhesion Promoter”), can be supplied on the surface to improve encapsulation adhesion electrically insulating to the leadframe. However, working with NEAP may involve phases processing that requires time and / or has a cost high. Furthermore, it was observed that a layer of NEAP formed on the surface of a leadframe can dissolve (at least) partially when exposed to acid baths, such as a de-flashing or plating bath, commonly involved in the manufacturing processes of devices semiconductor. According to other approaches, the surface of the leadframe can be formed with grooves / notches in order to improve adhesion with a printed-on encapsulation it. Such solutions may not be adequate in devices comprising relatively small pads, for example, where little space is available to provide such grooves (by punching / stamping, for example). US document 6329706 B1 (already cited) describes a die pad formed with a raised edge in order to increase the path of delamination from an external surface of the semiconductor single-die device arranged on the die pad. This raised edge is formed by folding a portion of the die pad. These solutions may not be adequate in cases where where the die pad is relatively small and / or thick, making thus the formation of such a raised edge (by means of (difficult or complex folding). In solutions as described here, raised formations or formations are formed at a surface of a substrate for semiconductor devices in order to to counteract unwanted delamination of a electrically insulating encapsulation from the surface of the substrate. Solutions as described here may result in form raised formations using techniques additive manufacturing, such as induced direct transfer with laser, LIFT, for example. In solutions such as those described here, raised formations can be formed before and / or after the arrangement of a semiconductor die in a region of substrate die assembly. In solutions such as those described here, raised formations can be formed before and / or after the supply of electrically conductive formations for a semiconductor die arranged in a mounting region of the substrate die. Solutions as described here can be applied to leadframe-based semiconductor devices, where raised formations can be provided on the die pad or on leads. Figures 2A to 2E are cross-sectional views illustrating a sequence of processing phases according to embodiments of this description. For the rest, it will be appreciated that the sequence of phases of Figures 2A to 2E are purely for illustrative purposes, to the extent that: one or more of the phases illustrated in Figures 2A through 2E they can be omitted, performed differently (with other tools, for example) and / or replaced by others phases; additional stages can be added; one or more phases can be realized in one sequence different from the sequence illustrated. In current device manufacturing processes semiconductor, more devices are fabricated simultaneously to be separated into a single individual device in a singulation final. For simplicity and ease of explanation, the The following description and the related figures will reference to the manufacture of a single device. Figure 2A is illustrative of a substrate 12 for semiconductor devices supplied on a carrier temporary (and possibly sacrificial). In various forms in implementation, the substrate 12 may be a leadframe such as illustrated in Figure 2A, comprising a die pad 12A and an array of 12B electrically conductive leads arranged at the periphery or next to the 12A die pad. Substrate 12 is configured to have a die a semiconductor (integrated circuit, IC) arranged in correspondence of a mounting region of die 140 of the upper / front surface. In embodiments in where the substrate is a leadframe 12, the mounting region of die 140 is located in correspondence with the surface top / front of die pad 12A. In the following description, for ease of reference, explanation, reference will be made to processes of manufacturing of a device comprising a leadframe 12 as a substrate; this is purely by way of example to the extent that solutions as described herein can be applied advantageously to devices comprising substrates other than a leadframe such as illustrated here. Figure 2B is illustrative of a semiconductor die 14 arranged by a die etching material (a film for die etching, for example) in correspondence of the mounting region of die 140 of the surface top / front of a 12A die pad in a 12 leadframe. Figure 2C is illustrative of a processing stage in which raised structures or formations 100 are formed in correspondence of the upper / anterior surface of the leadframe 12. According to forms of implementation of this description, the raised formations (or structures) 100 can be formed by manufacturing techniques additive such as jet printing or 3D printing, for example. Advantageously, a technique can be used laser induced direct transfer, LIFT, to form the 100 raised formations on the surface top / front of the leadframe 12. Essentially, a LIFT process includes a deposition process in which a material from a sheet or a donor ribbon is transferred to an acceptor substrate (here the top / front surface of the leadframe 12) facilitated by laser pulses. General information about the LIFT process can be found here. found, for example, in P. Serra, et al.: “Laser-Induced Forward Transfer: Fundamentals and Applications”, in Advanced Materials Technologies / Volume 4, Number 1. Forming 100 raised formations using LIFT can be advantageous to the extent that the LIFT facilitates a precise control over the distribution method and the geometry that can be varied, for example, in order to to increase the adhesion of the raised formations 100 to the leadframe surface 12. Whatever the particular technique, formations raised 100 can be formed by distributing a additional or “add-on” material (“add-on material”) in correspondence of the upper / anterior surface of the substrate 12. To form the raised formations 100 can be used both an electrically conductive add-on material is an electrically insulating add-on material. Among the electrically conductive materials, choices suitable include a silver material, a material of copper and / or a solder material (a paste for welding), for example. To form the raised formations 100 can be also used an adhesive epoxy resin (electrically insulating). In various forms of implementation, raised formations 100 can be formed at the surface top / front of die pad 12A, at the periphery of the mounting region of die 140, as illustrated in Figure 2C. The carved configuration (“pattern”) of formations raised 100 may include raised formations formed as: 100 raised pillar-like formations (“pillar- like”) on the outskirts of the assembly region of die 140, or raised formations 100 similar to dykes / dikes (“dyke- like”) around the mounting region of die 140. It is noted that raised formations as described in precedence (where raised formations 100 are formed on the surface of the substrate 12 having a die arranged semiconductor 14 in its die mounting region 140) can be formed on the surface upper / front of the substrate 12 even before arrange a semiconductor die 14 in the region of assembly of die 140 of substrate 12. In other words, in various forms of implementation the phases of processing described in relation to Figures 2B and 2C can be done in reverse order, resulting in so as to arrange a semiconductor die 14 in the region of assembly of die 140 of a substrate having (already) 100 raised formations provided on its surface (front / upper). Figure 2D is illustrative of processing steps in which electrically conductive formations 16 (wires electrically conductive, for example) are provided for electrically couple the semiconductor die 14 to lead 12B selected in the 12B lead field. As illustrated, the electrically charged formations conductive 16 have: a first terminal portion corresponding to the pads of die bonding provided on the top / front surface of the semiconductor die 14 (not visible in the figures for scale reasons), and a second terminal portion corresponding to a 160 bonding region in the 12 leads. As illustrated, a welding material can be provided in the 160 bonding region in 12B leads, for facilitate the bonding of an end portion of the wires. According to the forms of implementation of this description, 100 raised formations can be formed at the anterior / superior surface of the substrate after the supply of formations electrically conductive to electrically couple the semiconductor die 14 to leads 12B. Figure 2E is illustrative of an encapsulation electrically insulating 20 provided to the device by printing an electrically insulating molding compound (a epoxy resin, for example) on the assembly illustrated in Figure 2D. As discussed previously, it is more likely that a delamination (or cracks) start at points D1 of the interface between the substrate 12 and the encapsulation electrically insulating 20 which are exposed in correspondence of the lower / posterior surface of the device. A possible delamination path along the interface between the substrate 12 and the encapsulation 20 is illustrated with a dotted line in Figure 2E. It has been observed that raised formations 100 as illustrated in Figure 2E contrast a propagation of delamination, that is, delamination does not go beyond a point D2 where it reaches the base of the formation 100 raised provided on the upper / front surface of the substrate 12. Furthermore, in the worst cases where delamination occurs propagates beyond that point D2, it can be appreciated that the 100 raised formation increases the length of the path of delamination to the semiconductor die 14 arranged on the upper / front surface of the substrate 12. In various forms of implementation, the raised formations 100 can be formed at the top / front surface of a 12 in leadframe positions other than that of die pad 12A. For example, as illustrated in Figure 3, raised formations 100 can be formed at the surface top / front of selected 12B leads in the array of lead 12B. As illustrated in Figure 4, raised formations 100 can be formed either at the top / front surface of die pad 12A both in lead top / front surface match 12B selected in the 12B lead field. Processing steps to obtain a device semiconductor having raised formations 100 as illustrated in Figure 3 or Figure 4 are similar to the processing phases described with reference to the Figures from 2A to 2E, and a similar description will not be repeated. In summary, solutions according to forms of implementation of this description include: arrange a semiconductor die 14 in a first region 140 (a die mounting region, for example) of a surface of a substrate 12, and distribute an add-on material on a second substrate surface region 12. The add-on material distributed on the surface of the substrate 12 provides a sculpted configuration of raised formations 100. An electrically insulating material 20 is printed on the surface of the substrate 12 having the die a semiconductor 14 arranged in the first region 140 of the substrate surface 12. The electrically charged material insulator 20 encapsulates the semiconductor die 14 as well as the sculpted configuration of raised formations 100 provided on the surface of the substrate 12. The carved configuration of raised formations 100 counteracts electrically delamination of the material insulator 20 printed on the surface of the substrate 12 from the surface of the substrate 12. The substrate 12 may be a leadframe comprising a die pad 12A which comprises the first region 140 of the surface of a substrate 12 and a lead array electrically conductive 12B arranged around the die pad 12A. Distribute the add-on material on the second region 140 of the surface of the substrate 12 comprises distribute the add-on material on at least one of the die pad 12A (as shown in Figure 2E) and the array of electrically conductive leads 12B (as illustrated in the Figure 3). An add-on material can be distributed either on the die pad 12A both on the lead array electrically conductive 12B (as shown in Figure 4). As mentioned previously, the order of the phases of processing described in relation to Figures 2A to 2E may be different from what is illustrated in the same sequence as Figures. Figures 5A to 5C are flowcharts that summarize a possible sequence of processing phases according to forms of implementation of the present description. Referring to Figure 5A, a machining such as described here may include: 1000 – form raised formations 100 in correspondence of the upper / anterior surface of a substrate 12, 1010 – arrange a 14 semiconductor die in correspondence of a mounting region of die 140 of the upper / front surface of the substrate 12 having 100 raised formations formed on it, 1020 – provide electrical coupling between the die and semiconductor 14 and substrate 12, and 1030 – Print an electrically encapsulated package insulator 20 on the upper / front surface of the substrate 12. The flowchart illustrated in Figure 5B is refers to forms of implementation of this description in which raised formations 100 (block 1000) are formed following the arrangement (block 1010) of a die a semiconductor 14 on the top / front surface of a substrate 12. In other words, an add-on material can be distributed over a second region of the surface of the substrate 12 with the semiconductor die 14 (already) placed in the first region 140 (or in the region of die mounting) of the substrate surface 12. The flowchart illustrated in Figure 5C is refers to forms of implementation of this description in which raised formations 100 (block 1000) are formed following the arrangement (block 1010) of a die a semiconductor 14 on the top / front surface of a substrate 12 and subsequently to the supply of a electrical coupling (block 1020) to the die semiconductor 14. In other words, an add-on material can be distributed to provide a sculpted configuration of 100 raised formations at the surface top / front of a substrate 12 having a die a semiconductor 14 provided with electrically formed conductive 16 towards die 14. The electrically conductive formations conductive 16 can extend along non-conductive paths interfering with the sculpted configuration of formations raise 100. Without prejudice to the basic principles, details and forms of implementation may vary, even in a appreciable, compared to what has been described, purely by way of example, without going beyond the scope of the forms of implementation. The scope of protection is defined by the claims annexes.

Claims

1. A method, comprising: arranging a semiconductor die (14) at a first region (140) of a surface of a substrate (12), dispensing an additional material on a second region of the surface of said substrate (12), wherein the additional material distributed on the surface of the substrate (12) provides a sculpted pattern of raised formations (100), printing an electrically insulating material (20) on the surface of the substrate (12) having the semiconductor die (14) disposed in the first region (140) of the surface of the substrate (12), wherein the electrically insulating material (20) encapsulates the semiconductor die (14) as said sculpted pattern of raised formations (100) is provided at the surface of the substrate (12),wherein the sculpted configuration of raised formations (100) counteracts a delamination of the electrically insulating material (20) printed on the surface of the substrate (12) from said surface of the substrate (12)., 2. A method according to claim 1, comprising distributing the additional material onto the second region (140) of the surface of said substrate (12) by an additive manufacturing technique, preferably by a laser induced direct transfer technique, LIFT.

3. A method according to claim 1 or claim 2, comprising distributing the additional material onto said second region (140) of the surface of said substrate (12) with the semiconductor die (14) disposed at said first region (140) of the surface of the substrate (12).

4. A method according to any of claims 1 to 3, comprising providing in said substrate (12) a die pad (12A) comprising said first region (140) of the surface of a substrate (12) and an array of electrically conductive leads (12B) disposed around the die pad (12A), wherein dispensing said additional material on the second region (140) of the surface of said substrate (12) comprises dispensing the additional material at at least one of the die pad (12A) and the array of electrically conductive leads (12B).

5. The method of claim 4, wherein dispensing said additional material onto the second region (140) of the surface of said substrate (12) comprises dispensing the additional material both at the die pad (12A) and at the electrically conductive lead array (12B).

6. A method according to any of claims 1 to 3, comprising providing in said substrate (12) a die pad (12A) comprising a central portion providing said first region (140) of the surface of a substrate (12), as well as a peripheral portion around the central portion, wherein dispensing said additional material on said second region (140) of the surface of said substrate (12) comprises dispensing the additional material at said peripheral portion of the die pad.

7. A method according to claim 6, comprising providing in said substrate (12) an array of electrically conductive leads (12B) disposed around the die pad, wherein distributing said additional material on the second region (140) of the surface of said substrate (12) comprises distributing the additional material both at the peripheral portion of the die pad and at the array of electrically conductive leads (12B).

8. A method according to any preceding claim, comprising providing electrically conductive formations (16) to the semiconductor die (14) disposed at the first region (140) of the surface of a substrate (12), wherein said electrically conductive formations (16) extend along paths non-interfering with the sculpted pattern of raised formations (100).

9. A method according to any preceding claim, wherein said raised formations (100) comprise pillar-like or embankment-like formations.

10. Device, comprising: a semiconductor die (14) disposed at a first region (140) of a surface of a substrate (12), an additional material distributed on a second region (140) of the surface of said substrate (12), wherein the additional material distributed on the surface of the substrate (12) provides a sculpted pattern of raised formations (100), an electrically insulating material (20) printed on the surface of the substrate (12) having the semiconductor die (14) disposed at the first region (140) of the surface of the substrate (12), wherein the electrically insulating material (20) encapsulates the semiconductor die (14) as said sculpted pattern of raised formations (100) provided on the surface of the substrate (12),wherein the sculpted configuration of raised formations (100) counteracts a delamination of the electrically insulating encapsulation (20) printed on the surface of the substrate (12) from said surface of the substrate (12)., 11. Device according to claim 10, wherein: said substrate (12) comprises a die pad (12A) comprising said first region (140) of the surface of a substrate (12) and an array of electrically conductive leads (12B) disposed around the die pad, and an additional material distributed on the second region (140) of the surface of said substrate (12) comprising the additional material distributed on at least one of the die pad (12A) and the array of electrically conductive leads (12B), preferably on both the die pad (12A) and the array of electrically conductive leads (12B), and / or said substrate (12) comprises a die pad (12A) comprising a central portion providing said first region (140) of the surface of a substrate (12), as well as a peripheral portion around the central portion,wherein the additional material distributed on said second region (140) of the surface of said substrate (12) comprises the additional material distributed at said peripheral portion of the die pad, and / or said substrate (12) comprises an array of electrically conductive leads (12B) disposed around the die pad, wherein the additional material distributed on the second region (140) of the surface of said substrate (12) comprises additional material distributed on both the peripheral portion of the die pad and the array of electrically conductive leads (12B), and / or the device comprises electrically conductive formations (16) towards the semiconductor die (14) disposed at the first region (140) of the surface of a substrate (12), wherein said electrically conductive formations (16) extend along paths non-interfering with the sculpted pattern of raised formations (100),and / or said raised formations (100) include pillar-like or dike-like formations.,