PROCEDURE FOR MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR DEVICE

Description

IPC Rankings Title Process for manufacturing semiconductor devices and corresponding semiconductor device DESCRIPTION of the industrial invention entitled: Process for manufacturing semiconductor devices and corresponding semiconductor device” by: STMicroelectronics International NV, of Dutch nationality acting through its headquarters and Swiss branch located at Chemin du Champ-des-Filles 39, 1228 Plan-les-Ouates Geneva, Switzerland. Designated Inventors: Marco ROVITTO, Samuele ZALAFFI. Filed on: May 30, 2024 **** DESCRIPTION TEXT Technical field The description is about semiconductor devices. One or more embodiments may be applied to semiconductor devices comprising integrated circuits (ICs), for example. Background Current semiconductor device (integrated circuit, IC) fabrication processes may involve etching a semiconductor die onto a substrate (a leadframe, for example) and then providing an electrically insulating package to the device. The package is provided by printing an electrically insulating molding compound (an epoxy resin, for example) onto the substrate having the semiconductor die attached to it. Inadequate adhesion between the molding compound and the substrate (metallic in the case of a leadframe) can result in delamination of the package from the substrate. In some cases, the degree of delamination is such that moisture and contaminants can penetrate the package and reach the semiconductor die(s) within it, possibly causing reliability problems (die peel or corrosion, for example). Documents such as US 7821113 B2, US 6329706 B1, US 20200127637 A1, US 20200020614 A1, US 20200211982 A1, US 20210217686 A1, US 20190182997 A1, and US 20180012848 A1 provide background information in the relevant technology area. Purpose and summary One purpose of one or more embodiments is to overcome the drawbacks discussed above. According to one or more embodiments, this aim is achieved by means of a process having the characteristics set out in the following claims. One or more embodiments relate to a corresponding semiconductor (integrated circuit) device. The claims are an integral part of the technical teaching provided with reference to the embodiments. In solutions as described herein, raised formations are formed on a surface of a semiconductor device substrate in order to counteract unwanted delamination of an electrically insulating encapsulation from the substrate surface. Solutions as described here may involve forming raised formations using additive manufacturing techniques, such as laser-induced forward transfer (LIFT), for example. In solutions as described herein, raised formations may be formed prior to and / or subsequent to the placement of a semiconductor die in a die-mount region of the substrate. In solutions as described herein, raised formations may be formed prior to and / or subsequent to the provision of electrically conductive formations for a semiconductor die disposed in a die mounting region of the substrate. Solutions as described here can be applied to semiconductor devices having a leadframe as substrate, where raised formations can be provided in a die pad and / or in leads in the leadframe. Brief description of the figures One or more forms of implementation will now be described, purely by way of example, with reference to the attached figures, in which: Figure 1 is a cross-sectional view of a semiconductor device illustrative of possible problems in conventional semiconductor devices, Figures 2A through 2E are cross-sectional views illustrative of a sequence of processing steps according to embodiments of the present disclosure, and Figures 3 and 4 are cross-sectional views illustrative of semiconductor devices according to embodiments of the present disclosure, and Figures 5A through 5C are flowcharts illustrative of sequences of processing steps according to various embodiments of the present disclosure. The corresponding numbers and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. The edges of features drawn in the figures do not necessarily indicate the end of the feature extension. Detailed description In the following description, one or more specific details are illustrated to provide a thorough understanding of exemplary embodiments of this disclosure. The embodiments may be achieved without one or more of the specific details, or with other processes, components, materials, etc. In other cases, known operations, materials, or structures are not illustrated or described in detail, so that certain aspects of the embodiments will not be obscured. A reference to "an embodiment" within this specification is intended to indicate that a particular configuration, structure, or feature described with respect to the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or the like that may appear in one or more places within this specification do not necessarily refer to the same embodiment. Furthermore, particular conformations, structures or features may be combined in any suitable way in one or more embodiments. The references used herein are provided merely for convenience and therefore do not define the scope of protection or the scope of embodiments. For simplicity and ease of explanation, throughout this description, and unless the context otherwise indicates, similar parts or elements are indicated in the various figures with similar reference symbols and a corresponding description will not be repeated for each figure. Figure 1 is an illustrative cross-sectional view of a portion of a semiconductor (integrated circuit, IC) device 10 having a Quad Flat Package (QFP) package. A device 10 as illustrated in Figure 1 comprises: a semiconductor chip / die 14 (the terms chip and die are considered synonymous herein) attached to the top / front surface of a die pad 12A of a substrate such as a leadframe, and an electrically insulating package 20 encapsulating the leadframe having the semiconductor die 14 attached thereto. The designation leadframe (or “lead frame”) is commonly used (see, for example, the USPC Consolidated Glossary of the United States Patent and Trademark Office) to refer to a metal frame that provides support for an integrated circuit chip or die as well as electrical leads to interconnect the integrated circuit in the die or chip to other electrical contacts or components. Essentially, a leadframe comprises an array of electrically conductive leads or formations (seen in Figures 2A, for example, and designated 12B therein) extending inward from a peripheral location in the direction of a semiconductor die or chip 14 thereby forming an array of electrically conductive formations from a die pad 12A configured to have at least one semiconductor (integrated circuit, IC) die attached thereto. This may be by conventional means such as a die-etch adhesive (a die-etch film, for example, as shown in Figure 1 and designated 1A herein). As illustrated here by way of example, a semiconductor (integrated circuit) device may also include electrically conductive formations 16 (wires, for example) that couple the semiconductor die 14 to the leads (which provide input / output signals, for example) and / or to the die pad 12A (which provides a ground level, for example). The fabrication processes for obtaining a semiconductor device as illustrated in Figure 1 are traditional in the art, making it unnecessary to provide a more detailed discussion here. The electrically insulating package 20 may be provided by molding an electrically insulating molding compound (an epoxy resin, for example) onto the leadframe having the semiconductor die 14 attached thereto (on the top / front surface of the die pad 12A). In a semiconductor as exemplified in Figure 1, potential reliability issues may arise from delamination of the package 20 from the leadframe and / or cracks in the package 20. Cracks in the molding compound 20 or a delamination of the molding compound 20 from the surface of the die pad 12A or the leads 12B can allow moisture or contaminants to enter the package 20 and possibly reach the die 14 disposed on the die pad 12A and cause the device to malfunction. A delamination and / or crack may initiate on the bottom surface of the device (at points D and C illustrated in Figure 1, for example) and may progress along a delamination path (two possible crack / delamination paths are illustrated with dashed lines in Figure 1) in the package 20. In a traditional approach, delamination of the electrically insulating encapsulation 20 from the leadframe surface can be counteracted by coating the leadframe surface with a layer of an adhesion promoter. For example, so-called non-etching adhesion promoters (NEAPs) can be applied to the surface to improve the adhesion of the electrically insulating encapsulation to the leadframe. However, processing with NEAP can involve time-consuming and / or expensive processing steps. Furthermore, it has been observed that a NEAP layer formed on the surface of a leadframe can (at least) partially dissolve when exposed to acidic baths, such as a de-flashing or plating bath, commonly involved in semiconductor device fabrication processes. Other approaches include forming grooves / notches on the leadframe surface to improve adhesion with a printed encapsulation. Such solutions may not be suitable for devices with relatively small pads, for example, where there is little space to provide such grooves (e.g., by punching / stamping). US 6329706 B1 (cited above) describes a die pad formed with a raised lip to increase the delamination path from an external device surface to a semiconductor die located on the die pad. This raised lip is formed by bending a portion of the die pad. Such solutions may not be suitable in cases where the die pad is relatively small and / or thick, thus making the formation of such a raised lip (by bending) difficult or complex. In solutions as described herein, raised formations or ridges are formed at a surface of a semiconductor device substrate in order to counteract unwanted delamination of an electrically insulating encapsulation from the substrate surface. Solutions as described here may involve forming raised formations using additive manufacturing techniques, such as laser induced direct transfer, LIFT, for example. In solutions as described herein, raised formations may be formed prior to and / or subsequent to the placement of a semiconductor die in a die-mount region of the substrate. In solutions as described herein, raised formations may be formed prior to and / or subsequent to the provision of electrically conductive formations for a semiconductor die disposed in a die mounting region of the substrate. Solutions as described here can be applied to leadframe-based semiconductor devices, where raised formations can be provided on the die pad or on the leads. Figures 2A through 2E are cross-sectional views illustrating a sequence of processing steps according to embodiments of the present disclosure. For the rest, it will be appreciated that the sequence of phases in Figures 2A to 2E is purely by way of example, insofar as: one or more steps illustrated in Figures 2A to 2E may be omitted, performed differently (with other tools, for example) and / or replaced by other steps; additional stages can be added; one or more phases may be performed in a sequence different from the sequence illustrated. In current semiconductor device fabrication processes, multiple devices are fabricated simultaneously and then separated into a single device in a final singulation. For simplicity and ease of explanation, the following description and related figures will refer to the fabrication of a single device. Figure 2A is illustrative of a semiconductor device substrate 12 provided on a temporary (and possibly sacrificial) support. In various embodiments, the substrate 12 may be a leadframe as illustrated in Figure 2A, comprising a die pad 12A and an array of electrically conductive leads 12B disposed at the periphery or adjacent to the die pad 12A. Substrate 12 is configured to have a semiconductor (integrated circuit, IC) die disposed at a die mounting region 140 of the top / front surface. In embodiments where the substrate is a leadframe 12, the die mounting region 140 is located at the top / front surface of die pad 12A. In the following description, for ease of explanation, reference will be made to fabrication processes of a device comprising a leadframe 12 as a substrate; this is purely by way of example insofar as approaches as described herein may be advantageously applied to devices comprising substrates other than a leadframe as illustrated herein. Figure 2B is illustrative of a semiconductor die 14 disposed by a die etch material (a die etch film, for example) at the die mounting region 140 of the top / front surface of a die pad 12A in a leadframe 12. Figure 2C is illustrative of a processing step wherein raised structures or formations 100 are formed at the top / front surface of the leadframe 12. In accordance with embodiments of the present disclosure, the raised structures (or structures) 100 may be formed by additive manufacturing techniques such as jet printing or 3D printing, for example. Advantageously, a laser-induced direct transfer technique, LIFT, may be used to form the raised formations 100 on the upper / front surface of the leadframe 12. Essentially, a LIFT process comprises a deposition process where material from a donor foil or tape is transferred to an acceptor substrate (here the top / front surface of the leadframe 12) facilitated by laser pulses. General information on the LIFT process can be found, for example, in P. Serra, et al.: “Laser-Induced Forward Transfer: Fundamentals and Applications”, in Advanced Materials Technologies / Volume 4, Number 1. Forming the raised formations 100 by LIFT may be advantageous insofar as the LIFT facilitates precise control over the distribution pattern and geometry which can be varied, for example, in order to increase the adhesion of the raised formations 100 to the surface of the leadframe 12. Whatever the particular technique, raised formations 100 may be formed by distributing an additional or “add-on” material at the top / front surface of the substrate 12. To form the raised formations 100, either an electrically conductive add-on material or an electrically insulating add-on material can be used. Among electrically conductive materials, suitable choices include a silver material, a copper material, and / or a solder material (a solder paste), for example. To form the raised formations 100 an adhesive epoxy resin (electrically insulating) can also be used. In various embodiments, raised formations 100 may be formed at the top / front surface of die pad 12A, at the periphery of die mounting region 140, as illustrated in Figure 2C. The sculpted pattern of raised formations 100 may include raised formations formed as: 100 pillar-like raised formations at the periphery of the die assembly region 140, or 100 dyke-like raised formations around the die assembly region 140. It is noted that raised formations as described above (where raised formations 100 are formed on the surface of substrate 12 having disposed a semiconductor die 14 in its die mounting region 140) may be formed on the top / front surface of substrate 12 even prior to disposing a semiconductor die 14 in the die mounting region 140 of substrate 12. Stated otherwise, in various embodiments the processing steps described in relation to Figures 2B and 2C may be performed in a reverse order, thereby involving arranging a semiconductor die 14 in the die mounting region 140 of a substrate having (already) raised formations 100 provided on its (front / top) surface. Figure 2D is illustrative of processing steps in which electrically conductive formations 16 (electrically conductive wires, for example) are provided to electrically couple the semiconductor die 14 to leads. 12B selected in the 12B lead field. As illustrated, the electrically conductive formations 16 have: a first terminal portion corresponding to the die bonding pads provided on the top / front surface of the semiconductor die 14 (not visible in the figures for scale reasons), and a second terminal portion corresponding to a bonding region 160 in the leads 12. As illustrated, a solder material may be provided in the bonding region 160 in the leads 12B, to facilitate bonding of an end portion of the wires. In accordance with embodiments of the present disclosure, raised formations 100 may be formed at the front / top surface of the substrate subsequent to the provision of electrically conductive formations to electrically couple the semiconductor die 14 to the leads 12B. Figure 2E is illustrative of an electrically insulating encapsulation 20 provided to the device by molding an electrically insulating molding compound (an epoxy resin, for example) onto the assembly shown in Figure 2D. As discussed previously, delamination (or cracks) are most likely to initiate at locations D1 of the interface between substrate 12 and electrically insulating encapsulation 20 that are exposed at the bottom / back surface of the device. One possible delamination path along the interface between substrate 12 and encapsulation 20 is illustrated with a dashed line in Figure 2E. It has been observed that raised formations 100 as illustrated in Figure 2E counteract a propagation of delamination, i.e., the delamination does not go beyond a point D2 where it reaches the base of the raised formation 100 provided on the top / front surface of the substrate 12. Furthermore, in the worst cases where the delamination propagates beyond that point D2, it can be appreciated that the raised formation 100 increases the length of the delamination path to the semiconductor die 14 disposed on the top / front surface of the substrate 12. In various embodiments, raised formations 100 may be formed at the top / front surface of a leadframe 12 at locations other than that of the die pad 12A. For example, as illustrated in Figure 3, raised formations 100 may be formed at the top / front surface of selected leads 12B in the lead array 12B. As illustrated in Figure 4, raised formations 100 may be formed either at the top / front surface of die pad 12A or at the top / front surface of selected leads 12B in the lead array 12B. Processing steps for obtaining a semiconductor device having raised formations 100 as illustrated in Figure 3 or Figure 4 are similar to the processing steps described with reference to Figures 2A through 2E, and a similar description will not be repeated. In summary, solutions according to embodiments of this description involve: arranging a semiconductor die 14 in a first region 140 (a die mount region, for example) of a surface of a substrate 12, and dispensing an add-on material onto a second region of the surface of the substrate 12. The add-on material distributed on the surface of the substrate 12 provides a sculpted pattern of raised formations 100. An electrically insulating material 20 is printed on the surface of the substrate 12 having the semiconductor die 14 disposed in the first region 140 of the surface of the substrate 12. The electrically insulating material 20 encapsulates the semiconductor die 14 as well as the sculpted pattern of raised formations 100 provided on the surface of the substrate 12. The sculpted configuration of raised formations 100 counteracts delamination of the electrically insulating material 20 printed on the surface of the substrate 12 from the surface of the substrate 12. Substrate 12 may be a leadframe comprising a die pad 12A that comprises the first region 140 of the surface of a substrate 12 and an array of electrically conductive leads 12B disposed around the die pad 12A. Distributing the add-on material onto the second region 140 of the surface of substrate 12 comprises dispensing the add-on material onto at least one of die pad 12A (as illustrated in Figure 2E) and the array of electrically conductive leads 12B (as illustrated in Figure 3). An add-on material may be distributed on both the die pad 12A and the electrically conductive lead array 12B (as illustrated in Figure 4). As previously mentioned, the order of the processing steps described in connection with Figures 2A through 2E may be different from that illustrated in the actual sequence of the Figures. Figures 5A through 5C are flowcharts summarizing a possible sequence of processing steps according to embodiments of the present disclosure. Referring to Figure 5A, a process as described herein may include: 1000 - forming raised formations 100 at the upper / front surface of a substrate 12, 1010 - arranging a semiconductor die 14 at a die mounting region 140 of the top / front surface of the substrate 12 having raised formations 100 formed thereon, 1020 - providing electrical coupling between the semiconductor die 14 and the substrate 12, and 1030 - printing an electrically insulating encapsulation 20 on the top / front surface of the substrate 12. The flowchart illustrated in Figure 5B relates to embodiments of the present disclosure wherein raised formations 100 (block 1000) are formed subsequent to the arrangement (block 1010) of a semiconductor die 14 on the top / front surface of a substrate 12. In other words, an add-on material may be distributed onto a second region of the surface of the substrate 12 with the semiconductor die 14 (already) arranged in the first region 140 (or die mounting region) of the surface of the substrate 12. The flowchart illustrated in Figure 5C relates to embodiments of the present disclosure wherein raised formations 100 (block 1000) are formed subsequent to the arrangement (block 1010) of a semiconductor die 14 on the top / front surface of a substrate 12 and subsequent provision of an electrical coupling (block 1020) to the semiconductor die 14. In other words, an add-on material may be distributed to provide a sculpted pattern of raised formations 100 at the top / front surface of a substrate 12 having a semiconductor die 14 provided with electrically conductive formations 16 toward the die 14. The electrically conductive formations 16 may extend along paths that do not interfere with the sculpted pattern of raised formations 100. Without prejudice to the underlying principles, the details and forms of implementation may vary, even significantly, from what has been described purely by way of example, without departing from the scope of the forms of implementation. The scope of protection is defined by the attached claims.

Claims

1. A method, comprising: arranging a semiconductor die (14) at a first region (140) of a surface of a substrate (12), dispensing an additional material on a second region of the surface of said substrate (12), wherein the additional material distributed on the surface of the substrate (12) provides a sculpted pattern of raised formations (100), printing an electrically insulating material (20) on the surface of the substrate (12) having the semiconductor die (14) disposed in the first region (140) of the surface of the substrate (12), wherein the electrically insulating material (20) encapsulates the semiconductor die (14) as said sculpted pattern of raised formations (100) is provided at the surface of the substrate (12),wherein the sculpted configuration of raised formations (100) counteracts a delamination of the electrically insulating material (20) printed on the surface of the substrate (12) from said surface of the substrate (12)., 2. A method according to claim 1, comprising distributing the additional material onto the second region (140) of the surface of said substrate (12) by an additive manufacturing technique, preferably by a laser induced direct transfer technique, LIFT.

3. A method according to claim 1 or claim 2, comprising distributing the additional material onto said second region (140) of the surface of said substrate (12) with the semiconductor die (14) disposed at said first region (140) of the surface of the substrate (12).

4. A method according to any of claims 1 to 3, comprising providing in said substrate (12) a die pad (12A) comprising said first region (140) of the surface of a substrate (12) and an array of electrically conductive leads (12B) disposed around the die pad (12A), wherein dispensing said additional material on the second region (140) of the surface of said substrate (12) comprises dispensing the additional material at at least one of the die pad (12A) and the array of electrically conductive leads (12B).

5. The method of claim 4, wherein dispensing said additional material onto the second region (140) of the surface of said substrate (12) comprises dispensing the additional material both at the die pad (12A) and at the electrically conductive lead array (12B).

6. A method according to any of claims 1 to 3, comprising providing in said substrate (12) a die pad (12A) comprising a central portion providing said first region (140) of the surface of a substrate (12), as well as a peripheral portion around the central portion, wherein dispensing said additional material on said second region (140) of the surface of said substrate (12) comprises dispensing the additional material at said peripheral portion of the die pad.

7. A method according to claim 6, comprising providing in said substrate (12) an array of electrically conductive leads (12B) disposed around the die pad, wherein distributing said additional material on the second region (140) of the surface of said substrate (12) comprises distributing the additional material both at the peripheral portion of the die pad and at the array of electrically conductive leads (12B).

8. A method according to any preceding claim, comprising providing electrically conductive formations (16) to the semiconductor die (14) disposed at the first region (140) of the surface of a substrate (12), wherein said electrically conductive formations (16) extend along paths non-interfering with the sculpted pattern of raised formations (100).

9. A method according to any preceding claim, wherein said raised formations (100) comprise pillar-like or embankment-like formations.

10. Device, comprising: a semiconductor die (14) disposed at a first region (140) of a surface of a substrate (12), an additional material distributed on a second region (140) of the surface of said substrate (12), wherein the additional material distributed on the surface of the substrate (12) provides a sculpted pattern of raised formations (100), an electrically insulating material (20) printed on the surface of the substrate (12) having the semiconductor die (14) disposed at the first region (140) of the surface of the substrate (12), wherein the electrically insulating material (20) encapsulates the semiconductor die (14) as said sculpted pattern of raised formations (100) provided on the surface of the substrate (12),wherein the sculpted configuration of raised formations (100) counteracts a delamination of the electrically insulating encapsulation (20) printed on the surface of the substrate (12) from said surface of the substrate (12)., 11. Device according to claim 10, wherein: said substrate (12) comprises a die pad (12A) comprising said first region (140) of the surface of a substrate (12) and an array of electrically conductive leads (12B) disposed around the die pad, and an additional material distributed on the second region (140) of the surface of said substrate (12) comprising the additional material distributed on at least one of the die pad (12A) and the array of electrically conductive leads (12B), preferably on both the die pad (12A) and the array of electrically conductive leads (12B), and / or said substrate (12) comprises a die pad (12A) comprising a central portion providing said first region (140) of the surface of a substrate (12), as well as a peripheral portion around the central portion,wherein the additional material distributed on said second region (140) of the surface of said substrate (12) comprises the additional material distributed at said peripheral portion of the die pad, and / or said substrate (12) comprises an array of electrically conductive leads (12B) disposed around the die pad, wherein the additional material distributed on the second region (140) of the surface of said substrate (12) comprises additional material distributed on both the peripheral portion of the die pad and the array of electrically conductive leads (12B), and / or the device comprises electrically conductive formations (16) towards the semiconductor die (14) disposed at the first region (140) of the surface of a substrate (12), wherein said electrically conductive formations (16) extend along paths non-interfering with the sculpted pattern of raised formations (100),and / or said raised formations (100) include pillar-like or dike-like formations.,