DATA READING CIRCUIT AND CORRESPONDING MEMORY DEVICE

Description

DESCRIPTION of the industrial invention entitled: “Data reading process, circuit and device corresponding memory” by: STMicroelectronics International NV, nationality Dutch, agent through head office and branch Switzerland located at: Chemin du Champ-des-Filles 39, 1228 Plan-les-Ouates, Geneva, Switzerland. Designated Inventors: Santi Nunzio Antonino PAGANO, Francesco LA ROSA, Francesca GRANDE. Filed on: June 26, 2024 **** DESCRIPTION TEXT Technical field The description refers to data reading bus in memory devices. Aspects of this description may be used, for example, to manage multiple data buses in matrices or large memory arrays. Description of the related technique To manage multiple data buses in memory matrices or arrays large size you can use an approach multiplex. For example, in large flash memories the memory array can be divided into several banks; This facilitates the reduction of the length of the line bit or bitline and achieving fast reading performance and lower consumption. Each bench is equipped with a respective sensing amplifier (“page” or bank) which outputs the read data and multiple output data buses are multiplexed to obtain a single output data bus. Multiplexing introduces an additional delay in the access time. Additionally, problems may arise related to the synchronization of output data and signal control of multiplexing action in counteracting unwanted spurious switching on the data bus resulting from multiplexing. Using multiplexing also has some impact on the area of ​​occupation. This is linked to the presence of the routing or data bus routing (which can also cause congestion problems) and ports or gates logic involved (the number of which increases with the number of memory banks). Purpose and summary One purpose of one or more embodiments is to contribute to addressing the issues discussed in precedence. According to one or more forms of implementation, such a purpose can be achieved through a procedure having the features set forth in the following claims. One or more embodiments involve a circuit corresponding. A configured sense amplifier to be coupled to a memory bank to read data from it can be exemplary of such a circuit. One or more forms of implementation concern a corresponding memory device. In the solutions as described here the data outputs from multiple memory banks are shared on a common data bus single without resorting to multiplexers. In the solutions as described here, this data bus output is maintained by a single detection bank (e.g. example, the last one involved in reading); during a read operation, the bus is released (in a state HiZ high impedance) without being driven for a short time period (e.g., a few nanoseconds): due to the own capacity, this is not discharged and you do not have no switching takes place on the bus during this interval of time. In the solutions as described here, during the switching, a sense amplifier takes over independently control your own network within of the bus without any delay; the bus control takes place locally in the bench, inside each amplifier of detection. The solutions described here effectively counteract any spurious switching on the output bus and the additional consumption associated; no additional cost is added delay in access time and saves storage area semiconductor (silicon) to the extent that a output data bus only, regardless of the number of memory banks, while you can do without them multiplexer. Brief description of the drawings One or more forms of implementation will now be described, for example only, with reference to the figures annexes, in which: Figure 1 is an example block diagram of a conventional approach to managing multiple data buses in a memory array; Figure 2 represents possible time trends (waveforms) of signals that can occur in a device as illustrated in Figure 1; Figure 3 is an example block diagram for manage multiple data buses in a memory array according to solutions as described here; Figure 4 is an example circuit diagram of possible details of the device in Figure 3; Figure 5 represents possible time trends (waveforms) of signals that can occur in solutions as described here; Figure 6 is an example circuit diagram of possible further details of the device in Figure 3; and Figure 7 and Figure 8 represent possible time courses (waveforms) of signals that can resort to solutions as described here. The figures are drawn to illustrate clearly the relevant aspects of the forms of implementation and are not necessarily drawn to scale. The edges of the features drawn in the figures do not necessarily indicate the boundaries of the characteristics. Detailed description The following description illustrates one or more specific details, aimed at providing an understanding in-depth analysis of examples of implementation forms of this description. The embodiments can be obtained without one or more of the specific details, or with other processes, components, materials, etc. In other cases, Note structures, materials, or operations are not illustrated or described in such detail that certain aspects of the forms of implementation will not be made unclear. The reference to “a form of implementation” in the The structure of this description is intended to indicate that a particular configuration, structure, or feature described in relation to the form of implementation is included in at least one embodiment. Therefore, a sentence like for example “in an embodiment” which can be present in one or more points of this description not necessarily refers to one and the same form of implementation. Furthermore, particular configurations, structures, or features can be combined in any appropriate manner in one or more forms of implementation. The headings / references used here are provided simply for convenience and therefore not define the scope of protection or the scope of the forms of implementation. For all figures herein annexed, unless the context indicates otherwise, similar parts or elements are indicated with similar references / numbers without repeating for brevity a corresponding description. Again, for the sake of simplicity and ease of the explanation, the same denomination can be applied throughout this description to indicate: a certain node or line as well as a recurring signal on that node or line, and / or a certain component (such as a capacitor, resistor or inductor coil) as well as parameters electrics of the same. When an element is said to be “connected to” or “coupled with” another element, it must be understood that yet another element can be interposed, as well as that the element can be connected or coupled directly to another element. Conversely, when you says that an element is “directly connected to” or “directly coupled to” another element, it must to understand that there is no other element in between. Figure 1 is an example block diagram of a conventional approach to managing multiple data buses Dout_Bank_0, Dout_Bank_1, …, Dout_Bank_n starting from respective memory banks Bank_0, Bank_1, …, Bank_n in a (large) memory array, such as a large flash memory. Split a memory array into multiple banks facilitates the reduction of bitline length in order to to achieve fast reading performance and low consumption inferior. The output buses Dout_Bank_0, Dout_Bank_1, …, Dout_Bank_n from the sense amplifier banks SAB_0, SAB_1, …, SAB_n that equip the data banks Bank_0, Bank_1, …, Bank_n are applied to the inputs of a MUX multiplexer that produces, under the control of the SEL selection signal <n:0>an outgoing data stream on a single DATA_Out output bus. The possible operation of such a device is illustrated (in combination with the data buses Dout_Bank_0 and Dout_Bank_1 taken as examples) in the diagram of Figure 2. The diagram in Figure 2 illustrates, with respect to a common time scale of the abscissa t, possible trends timelines (waveforms) of (from top to bottom): a data stream on the Dout_Bank_0 data bus; a data stream on the Dout_Bank_1 data bus; an SEL signal <0> which, when stated on "1", couples the Dout_Bank_0 data bus to the DATA_Out output bus; an SEL signal <1> which, when stated on "1", couples the Dout_Bank_1 data bus to the DATA_Out output bus; And a resulting data stream on the output bus DATA_Out. As visible in Figure 2, to avoid switching spurious on the DATA_Out output bus there is a margin of TM time. This causes an added delay to the time of access and can also lead to problems related to the synchronization of output data with the signal SEL control <n:0>of the MUX multiplexer. In addition, the multiplexing has negative effects in terms of area of occupation related to the presence of routing or routing of the data bus and the logic gates involved. Figure 3 is a general block diagram exemplifying an approach adopted in the solutions as described here. These are again expected to manage multiple data buses from respective data banks memory Bank_0, Bank_1, …, Bank_n in a memory array. As a possible example of such a memory array, can again cite a large flash memory dimensions. In the solutions as illustrated in Figure 3, the outputs of data from different banks Bank_0, Bank_1, …, Bank_n are (directly) shared on a single output data bus DATA_out without resorting to multiplexers such as MUX multiplexer in Figure 1. In the solutions as described here, it is expected that the output data bus DATA_Out is maintained (only) by a detection bench sensing amplifier SAB_0, SAB_1, …, SAB_n at a time, for example from that involved in the most recent read operation. During a read operation, the Data_Out bus is released to a high impedance HiZ state, and is not driven for a short interval (for example not limiting, a few nanoseconds). Thanks to its capacity, the bus does not discharge and during this interval there is no no switching on the bus. In the solutions as described here, whenever a sense amplifier SAB_0, SAB_1, …, SAB_n switches (becomes active), this sense amplifier takes on an autonomous control of an associated network in the bus Data_Out, without any delay. In this way, a read operation takes place in a bank (for example, Bank_1) with the other banks Bank_0, …, Bank_n (in the example case considered, the banks (other than Bank_1) in a high impedance (HiZ) state. Figure 4 is an example circuit diagram of possible details of the device in Figure 3. Essentially, Figure 4 is a schematic example of a possible circuit architecture, indicated collectively with SA, of any of the sense amplifiers SAB_0, SAB_1, …, SAB_n configured to be paired with respective banks of memory Bank_j, with j = 1, …, n. In the example representation of Figure 4, the Reference 10 indicates the core of the SA architecture, which is configured (in a manner known to experts) in the technique) so that the core switching SA 10 generates two signals: OUTINT, which corresponds to the read result - essentially the data that in Figure 1 are conveyed on bus Dout_Bank_0 to Dout_Bank_n, through a latch of reference and a buffer circuit driven by signals high impedance control (HiZ) (as further detailed below), and SALATCH, which is a completion trigger of reading. These signals can be obtained in a way of in itself known to those skilled in the art. For example: The OUTINT signal can be produced by a block of 12 bit differential reading coupled to the bit lines “Left” and “Right” in complementary memory sections in memory banks of an associated memory block Bank_j, with j = 1, …, n (not visible in Figure 4), and The SALATCH signal can be produced by a gate EX-OR 13 coupled to the "Left" and "Right" bit lines. The SETHZ and RESETHZ signals are produced (in the various memory banks Bank_0, Bank_1, …, Bank_n as described (in detail in relation to Figure 6) to set (set) and reset (reset) a high impedance state based on combinations of the main signals (for manage the HiZ status of the lines from the Bank_0, Bank_1 banks, …, Bank_n in the power-on phase) and read control signals (to manage the reading) Reference 14 in Figure 4 indicates a block of latch to which the OUTINT signal is applied and configured for output an output signal OUT. As illustrated, latch block 14 is sensitive to the SALATCH signal (read completion trigger) and to a NRST (negated) input which, in the case of a memory flash, can be used to reset and charge a new application in flash memory. In Figure 4, references 141 and 142 indicate two gates NOR configured to produce a HZ signal to set a high impedance state and a NHZ signal to reset a state of high impedance. As shown in Figure 4, the first NOR gate 141 has three inputs that receive respectively: the RESETHZ signal, the SALATCH signal, and the HZN signal (from the output of the second NOR gate 142, in a cross-coupled arrangement). As shown in Figure 4, the second NOR gate 142 It has two inputs that receive respectively: the SETHZ signal, and the HZ signal (from the output of the first NOR gate 141, in a cross-coupled arrangement). In Figure 4, references 161 and 162 indicate a gate NOR and a NAND gate configured to drive the terminals of control (gate, in the case of field-effect transistors such as MOSFET transistors) of two switches or electronic switches (e.g., MOSFET transistors) 181, 182 arranged with the paths of current flow through of them (source-drain, in the case of phase-effect transistors field such as MOSFET transistors) arranged in cascade in series in a current flow line between a node of power supply VDD and ground GND. As shown in Figure 4, the NOR gate 161 has two inputs that receive respectively: the OUT signal from latch 12, and the HZ signal from the NOR gate 141. As shown in Figure 4, the NAND gate 162 has two inputs that receive respectively: the OUT signal from latch 12, and the HZN signal from the NOR gate 142. An exit node on the power flow line between the VDD power node and the GND ground between the two Electronic switches 181, 182 provide an output signal SAOUT from sense amplifier architecture SA of any of the SAB_0 sense amplifiers, SAB_1, SAB_n to provide the output data stream DATA- Out. Switches 181, 182 consequently provide a output driver stage for architecture of the SA sense amplifier of Figure 4. To summarize, the amplifier architecture of detection indicated as SA in Figure 4 includes: a data reading stage (basically the core SA 10 and latch 14) configured to be coupled to a respective memory bank Bank_j (j = 1, …, n) for read from it OUTINT read data, and an output stage comprising switches electronic (e.g., MOSFET transistors) 181, 182 that are configured to be paired (to the SAOUT node) to the common data read bus DATA_Out to transfer to the bus common data reading DATA_Out OUTINT data read from respective memory bank via the read stage 10, 14. In the sense amplifier architecture indicated as SA in Figure 4 are logic gates 141, 142, 161, 162 realize a variation circuitry of impedance arranged between the reading stage 10, 14 and the output stage 181, 182, with such circuitry impedance variation configured to be switched (see HNZ, HZ signals generated based on the signals RESETHZ and SETHZ) between: a data transfer state, where the stage output 181, 182 has control over the data reading bus common DATA_Out and OUTINT data read from the respective bank of memory Bank_j (j=0, …, n) via the read stage 10, 14 are transferred to the common data read bus DATA_Out during a data read operation using the switches 181, 182 made selectively conductive, and a high impedance (HiZ) state, in which it is data transfer from the stadium was thwarted reading 10, 14 to the common data reading bus DATA_Out (in response to switches 181, 182 being non-conductive) for disable data read operations. As illustrated in Figure 4, the reading stage 10, 14 may advantageously comprise a generator of the latch signal (the EX-OR gate 13) configured for affirm the SALATCH signal indicating completion of a data read operation during which the data OUTINT read from the respective memory bank via the reading stage 10, 14 are transferred to the reading bus common data DATA_Out. As illustrated, the circuitry of impedance variation (comprising elements 141, 142, 161, 162) is coupled (at the NOR gate 141) to the latch signal generator and is consequently configured to switch (via NHZ and HZ signals) from the high impedance state to the transfer state of data in response to the completion signal of a data read operation that is asserted. As illustrated in Figure 4, the output stage can advantageously include a first electronic switch (the MOSFET transistor 181) and a second electronic switch (the MOSFET transistor 182) arranged with the paths of the flow of current through them (source-drain, in case of field effect transistors such as MOSFET transistors) arranged in series in a cascade in a line of the current flow between a VDD power node and the GND mass. An SAOUT exit node in such a flow line current in intermediate position between the first switch electronic 181 and the second electronic switch 182 is coupled to the common data read bus DATA_Out. As illustrated in Figure 4, the first switch electronic 181 and the second electronic switch 182 can be made selectively conductive (in the state data transfer) and non-conductive in the state of high impedance (HiZ). More specifically, as illustrated by way of example in Figure 4, the first electronic switch 181 and the second electronic switch 182 have control terminals (gate, in the case of field-effect transistors such as example MOSFET transistors) driven by the outputs of a first logic gate (the NOR gate 161) and a second gate logic (the NAND gate 162), where both the first gate logic gate 161 and the second logic gate 162 have a respective first input coupled to the reading stage 10, 14 to receive from it the OUTINT data read from respective memory bank, Bank_j (j=0, …, n). As illustrated by way of example in Figure 4, the first logic gate 161 and second logic gate 162 have a respective second input coupled to gates 141, 142 configured to act as control circuitry for was generating a gating signal that has a first value logical (i.e., NHZ) in the transfer state of data and a second logical value (i.e., HZ) in the high impedance state (HiZ). As illustrated by way of example in Figure 4, the first logic gate 161 and second logic gate 162 are configured to make the first electronic switch (the MOSFET transistor 181) and the second electronic switch (the MOSFET transistors 182) conductive and non-conductive in response to whether gating signal has, respectively, the first logical NHZ value or the second logical value HZ. As illustrated by way of example in Figure 4, the state control circuitry may include a first NOR gate 141 and a second NOR gate 142, where: the first NOR gate 141 includes configured inputs to receive a high impedance reset signal RESETHZ and the HZN output from the second NOR gate 142; and the second NOR gate 142 includes configured inputs to receive a high impedance setting signal SETHZ and the HZ output from the first NOR gate 141. Advantageously, the first NOR gate 141 can also include an input configured to receive the signal SALATCH indicative of the completion of an operation data reading. As an example of a possible operation of the architecture as illustrated in Figure 4, the diagram Figure 5 shows, with respect to a common time scale on the abscissa t, possible time trends (waveforms) of signals involved in a data reading operation from a memory configured as shown in Figure 3. More specifically, the diagram in Figure 5 shows possible time trends (waveforms), from top to bottom Bass: of the SETHZ signal; of the HZ signal; of the HZN signal; of the SALATCH signal; of the OUT signal; and of the SAOUT signal. Figure 6 is an example circuit diagram of a circuitry configured to generate respective signals SETHZ and RESETHZ for multiple memory banks Bank_0, Bank_1, Bank_n. In Figure 6, the SETHZ and RESETHZ signals for the bank of Memory Bank_0 are indicated by SETHZ_0 and RESETHZ_0, the SETHZ and RESETHZ signals for memory bank Bank_1 are indicated with SETHZ_1 and RESETHZ_1 and so on up to the signals SETHZ and RESETHZ for the memory bank Bank_n, which are indicated by SETHZ_n and RESETHZ_n. It is expected that these signals will be applied to the SETHZ and RESTHZ inputs of respective banks of the sense amplifier for the memory banks Bank_0, Bank_1, …, Bank_n. It is hypothesized that these amplifier banks detection are configured for all memory banks Bank_0, Bank_1, …, Bank_n according to the same architecture SA as illustrated in Figure 4: for this reason, such architecture is illustrated only once. On the contrary, the circuitry configured to generate the respective SETHZ and RESETHZ signals for a plurality of memory banks Bank_0, Bank_1, …, Bank_n is represented as such as to include n+1 circuits (which are also identical), each expected to be associated with one of the respective memory banks Bank_0, Bank_1, …, Bank_n. In each circuit shown in Figure 6 (with the exception of one of them, for example the circuit associated with the bank Bank_1): a 20_0, …, 20_n NAND gate has a first input that receives a binary complementary version (0>>>1, 1>>>0) of a READEN read enable signal (generated in a manner in itself known to those skilled in the art) and a second input that receives the NRST signal; a buffer stage 22_0, …, 22_n is configured for produce a signal SETHZ_0, …, SETHZ_n from the output of the NAND gate 20_0, …, 20_n; and a logical inverter 24_0, …, 24_n is configured for produce the signal RESETHZ_0, …, RESETHZ_n from the signal VDD. In the circuit associated with the Bank_1 bank, the signals of NRST and VDD input are "inverted" with respect to the circuits associated with other banks. In the circuit associated with the bank Bank_1, inverter input 24_1 is NRST and inputs of NAND gate 20_1 are READEN and VDD. This exemplifies one possibility of managing a initial condition at power on: one of the banks (the (Bank_1, for example) drives the Data_Out bus until the first read operation. As illustrated in Figure 6, a control unit of RCU reading can be configured (in a per way (known to those skilled in the art) to generate and forward to memory banks Bank_0, Bank_1, …, Bank_n READEN, NRST and VDD signals with values ​​like discussed previously which result in SETHZ_0 signals, RESETHZ_0, SETHZ_1, RESETHZ_1, …, SETHZ_n, RESETHZ_n (intended to be applied to logic gates 141, 142 in the SA architecture as illustrated in Figure 4) such as which during each reading operation: the sensing amplifier of one of the banks of memory Bank_0, Bank_1, …, Bank_n takes control over the common data reading bus DATA_Out and data (OUTINT in Figure 4) are read from that of the memory banks Bank_0, Bank_1, …, Bank_n via amplifier detection that has taken control on the read bus common data DATA_Out; and the sensing amplifiers of the other banks of memory Bank_0, Bank_1, …, Bank_n (different from the one you have the control on the common data reading bus DATA_Out are set to a high impedance (HiZ) state, so that the common data reading bus DATA_Out is decoupled from the respective reading stages 10 in the amplifiers detection of these “other” memory banks. Figure 6 (read in conjunction with Figures 3 and 4) is therefore an example of a possible structure of a memory device comprising: a plurality of memory banks Bank_0, Bank_1, ..., Bank_n, a plurality of SAB_0 sense amplifiers, SAB_1, …, SAB_n where each sense amplifier includes the SA architecture as exemplified in Figure 4 and comprising a reading stage 10, 14 coupled to one of the respective memory banks Bank_0, Bank_1, …, Bank_n to make it easier to read OUTINT data from it, and a RCU reading control unit coupled to the plurality of sensing amplifiers SAB_0, SAB_1, …, SAB_n is configured to selectively switch the impedance variation circuitry in it (the gates logical 141, 142, 161, 162) between the transfer state of data and the high impedance (HiZ) state. As an example of how the solutions described here, the diagram in Figure 7 shows, with respect to a common time scale in abscissa t, possible time courses (waveforms) of signals involved in turning on the circuit in a condition where the Bank_1 bank drives the DATA_Out output bus up to unless a first reading operation takes place. That is, the diagram in Figure 7 is example of a sequence of reading operations which are started with a power-on condition of the respective sense amplifiers SAB_0, SAB_1, …, SAB_n of memory banks Bank_0, Bank_1, …, Bank_n in which control on the common data reading bus DATA_Out is assigned by default (RESETHZ_1) to one of the selected sense amplifiers (i.e. SAB_1, associated with the memory bank Bank_1) of the memory banks memory Bank_0, Bank_1, …, Bank_n. More specifically, the diagram in Figure 7 shows possible temporal behaviors (waveforms), from above on the bass: of the NRST signal; of the SETHZ_0 signal for the Bank_0 bank; of the RESETHZ_0 signal for the Bank_0 bank; of the SETHZ_1 signal for the Bank_1 bank; of the RESETHZ_1 signal for the Bank_1 bank; of the SETHZ_n signal for the Bank_n bank; of the RESETHZ_0 signal for the Bank_n bank. These last two signals are identical to the signals SETHZ_0 and RESETHZ_0 for bank Bank_0: this is example of a condition where (only) the signals SETHZ_1 and RESETHZ_1 for Bank_1 have a behavior different from the signals SETHZ_j signals and RESETHZ_j for all other banks in the memory array. As a further example of a possible operation of solutions as described here, the diagram Figure 8 shows, with respect to a common time scale on the abscissa t, possible time trends (waveforms) of signals involved in the functioning including, after POWER ON, a Read Bank_0 read operation starting from, by way of non-limiting example, the Bank_0 bank followed by another read operation Read Bank_1 a starting from, similarly by way of example not limiting, the Bank_1 bank. More specifically, the diagram in Figure 8 shows possible time trends (waveforms) from top to bottom Bass: Read Bank_0 data read from bank Bank_0; Read Bank_1 data read from bank Bank_1; of a READEN read enable signal which, when asserted (e.g., on "1”) results in a state of high impedance HiZ (see also the lower curve in Figure 8); of the SETHZ_1 signal for the Bank_1 bank; of the RESETHZ_1 signal for the Bank_1 bank; of the SALATCH_1 signal for the Bank_1 bank; of the HZ_1 signal for the Bank_1 bank; of the SETHZ_0 signal for the Bank_0 bank; of the RESETHZ_0 signal for the Bank_0 bank; of the SALATCH_0 signal for the Bank_0 bank; of the HZ_0 signal for the Bank_0 bank; and of the (single) DATA_Out output signal. The last signal includes, after an initial string of zeros 0000 after power on: a first high impedance condition HiZ, a string of SOUT output data <0> (the data read from the Bank_0 bank) timed by an ER0 pulse in the SALATCH_0 signal that marks the end of reading from bankBank_0, a further high impedance condition HiZ, a string of SOUT output data <1> (the data read from the Bank_1 bank) timed by an ER1 pulse in the SALATCH_1 signal that marks the end of reading from bankBank_1. The diagram in Figure 8 is consequently further exemplifying the operation in which the memory bank sense amplifier SAB_1 Bank_1 from which data is read during the last operation of reading in a sequence of reading operations maintains control over the common data read bus DATA_Out on a short interval (e.g., a few nanoseconds) with the switching of the data reading bus common DATA_Out disabled during that interval time: due to one's own ability, even without being driven for a short time, the DATA_Out bus is not downloaded without any switching taking place on it. The diagram in Figure 8 highlights the advantages of the solutions as described here such as: spurious switching of the DATA_Out output bus avoid; no additional consumption; a high impedance (HiZ) state released in confirmation that an SA architecture is ready at the end of a read operation; a single DATA_Out data bus regardless of the number of memory banks involved; the possibility of doing without a multiplexer. Without prejudice to the basic principles, details and embodiments may vary, even significantly, compared to what has been described just as an example without departing from the scope of protection. The scope of protection is determined by the annexed claims.

Claims

CLAIMS 1. A method, comprising: coupling a plurality of memory banks (Bank_0, Bank_l, ..., Bank_n) to a common data read bus (DATA_Out) via respective sense amplifiers (SAB_0, SAB_1, ..., SAB_n), reading data (OUTINT) from memory banks in the plurality of memory banks (Bank_0, Bank_l, ..., Bank_n) in a sequence of read operations wherein, during each read operation: the sense amplifier (SAB_1) of one (Bank_l) of the memory banks in the plurality of memory banks (Bank_0, Bank_l, ..., Bank_n) assumes control (RESETHZ_1) over the common data read bus (DATA_Out) and the data (OUTINT) is read from said one (Bank_l) of the memory banks in the plurality of memory banks (Bank_0, Bank_l, ..., Bank_n) via the sense amplifier (SAB_1) which takes control (RESETHZ_1) on the common data read bus (DATA_Out), and the sense amplifiers (SAB_0, ..., SAB_n) of the other memory banks in the plurality of memory banks (Bank_0, Bank_l, ..., Bank_n) other than said one (Bank_l) of the memory banks in the plurality of memory banks (Bank_0, Bank_l, ..., Bank_n) are set (SETHZ_0, ..., SETHZ_n) to a high impedance state.

2. The method of claim 1, wherein the sense amplifier (SAB_1) of the memory bank (Bank_1) from which data is read during the last read operation in the sequence of read operations maintains control over the common data read bus (DATA_Out) over a time interval, with switching of the common data read bus (DATA_Out) disabled during said time interval.

3. A method according to claim 1 or claim 2, comprising initiating said sequence of read operations from a turn-on condition of said respective sense amplifiers (SAB_0, SAB_1, ..., SAB_n) of the memory banks in the plurality of memory banks (Bank_0, Bank_l, ..., Bank_n) wherein (RESETHZ_1) control over the common data read bus (DATA_Out) is assigned by default to a selected one (SAB_1) of the sense amplifiers of the memory banks in the plurality of memory banks (Bank_0, Bank_l, ..., Bank_n).

4. A sense amplifier (SA), comprising: a readout stage (10, 14) configured to be coupled to a respective memory bank in a plurality of memory banks (Bank_0, Bank_1, Bank_n) to read data (OUTINT) from the respective memory bank, an output stage (181, 182) configured to be coupled to a common data readout bus (DATA_Out) to transfer to said common data readout bus (DATA_Out) the data (OUTINT) read from said respective memory bank via the readout stage (10, 14), impedance variation circuitry (141, 142, 161, 162) between the readout stage (10, 14) and the output stage (181, 182), the impedance variation circuitry (141, 142, 161, 162) configured to be switched (HNZ, HZ) between: - 22 a data transfer state (NHZ), in which the output stage (181,182) has control over the common data read bus (DATA_Out) and the data (OUTINT) read from said respective memory bank via the read stage (10, 14) is transferred to the common data read bus (DATA_Out) during a data read operation, and a high impedance (HZ) state, in which the data transfer from the read stage (10, 14) to the common data read bus (DATA_Out) is resisted to disable data read operations., 5. A sense amplifier (SA) according to claim 4, wherein the read stage (10, 14) comprises a latch signal generator (13) configured to assert a signal (SALATCH) indicative of the completion of a data read operation wherein data (OUTINT) read from said respective memory bank via the read stage (10, 14) is transferred to the common data read bus (DATA_Out), and impedance variation circuitry (141, 142, 161, 162) is coupled to the latch signal generator (13) in the read stage (10, 14) and is configured to switch from the data transfer state (NHZ) to the high impedance state (HZ) in response to said signal (SALATCH) indicative of the completion of a data read operation being asserted.

6. The sense amplifier (SA) of claim 4 or claim 5, wherein the output stage comprises a first electronic switch (181) and a second electronic switch (182) arranged with current flow paths therethrough cascaded in a current flow line between a power supply node (VDD) and ground (GND) with an output node (SAOUT) in said intermediate current flow line between the first electronic switch (181) and the second electronic switch (182) coupled to the common data read bus (DATA_Out), the first electronic switch (181) and the second electronic switch (182) configured to be made conductive in said data transfer state (NHZ) and non-conductive in said high impedance state (HZ).

7. A sense amplifier (SA) according to claim 6, wherein: the first electronic switch (181) and the second electronic switch (182) have control terminals driven by the outputs of a first logic gate (161) and a second logic gate (162), wherein both the first logic gate (161) and the second logic gate (162) have a respective first input coupled to the readout stage (10, 14) for receiving therefrom data (OUTINT) read from said respective memory bank, the first logic gate (161) and the second logic gate (162) have a respective second input coupled to the state control circuitry (141, 142) configured to generate a gating signal having a first logic value (NHZ) in the data transfer state and a second logic value (HZ) in the high impedance state,wherein the first logic gate (161) and the second logic gate (162) are configured to make the first electronic switch (181) and the second electronic switch (182) conductive and non-conductive in response to the gating signal having, respectively, the first logic value (NHZ) or the second logic value (HZ)., 8. A sense amplifier (SA) according to claim 7, wherein the first logic gate and the second logic gate comprise a NAND gate (161) and a NOR gate (162), respectively.

9. The sense amplifier (SA) of claim 7 or claim 8, wherein the state control circuitry (141, 142) comprises a first NOR gate (141) and a second NOR gate (142), wherein: the first NOR gate (141) comprises inputs configured to receive a high impedance reset signal (RESETHZ) and output (HZN) from the second NOR gate (142); and the second NOR gate (142) comprises inputs configured to receive a high impedance set signal (SETHZ) and output (ZN) from the first NOR gate (141).

10. A sense amplifier (SA) according to claim 5 and claim 9, wherein the first NOR gate (141) comprises an input configured to receive said signal (SALATCH) indicative of the completion of a data read operation.

11. A memory device, comprising: a plurality of memory banks (Bank_0, Bank_1, ..., Bank_n), a plurality of sense amplifiers (SA) according to any of claims 4 to 10, each sense amplifier (SA) comprising a readout stage (10, 14) coupled to a respective memory bank in the plurality of memory banks for facilitating reading data (OUTINT) therefrom, and - 25 a readout control unit (RCU) coupled to the plurality of sense amplifiers (SA) and configured to selectively switch impedance variation circuitry (141, 142, 161, 162) therein between said data transfer state (NHZ) and said high impedance state (HZ). Translation fully compliant with the original text.