SYSTEM AND CONTROL METHOD OF A SWITCHING CONVERTER OPERATING IN PULSE FREQUENCY MODULATION (PFM)

Description

SYSTEM AND METHOD OF CONTROL OF A CONVERTER IN PULSE FREQUENCY MODULATION (PFM) SWITCHING ★ ★ ★ TECHNICAL FIELD This solution concerns a system and a control method for a switching converter, in particular a voltage converter operating in pulse frequency modulation (PFM). CONTEXT Switching converters (or switching converters), especially DC / DC voltage converters, are typically controlled with a PFM regulation loop when a low-power operating mode is required, for example in the case of power management integrated circuits (so-called PMICs - Power Management Integrated Circuits). This PFM control loop is implemented by a switching converter control unit, typically made as an integrated circuit (IC), capable of generating appropriate control signals to switch one or more switches (typically made with power transistors, for example MOSFETs) and determine the switching operation of the converter. As is known, PFM regulation involves the generation of a square-wave impulsive control signal, having a variable frequency and alternatively a constant on-time interval or off-time interval. The most widely used control mode is the one with a control loop with constant on-time interval (so-called COT - Constant On-Time control), which is the most convenient in terms of compromise between static current consumption and performance. Such a regulation loop usually operates with voltage control, comparing the regulated voltage (provided at the output of the voltage converter) with a reference voltage, for example generated by a bandgap reference. In this regard, Figure 1 shows a simplified schematic of a switching voltage converter 1, which includes a control unit 2, configured to implement a constant-on-time voltage-controlled PFM regulation logic. This control unit 2 is made as an integrated circuit, and has its own package and related input and output pins; this integrated circuit can be mounted on the same printed circuit board (PCB - Printed Circuit Board). Circuit Board) with the circuit components, or the respective integrated circuit, which implement the voltage converter 1. For purely illustrative purposes, Figure 1 refers to a buck converter scheme, but the proposed solution is generally applicable to all types of switching converters. In this configuration, the voltage converter 1 has: an input terminal IN, on which there is an input voltage Vin (for example a DC voltage); and an output terminal OUT, to which a load is connected (for example resistive, R) and on which there is an output voltage Vout, also DC, for example higher than the input voltage Vin and regulated to a desired value. Between the input terminal IN and an internal node N is connected a switching element 4, in particular a power MOSFET transistor, the switching of which determines the PFM switching operation of the voltage converter and is controlled by a control signal Se supplied by the control unit 2. The voltage converter 1 also comprises an inductor element 5, connected between the internal node N and the output terminal OUT; and a capacitor element 6, connected between the same output terminal OUT and a reference terminal, or ground. In particular, the aforementioned control signal Se has a switching period (of variable value), in which is defined: a first time interval, for example a switch-on time Ton in which an inductor current Il of increasing value flows in the inductor element 5; and a second time interval, for example a switch-off time Toff, in which the inductor current Il has a decreasing value. A voltage divider (not shown here), coupled to the output terminal OUT, provides a feedback voltage Vfb, a function of the value of the output voltage Vout, to the control unit 2, which is configured to implement appropriate control logic based on this feedback voltage Vfb. Figure 2 shows a possible, simplified implementation of the control unit 2 (realized as an integrated circuit, le), which implements a PFM control logic, e.g. constant-on-time (eOT) and voltage control. In particular, the control unit 2 comprises in this case a comparator stage 10, which receives at its input the aforementioned feedback voltage Vfb (from a resistive divider) and also a reference voltage Vref and supplies at its output a trigger signal Comp_trigger as a function of this comparison (in particular, having a high value, '1', in the case in which the feedback voltage Vfb falls below the reference voltage Vref) · The control unit 2 also comprises a first definition stage 11, in this case for defining the switch-on time Ton, configured so as to define in this example the constant duration of said switch-on time Ton, starting from the instant of switching (to the high value) of the aforementioned trigger signal Comp_trigger. In particular, this first definition stage 11 comprises a ramp generator 12 (known in itself, not described in detail here), configured so as to generate a ramp voltage Vramp, with an increasing value starting from the aforementioned switching instant; and a respective comparator stage 14, configured so as to receive the ramp voltage Vramp and also a respective reference voltage V'ref to provide at the output a time reference signal Ton_comp, indicative of the achievement of the pre-set (constant) duration for the switch-on time Ton. The control unit 2 further comprises a PFM logic stage 16, which receives as input the aforementioned trigger signal Comp_trigger and the time reference signal Ton_comp and is configured to generate the control signal Se supplied to the switch element 4, for PFM regulation in eOT mode. In use, the comparator stage 10 compares the value of the regulated output voltage with the reference voltage Vref; when the trigger signal eomp_trigger is activated, the control signal Se is set to 1 for a fixed time defined by the turn-on time Ton (in turn defined by the aforementioned first definition stage 11). The control loop described therefore intrinsically has no information on the load current of the converter. In such converters, it is normally required to implement some kind of diagnostics on the output quantities, in particular the monitoring of an overcurrent (OVe - Overcurrent) to protect both the circuits powered by the converter and the converter itself in the event of a fault. Unlike a current-mode control loop, where overcurrent limitation is intrinsically provided by the control, a voltage-mode control loop requires the implementation of additional circuit stages to detect faults or abnormal overcurrent events. Such circuit stages can, for example, implement a comparator that compares the current flowing through the transfer switch with a threshold generated on a reference that is a scaled copy of the same switch. Since COT regulation is typically implemented for low-power applications, where static current consumption and very low-load efficiency are key requirements, it is clear that implementing such additional circuit stages impacts both of these requirements, while also resulting in an unwanted increase in area occupancy. There is therefore certainly a need to implement a control of a switching converter operating in PFM that allows for simpler and less resource-intensive monitoring of the current supplied to a load. SUMMARY The present solution aims to overcome the limitations of known control systems and to provide an answer to the aforementioned need. According to the present solution, a system and a method for controlling a switching converter are therefore provided, as defined in the attached claims. BRIEF DESCRIPTION OF THE FIGURES For a better understanding of the present invention, a preferred embodiment thereof is now described, purely by way of non-limiting example and with reference to the attached drawings, in which: - Figure 1 is a basic block diagram of a switching voltage converter; - Figure 2 is a simplified block diagram of a control unit of the switching converter of Figure 1; - Figure 3 is a block diagram of a PFM logic stage implemented in a control unit of a switching converter operating in PFM, according to one aspect of the present solution; - Figure 4 shows diagrams of quantities associated with the operation of the PFM logic stage of Figure 3; - Figure 5 is a flowchart of operations performed by the PFM logic stage; - Figure 6 shows a possible implementation of a current anomalous event detection stage in the PFM logic stage, according to an embodiment of the present solution; and - Figure 7 shows diagrams of quantities associated with the operation of the detection stage of Figure 6. DESCRIPTION OF FORMS OF IMPLEMENTATION As will be described later, one aspect of the present solution involves using the specific features of a PFM control loop (previously described for a constant-on time control, but what will be described applies analogously to the case of a constant-off time control) to implement a current monitoring at the output of a switching converter, in particular a detection of an anomalous current event (for example, an overcurrent or a short circuit, depending on the DCM - Discontinuous Conduction Mode, or CCM - Continuous Conduction Mode, operating mode of the same converter). In particular, in discontinuous conduction mode (DCM), by defining a constant duration for a first time interval associated with the PFM modulated control signal, for example the turn-on time Ton, and also defining a minimum duration for the second time interval associated with the same control signal, in this example the turn-off time Toff, it is possible to define the maximum switching frequency and therefore the maximum output current capacity. By monitoring the condition in which the converter operates at the maximum frequency, and therefore at the minimum duration of the turn-off time Toff, it is possible to implement overcurrent detection with a negligible impact on current consumption. In continuous conduction mode (CCM), the output current level does not depend on the switching frequency and therefore in this case the current is not limited by setting a minimum duration for the turn-off time Toff. However, the same diagnosis used in DCM mode to detect an overcurrent condition can also be used in CCM mode to detect a rapid change in the switching frequency of the PFM control loop, which could occur, for example, in the event of a large variation (or in any case outside the ranges associated with normal operation) of the load current, caused, for example, by a short circuit. In detail, with reference to Figure 3, a possible implementation of a PFM logic stage, again indicated by 16, of a control unit of a switching converter operating in PFM is first described (for example, of the aforementioned control unit 2 of the voltage converter 1, described with reference to Figures 1 and 2). This implementation generally involves defining the aforementioned minimum duration for the second time interval, in the example the switch-off time Toff, therefore indicated in the following as Toff_min, in such a way as to correspondingly define a maximum frequency for the switching operation of voltage converter 1 (and at the same time, in case of DCM operation, a maximum limit on the current capacity). The aforementioned PFM logic stage 16 comprises a second definition stage 21 for defining the aforementioned minimum duration Toff_min (or, similarly, the aforementioned maximum operating frequency), which receives as input the trigger signal Comp_trigger supplied as output by the comparator stage 10 and also the time reference signal Ton_comp, indicative of the achievement of the preset (constant) duration for the first time interval, in the example the switch-on time Ton, supplied as output by the first definition stage 11 (not illustrated here). This second definition stage 21 comprises a logic gate element AND 22, which receives at a first input the aforementioned trigger signal Comp_trigger and at a second input a masking signal Trigger_mask, such as to mask the same trigger signal Comp_trigger (i.e. to ensure that this signal is not effective) until at least the aforementioned minimum duration Toff_min has elapsed from the end of the first time interval, in the example of the switch-on time Ton. The AND gate element 22 then outputs an actual trigger signal Trig (result of the above masking operation). In essence, and as also illustrated by the trend of the graphs in Figure 4, the Trigger_mask masking signal actually allows you to define the aforementioned minimum duration Toff_min of the second time interval, in the example of the Toff switch-off time, before the end of which the possible presence of the Comp_trigger trigger signal (in this example, always high) is therefore not considered. In greater detail, the second definition stage 21 comprises a set / reset flip-flop element 23, which receives the aforementioned time reference signal Ton_comp at a reset input and the aforementioned effective trigger signal Trig at a set input; the set / reset flip-flop element 23 then outputs a control signal Sc' (see also the aforementioned Figure 4), i.e. a square wave signal with a high value ('1') for the (constant) duration of the on-time Ton and a low value ('0') for at least the aforementioned minimum duration Toff_min. The second definition stage 21 also comprises a NOR logic gate element 24, which has a first input that receives the aforementioned control signal Sc' and a second input that receives a mask signal Smask supplied by a definition element of minimum duration 25 (for example a counter, or a filter) · In particular, this mask signal Smask has a high value ('1') starting from the switching to the low value ('0') of the control signal Sc' and for a duration equal to the aforementioned minimum duration Toff_min) · Consequently, the NOR gate element 24 outputs the aforementioned masking signal Trigger_mask, having a low value ('0') during the aforementioned minimum duration Toff_min, thus allowing the presence of the trigger signal Comp_trigger to be masked (in other words, ensuring that the trigger signal Comp_trigger itself is not effective until the minimum duration Toff_min is reached). As shown in the aforementioned Figure 3, the PFM logic stage 16 of the control unit 2 further comprises a detection stage 26, coupled to the aforementioned second definition stage 21 to receive the masking signal Trigger_mask and the aforementioned actual trigger signal Trig and configured to detect an anomalous current event (i.e., overcurrent or short circuit, depending on the operating mode DCM - Discontinuous Conduction Mode, or CCM - Continuous Conduction Mode), based on monitoring operations performed starting from the same masking signal Trigger_mask and actual trigger signal Trig. In particular, as will be described in detail, such monitoring operations involve, using the information provided by the aforementioned second definition stage 21, counting, by means of a suitable anomalous event counter, a predetermined number N of temporally successive, and in particular consecutive, periods of the control signal Sc (provided by the control unit 2 and which determines the PEM switching operation of the same voltage converter 1) in which the switching converter operates with the aforementioned minimum duration Toff_min for the second time interval; and determining an anomalous current event if the count reaches such predetermined number N, consequently inhibiting the switching operation of the converter and protecting both the internal circuit and the external components from dangerous current levels. Furthermore, if, during monitoring, a period is determined in which the duration of the second time interval is greater than the aforementioned minimum duration Toff_min, the aforementioned anomalous event counter is decremented or reset. With reference to Figure 5, the above-mentioned monitoring operations performed by the control unit 2 of the voltage converter 1, in particular by the relevant PEM logic stage 16, aimed at detecting anomalous current events, are now described in greater detail. In an initial block, indicated by 30, a check of the ignition time Ton is foreseen, having in the example a constant duration (as indicated previously, this check foresees the comparison between the ramp voltage Vramp and the respective reference voltage V'ref). Once this constant duration has elapsed, the control signal Sc' (at the output of the set-reset flip-flop element 23) goes to the low value '0', as indicated in block 31. As a result, block 32 starts checking the minimum duration Toff_min of the second time interval, in the example corresponding to the switch-off time Toff. Once it is determined, as shown in block 33, that the minimum duration Toff_min has elapsed, the check for detecting anomalous current events is implemented, as shown in block 34. In particular, if, at an end instant of the aforementioned minimum duration Toff_min (and, as discussed below, within a monitoring time window immediately following that end instant) the presence of a pulse of the actual trigger signal Trig is detected (which determines the start of the subsequent ignition time Ton), as indicated in block 35, the count is incremented by the anomalous event counter, block 36. Subsequently, block 37, it is checked whether the same anomalous event counter has reached the count limit (corresponding to the aforementioned pre-set number N). If this counting limit has not been reached, output 'NO' from the aforementioned block 37, a new ignition event is carried out, with the control signal assuming a high value of '1', as indicated in block 38, resulting in the consequent start of the ignition interval Ton, block 39 (from which one returns, in a cyclical or iterative manner, to the aforementioned block 30). If the counting limit has been reached, the 'YES' output from the aforementioned block 37 determines the occurrence of an anomalous current event. For example, an overcurrent detection flag (OVC flag) is then set to '1', as indicated in block 40; and furthermore, the switching operation of voltage converter 1 is stopped or inhibited, as indicated in block 41, for example until a subsequent reboot or restart of the same voltage converter 1. However, if the presence of the actual Trig trigger signal is not detected in the aforementioned block 35, monitoring involves, as previously indicated, waiting for the end of a monitoring time window, as indicated in block 42. At the end of this monitoring time window (without an actual trigger signal Trig having been detected), we move on to blocks 44 and 45, where the arrival of a subsequent pulse of the same actual trigger signal Trig is awaited; after which, as indicated in block 46, the count of the aforementioned anomalous event counter is decremented (or, depending on the needs and actual applications in which the voltage converter 1 is used, reset). In essence, this abnormal event counter is decremented, or reset, if it is determined, during monitoring (and the aforementioned counting by the abnormal event counter), that the switching converter does not operate in a subsequent operating cycle with the minimum duration Toff_min for the second time interval. From the aforementioned block 46 we move back to block 38, to wait for a new ignition event, as described previously. With reference to Figure 6, a possible implementation using asynchronous logic of the aforementioned detection stage 26 of the control unit 2 is now described. In this implementation, the detection stage 26 is coupled to the output of the second definition stage 21, by means of the interposition of an inverting element 50, connected between the output of the aforementioned NOR logic gate element 24 (not shown here) and the input of the same detection stage 26. In detail, the detection stage 26 comprises: a first delay logic element 52, connected to the input of the same detection stage 26 and configured so as to implement the aforementioned monitoring time window within which the state of the actual trigger signal Trig is monitored; and furthermore a logic stage 54 (e.g. a two-state flip-flop with clock), which has a signal input connected to the output of the first delay logic element 52 and a clock input which receives the aforementioned actual trigger signal Trig. This logic stage 54 is configured to output a counting increment (Up) or decrement (or reset) signal depending on whether or not the state of the actual trigger signal Trig changes within the monitoring time window. The detection stage 26 also comprises a counter element 56, for example a three-bit incremental counter (in the purely exemplary case in which the aforementioned predetermined number N of consecutive periods is equal to eight), which receives at a control input the aforementioned count increment or decrement / reset signal supplied at the output of the logic stage 54 and also has a timing input. This timing input is coupled to the output of a second delay logic element 57, which receives the actual trigger signal Trig and implements an appropriate time delay, to allow its propagation towards the counter element 56, within which it is used as a clock signal that determines the actual increment or decrement / reset of the count. The same counter element 56 is also configured to output the counting signal, which can in particular cause the aforementioned abnormal current event detection flag (OVC flag) to switch to the high value, '1', in the event that the counting reaches the maximum counting threshold (as indicated, for example equal to eight). The graphs in Figure 7 illustrate the operation described above, in a case where an anomalous current event causes, for example, an output short circuit and the output voltage Vout of the voltage converter is therefore below the reference voltage Vref, starting from a specific time instant t1. The example refers to a switching control with constant on-time duration Ton and continuous conduction mode, CCM. In particular, it is highlighted how, due to the aforementioned short circuit, the inductor current Il continues to rise and the load current Iload is above an overcurrent condition. In this condition, the high value of the actual trigger signal Trig within the monitoring time window (highlighted in Figure 7) following the end of the minimum duration Toff_min associated with the switch-off time Toff determines the increment of the counting signal for the preset number N of consecutive periods of the control signal (in the example equal to eight), consequently determining the switching of the flag indicating the anomalous current event and the application of appropriate protection measures for the voltage converter 1, for example to determine its switch-off. The advantages of the proposed solution clearly emerge from the previous description. In any case, it is reiterated that the solution described allows for increased safety in monitoring the operation of the voltage converter, ensuring the implementation of a diagnosis of / protection from anomalous current events, in particular with overcurrent control (OVC) and current limitation in DCM mode or detection of large load variations (e.g. due to short circuits) in CCM mode. The described solution also does not have any additional static current consumption and has a negligible impact on size and area occupation. Furthermore, the described solution allows for the implementation of self-diagnosis, without impacting the converter's test time. For example, by using the counter, it is possible to automatically test the PFM logic stage 16 (in particular, the related second definition stage 21 and the related detection stage 26). Finally, it is clear that changes and variations may be made to what is described and illustrated here without departing from the scope of protection of the present invention, as defined in the attached claims. In particular, it is highlighted that the proposed solution can also be applied in the case of different types of control and regulation loops in PFM (in particular with a constant switch-off time Toff), in this case the solution can be implemented with a minimum duration Ton_mìn of the switch-on time Ton. Furthermore, in general, the described solution can find advantageous application for any type of DC / DC switching converter operating in PFM regulation mode.

Claims

1. Control unit (2), for controlling a converter (1) operating in switching with REM regulation, configured to generate a control signal (Sc) of the square wave type to control the switching of at least one switching element (4) of the converter (1) having a switching period in which a first time interval (Ton) and a second time interval (Toff) are defined, characterised by a respective high or low value of the control signal (Sc);wherein said control unit (2) is configured to determine a constant duration of said first time interval (Ton) and furthermore to determine a minimum duration (Toff_min) of said second time interval (Toff), so as to determine a maximum operating frequency of said converter (1), characterised in that it comprises a detection stage (26), configured to detect an anomalous current event, as a function of a count of a predetermined number (N) of temporally successive periods of the control signal (Sc) in which said converter (1) operates with said minimum duration (Toff_min) for the second time interval (Toff) and, consequently, with maximum operating frequency.; 2. Control unit according to claim 1, wherein said anomalous current event is an overcurrent or short circuit event, depending on the DCM - Discontinuous Conduction Mode, or respectively CCM - Continuous Conduction Mode, operating mode of the converter (1).

3. Control unit according to claim 1 or 2, configured so as to inhibit the switching operation of the converter (1) if the count reaches said preset number (N).

4. Control unit according to any of the preceding claims, wherein said detection stage (26) is configured to detect an anomalous current event, as a function of counting a predetermined number (N) of temporally consecutive periods of the control signal (Sc) in which said converter (1) operates with said minimum duration (Toff_min) for the second time interval (Toff).

5. Control unit according to any of the preceding claims, comprising: a first definition stage (11) of the first time interval (Ton), configured to define its constant duration, starting from the instant of switching of a trigger signal (Comp_trigger); and a second definition stage (21) for defining said minimum duration (Toff_min) or, similarly, said maximum operating frequency, adapted to receive at input the trigger signal (Comp_trigger) and also a time reference signal (Ton_comp), indicative of the achievement of the constant duration for the first time interval (Ton), provided at output from the first definition stage (11).

6. Control unit according to claim 5, wherein said second definition stage (21) comprises an AND logic gate element (22), capable of receiving at a first input said trigger signal (Comp_trigger) and at a second input a masking signal (Trigger_mask), such as to mask said trigger signal (Comp_trigger) until said minimum duration (Toff_min) has elapsed from the end of the first time interval (Ton), and capable of providing at the output an effective trigger signal (Trig), result of said masking operation.

7. A control unit according to claim 6, wherein said detection stage (26) is configured to: increment said count in the event that the presence of a pulse of said actual trigger signal (Trig) is detected within a monitoring time window corresponding to and immediately following the end of said minimum duration (Toff_min); and, once said monitoring time window has elapsed without the presence of a pulse of said actual trigger signal (Trigger) being detected, decrement, or reset, said count in correspondence with a subsequent pulse of said actual trigger signal (Trig).

8. Control unit according to claim 6 or 7, wherein said detection stage (26) is configured to detect said anomalous current event, as a function of monitoring said actual trigger signal (Trig) and said masking signal (Trigger_mask).

9. A control unit according to claim 8, wherein said detection stage (26) comprises: a first delay logic element (52), configured to implement said monitoring time window within which the state of the actual trigger signal (Trig) is monitored; and further a logic stage (54), which has a signal input connected to the output of the first delay logic element (52) and a timing input which receives said actual trigger signal (Trig) and is configured to output a counting increment, decrement or reset signal depending on whether or not the state change of the actual trigger signal (Trig) occurs within the monitoring time window.

10. Control unit according to claim 9, wherein said detection stage (26) further comprises a counter element (56), configured to implement the counting of said predetermined number (N), which receives at a control input said counting increment, or decrement or reset signal supplied at the output of the logic stage (54) and further presents a timing input coupled to the output of a second delay logic element (57), which receives at its input said effective trigger signal (Trig).

11. Control unit according to claim 9 or 10, wherein said detection stage (26) is implemented by asynchronous logic using said effective trigger signal (Trig) as timing signal.

12. Control unit according to any of claims 5-11, comprising a comparator stage (10), configured to receive at its input a feedback voltage (Vfb) indicative of an output voltage (Vout) from said converter (1) and also a reference voltage (Vref) and to provide at its output said trigger signal (Comp_trigger) as a function of a relative comparison.

13. Converter (1), of the switching type, comprising the control unit (2) according to any of the preceding claims.

14. Control method, for controlling a converter (1) operating in switching with PFM regulation, comprising: generating a control signal (Sc) of the square wave type to control the switching of at least one switching element (4) of the converter (1), having a switching period in which a first time interval (Ton) and a second time interval (Teff) are defined, characterised by a respective high or low value of the control signal (Sc); determining a constant duration of said first time interval (Ton);and further determine a minimum duration (Toff_min) of said second time interval (Toff), so as to define a maximum operating frequency of said converter (1), characterised by the fact of detecting an anomalous current event, as a function of a count of a predetermined number (N) of temporally successive periods of the control signal (Sc) in which said converter (1) operates with said minimum duration (Toff_min) for the second time interval (Toff) and, consequently, with said maximum operating frequency.; 15. Method according to claim 14, comprising inhibiting the switching operation of the converter (1) if the count reaches said predetermined number (N).