BIPOLAR PROGRAMMED LOGIC MATRIX.

Description

TITLE INV. DES PRIORITY INTERNATIONAL BUSINESS MACHINES CORP. A ARMONK NEW YORK USA programmed logic matrix BIPOLAR. DAVIS JAMES U. JONFS FRANK D. USA SUN. RREV. N. 022.589 OF 21 MARCH 1979 £3 DEC Ipop Register A Protocol No. 19930 A / 60 MINISTRY OF INDUSTRY, TRADE AND CRAFTS Provincial Office of Industry, Commerce and Crafts of Milan COPY OF THE MINUTES OF FILING FOR INDUSTRIAL INVENTION PATENT In the year 1980, on the fifteenth day of the month of February, at = =. = =.:=-- hours and = = = = = = minutes, the company INTERNATIONAL BUSINESS MACHINES CORPORATION of United States nationality with headquarters in ARMONK - NEW YORK 10504 (USA) Via through the agent Dr.ing. CAMILLO SAVI at IBM Italia SpA, and with domicile for legal purposes at Milan - Via Andrea Noria 56 at the agent has presented to me, the undersigned: - Stamped application for the granting of a PATENT FOR A MAIN INDUSTRIAL INVENTION having as its designation Τ IT OL O . LOCAL PROGRAMMED REPOLAR MATRIX Priority of patent application in : USA N, 022,589 dated March 21, 1979 designated inventor(s): Jaraes w· Davis G Frank D' Jones' accompanied by : - Description in duplicate of 10 pages of writing. - Drawings, tables n, 2 jn pypio, - Declaration referring to Power of Attorney. - Priority document and Italian translation. Deed of transfer with certified translation (reservation). - Proof of payment into postal account no. 00668004 in the name of the Registry Office for Government Concession Taxes - Rome of Lit. 58,000.* issued by the Milan Post Office on 21 January 1980 at 9:98 p.m. Revenue stamp of Lit. 2,000.- Deed of designation of inventor The application, descriptions and drawings listed above have been signed by the applicant and countersigned by me and stamped with the office seal. THE DEPOSITOR, ................ZZ==s3-i-\........ For a final 11'ori copy THE OFFICIAL R0£A Pietro Jweesineo ' pVp ί rector.-- - (Salvatore RaValli) the addition to the Offices of Odi. ali' Uffici ò-ikewju ...... ' !- I '99 n . / / ' ί / . :.Χ\ τ θ' \ ON. MINISTRY OF INDUSTRY, TRADE AND CRAFTS CENTRAL PATENT OFFICE - ROME The applicant, International Business Machines Corporation, of US nationality, with registered office in ARMONK, NEW YORK 10504 (USA) and domiciled for all legal purposes in Milan, at its Agent Dr.Ing. Camillo Savi, c / o IBM Italia SpA, via A. Doria 56, 20124 Milan, requests, through the aforementioned agent, that the Patent Certificates be granted for the industrial invention entitled: BIPOLAR PROGRAMMED LOGIC MATRIX 9 toi / bii is.o7.eo «ìttsi On.»™... min and this for the purpose of being able to manufacture, sell and use exclusively said invention. the Priority of patent application filed in the United States United States of America N, serial number 022.589 of 21 March 1979. Please attach the following documents to this letter: 1) Description in two copies of n. 10 pages of writing. 2) Drawings n. 2 tables in two copies, ; ι 3) Statement of reference to the General Power of Attorney Act, j 4) Proof of payment into postal account no. 00668004 in the name of the Registry Office for Government Tax Concessions - Rome of Lit. 58,000. Post office Milan 14 no. 998 of 21 January 1980. 5) Revenue stamp of Lit. 2,000 for issuing the Certificate. i*' fi !· ì r * irt; » 6) Priority document and Italian translation. 7) Deed of Transfer with certified translation (reservation). 8) Inventor Designation, j Inventors Designated: James W. Davis and Frank D. Jones. p. International Business Machines Corporation Docket MA9-78-005 / BG .....................................D......ESC.....R.....1 Ζ 1 ONE of the invention having . for title : BIPOLAR PROGRAMMED LOGIC MATRIX name: International Business Machines Corporation residing in Armonk, New York 10504 - USA. of US nationality ί 5 FB deposited on Summary of the invention with no. 4 4 4 4 4 4 4 » :· 4 4 4 4 ........... 1 4··* • 4 *· 4 ft • - And · • ♦ · · • 4 4..4 4 4 · * • 4 4 4 4 4 4 4 4 ft φ 4 4 4 4 * « 4... · A PLA array of bipolar transistor integrated circuits is described. The array includes first and second epitaxial regions, mutually isolated, in a semiconductor substrate. In the first epitaxial region is formed a plurality of common-collector bipolar transistors, selected transistors having their emitters connected in common to a first current source. In a second plurality of common-collector bipolar transistors in the second epitaxial region, the emitters of selected transistors are connected in common to the first epitaxial region. The bases of the corresponding transistor pairs from the first and second epitaxial regions are connected to an input signal source. The second epitaxial region is connected to an output node.In this way a cascode-connected PLA array is formed which eliminates the need for extra current sources required. IV-75 p. International Business Machines Corporation in the prior art. The dot OR combination formed by the circuit effectively merges the prior art OR matrix with the lookup matrix. Description of the invention ·· · · « • · · · * « » » ♦ · • ···· » « · · » Φ • · · · The invention described concerns, in general, semiconductor devices and in particular bipolar PLA arrays. Figure IA illustrates a prior art bipolar PLA circuit in which the lookup array 1 has each OR block 2 and 8 connected to its own respective current source 40 or 41. • · • · ·. ···»· « • · • · * * • ♦ « * · · • · · Φ ···* • · · • · · · In the OR block 2, shown in the logic diagram of figure 1B, the transistors 20 and 21 of the matrix are connected, according to a coupled emitter logic configuration, to the transistor 26, whose collector is the output node for this OR block. The output of the OR block is to be inverted by the inverter using its own current source 42 and the inverted output ORed with the corresponding output of the OR block 8. To perform the PLA function, this prior art circuit shown in FIG. 1A requires five current sources 40, 41, 42, 43, and 44, two inverters 4 and 10, and a separate OR array 6. Note that the epitaxial section serving as the common collector for the OR block 2 is connected to the collector voltage VCC, and that the collector of the reference transistor 26 is connected, through a resistor, to the collector voltage VCC. Accordingly, it is an object of the invention to reduce the p, International Business Machines Corporation number of current sources required in a bipolar PLA circuit. Another object of the invention is to improve the speed / power product of a bipolar PLA circuit. A further object of the invention is to reduce the overall area occupied by a bipolar PLA circuit for a given func- tion r 1·. • •444 4 • ·444 4 ' · •4444 4 4 4 ζ· 4444 ..... ... ,··· · ·· «44· 44·« 4· • ♦ 4 4 action to be performed. The foregoing and other objects, features, and advantages of the invention are achieved with the cascode PLA array described herein. A PLA array of bipolar transistor integrated circuits is described. The array includes first and second regions, both epitaxial and reciprocally.......... isolated, in a semiconductor substrate. In the first epitaxial region, a plurality of common-collector bipolar transistors is formed, selected transistors having their emitters connected in common to a first current source. In a second plurality of common-collector bipolar transistors in the second epitaxial region, selected transistors have their emitters connected in common to the first epitaxial region. The bases of corresponding pairs of transistors from the first and second epitaxial regions are connected to an input signal source. The second epitaxial region is connected to an output node. In this way, a connected PLA array is formed. in cascode which eliminates the need for power sources from 5V-76 p. International Business Machines Corporation extra required in the prior art. The dot OR combination formed by the circuit effectively merges the prior art OR matrix with the lookup matrix. The foregoing and other objects, features and advantages of the invention may be better understood by reference to the accompanying drawings. Figure IA illustrates a bipolar PLA circuit of the prior art. i Figure 1B is a logic diagram of the circuit shown in Figure IA. Figure 2A is a circuit diagram of the cascode PLA array of the invention. Figure 2B is a circuit diagram that more clearly illustrates the coupled-emitter logic configuration of the circuit shown in Figure 2A. Figure 2C is a logic block diagram of the circuit shown in Figure 2A. The PLA cascode array of the invention is shown in Figures 2A, 2B and 2C. As can be seen in the figure 2A, transistors that perform the logic functions corresponding to those performed with the prior art circuit The transistors shown in Figure IA are marked with superscript numbers, to distinguish them from the transistors carrying the same number in Figure IA. In Figure 2A, each OR block 30 and 32 is isolated in its own epitaxial section which acts as a common collector for **·· - fi ···· », • * · * · -····· • MM ···* I ♦ ··· . * ♦ .....* » * • · * · * » · * « · * * ·* • · • · · · · ···· • ♦ · • · · ♦ IV-76 p, Infernalional Business Machines Corporation the transistor array. In OR block 32, for example, the emitters of the bipolar transistors are selectively connected to an emitter line 33 that can serve as a current source connection for the OR block. The most important feature is that the emitter line 33 can be cascoded to the common collector section of the OR block 30, as shown in Figure 2B, so that the function r-·. ·· ·* • · » « a - · ·* • 9 9 9 9 .......· ··'* • * · '·*· « « · « 9999 · • « • · · · φ MI* 1 • · ♦ • a · «a » logic executed by the OR matrix 32 and that executed by the OR matrix 30 are combined at output 35 of the OR block 32^ as shown in the logic diagram of figure 2C. As can be seen more clearly from Figure 2B, the cascode array of bipolar transistors provides a current-switched logic path in which the parallel array of transistors 20', 21', and 50 in the lower OR block 30 is connected in series with the parallel array of transistors 23', 24', and 5Ϊ in the upper OR block 32. In this way, at least one of the transistors in the lower block 30 and at least one of the transistors in the upper block 32 must be in the conducting state before current can flow from V, through the load resistor L, and through the upper row of transistors and the lower row of transistors 30. As current flows through the load transistor L, the voltage of the output terminal 35 drops. For example, if the logic value of the voltage input AB to transistor 23' is greater than the magnitude of the reference voltage REF2, the input to Sip. International Business Machines Corporation transistor 25', transistor 23' is made conductive. During the same period, if the magnitude of the logic voltage C applied to the input of transistor 50 is greater than the value of the reference voltage REFI at transistor 26*, transistor 50 is made conductive. A conductive current path is then formed from V, through the loaded resistor L, the upper row transistor 23' and the lower row transistor 50, to the current source 40', thereby causing the output at output node 35 to go from a relatively high voltage, when all transistors *·· » ·· · « • « « · · · · • » «M ♦ . * « · ♦ · · · « »···* * in the upper row or all transistors in the lower row are off, to a relatively low logic voltage. A shorthand expression for the logical function performed by the transistors in the top row is UOR, while the one for the transistors LOR, as shown in Figure 2C. The bipolar transistors 25' and 26' are referenced respectively REFI and third isolated epitaxial section 34, epitaxial section 34 may contain further transistors whose bases are connected to other reference voltages REF3, REF4 and REF5, for example, provide reference voltages to reference transistors in other cascoded PLA circuits. The collectors of the transistors in section 34 are connected in common in a similar manner to those in the bottom row, which provide the voltages. REF2 are arranged in a shown in figure 2A. L Yes> p. Internationa 1 Business Machines Corporation made the common collector connections for the transistors in sections 30 and 32, described above. Therefore, it can be seen that with the cascode PLA array shown in Figures 2A, 2B, and 2C, the current sources 41, 42, 43, and 44 shown in the prior art circuit of Figure 1A are eliminated. The speed / power product of the cascode PLA array shown in Figure 2A is improved by a factor of approximately ten over that of the prior art circuit shown in Figure 1A. The key feature of the improved cascode PLA circuit of Figure 2A is the elimination. ♦·· ···*: ··., ”'I · . · . ,····· • 4 4 4 · *44» 4 • 4 4 4 4 ***** · 4 · * ·*·.* « 44 4 * mination of the OR matrix 6 of Figure IA by the dot OR combination indicated by E in Figures 2A, 2B and 2C, which effectively merges the OR matrix 6 with the search matrix The resulting cascode PLA array occupies a reduced chip area compared to prior art bipolar PLA arrays. It will be obvious to the skilled person that, although the invention has been shown and described in detail in relation to a preferred embodiment thereof, numerous modifications of the whole and of the details can be made without departing from either the spirit or the scope thereof. 1.

Claims

1. CLAIMS 1. A bipolar transistor integrated circuit PLA array comprising a first epitaxial region isolated in a semiconductor substrate; a second iso-76 p epitaxial region. International Business Machines Corporation formed in said substrate; a plurality of common-collector bipolar transistors formed in said first epitaxial region, selected transistors of said plurality having their emitters connected in common to a first current source; a second plurality of common-collector bipolar transistors in said second epitaxial region, selected transistors of said second plurality having their emitters connected in common to said first epitaxial region; the bases of corresponding pairs of ·· · · • 4 4 4 · 4 · * • 4 4 * 4 ·· ·* * 4 4*444 4 4*44 • 4 4 4 * 4 4 « ft 4 * 4 4 4 4 44 * 4*4 4 4 4 ♦ 4 · 4*44 .··.·* 4 4 4 4 ♦4*· 4 4 > 4 4 4 » 4 » • 4 4 4 * 4 4 4 4 .4 4 4 4 * transistors from said first and said second epitaxial region being connected to an input signal source; said second epitaxial region being connected to an output node; whereby a cascode-connected PLA array is formed.

2. The bipolar transistor integrated circuit PLA array of claim 1 further comprising a third insulated epitaxial region in said substrate; a plurality of common-collector bipolar transistors formed in said third epitaxial region, a first transistor of said plurality having its emitter connected in common with said emitters of said selected transistors of said plurality of transistors in said first epitaxial region, a second transistor of said plurality of transistors in said third epitaxial region having its emitter connected in common with said emitters of said 'V-76 p.International Business Machines Corporation selected transistors of said second multiplicity of transistors in said second epitaxial region; said first of said transistors in said third epitaxial region serving as a reference transistor for said selected transistors of said multiplicity of transistors in said first epitaxial region being connected in a current-switched logic configuration; said second transistor of said multiplicity of transistors in said third epitaxial region serving as a reference transistor for said selected transistors of said second multiplicity of transistors in said second epitaxial region being connected in a current-switched logic configuration.

3. The bipolar transistor integrated circuit PLA array of claim 3 wherein said select transistors of said plurality of transistors formed in said first epitaxial region further comprise a first transistor (the base of which is connected to a first logic input; a second transistor the base of which is connected to a second logic input; said first and said second transistors in said first epitaxial region being connected to said first of said transistors in said third epitaxial region in a current-switched logic configuration, 4. The bipolar transistor integrated circuit PLA array of claim 3 wherein said selected transistors of said second plurality of transistors in said second epitaxial region further comprise a third transistor whose base is connected to a third logic input; a fourth transistor whose base is connected to a fourth logic input; said third and said fourth transistors in said second epitaxial region being connected to said second of said transistors in said third epitaxial region in a logic configuration switched by current.

5. A bipolar transistor integrated circuit PLA array according to claim 4, further comprising a load resistor connected between said output node and a collector voltage; whereby said output node provides a voltage approximately equal to said collector voltage when all said selected transistors of said plurality of transistors in said first epitaxial region are turned off or when all said selected transistors of said second plurality of transistors in said second epitaxial region are turned off. p, International Business Machines Corporation / The Authorized Representative / Dr. Eng. Camillo Savi - 10 ·· · · • · ···· • · · · · ·♦· ***** *··· ·' * ' ·* ·· ***** ·· · * · ***** :· --*·»** * *··· • · * * 4 · • » ♦· · · . . ..· ***** «· * ♦ * ***** * ***** ***** * · · * * * · · * * * · * · • · • * · • · · · • « • » * • * * * * * · · *·*· * · * « « « · -:V. fo me.IV-76 REF2 REFI W bEoOb. AB ed 3. Mfte-tS-OOf l ICQ -l·' + CO + co co < ​​l«C cL hM-ÌÌ-OOT Docket MA9-78-OO5.