SEMICONDUCTOR DEVICE.

Description

TITLE SEMI-CONDUCTOR DEVICE. INV. DES. PRIORITY irfl.HELHUS GERLACHUS VONCKEN °A?SI SASSI DOM. ^REV. N. «006482 OF 28 NOVEMBER 1 o 8 0 Rome, September 24th 4 / 66869 ve Register A Protocol No. 25 287 A / 81 MINISTRY OF INDUSTRY, COMMERCE AND CRAFTS Provincial Office of Industry, Commerce and Crafts of Milan COPY OF THE MINUTES OF FILING FOR INDUSTRIAL INVENTION PATENT In the year 1931, on the twenty-fifth day of the month of NOVEMBER, the pjtt a NV Philips' Gloeilampenf abrieken / H^StgnoK of nationality Netherlands Tjasroenie} in · Eindhoven (Netherlands) Via through an agent of the International Patent Office, C. GREGORJ, with domicile for legal purposes at Milan - Via Dogana 1 at the office of the agent himself, has presented to me, the undersigned: - Stamped application for the granting of a PATENT FOR INDUSTRIAL INVENTION having as TITLE! SEMICONDUCTOR DEVICE Inventor and designat o: Wilhelmus Gerlachus VONCKEN — Priority* of the patent application in: NETHERLANDS No. 8C0643 2 of 28 November 1980 accompanied by: - Description in duplicate of 28 pages of writing. - Drawings, plates no. 2 jn duplo. - lasaeraxlltowartJKK- Declaration reference to Power of Attorney. - Priority document and Italian translation (reservation) - Act of designation of the inventor. - Proof of payment to postal account no. 00668004 in the name of the Tax and Concession Registry Office of RomadiL. 186000 issued by the Milan Post Office 32 on 25 / 11 / 81 no. 376 - Revenue stamp of L. 2,000. The invention referred to in this application is not the subject of other deposits of the same content, made anywhere in Italy on the same date, by the same Owner. The application, descriptions and drawings listed above have been signed by the applicant and countersigned by me and stamped with the office seal. KtìrfiìfSSÌ p. the Director (Salvatore Ravalli) GMTO PATENTS (BoJelli) For a copy compliant with the original THE BOSS 4 / 668 69 ve Hon. MINISTRY OF INDUSTRY, TRADE AND CRAFTS 5 28 7 A / 81 Central Patent Office - ROME to company 25.11 β 1 025.287 NV Philips* Gloeilampenfabrieken in: Eindhoven (Netherlands). of Netherlands nationality through agent and domiciliary PATENT OFFICE IMG. C. GREGORJ, Milan, Via Dogana 1 - requests a patent certificate for an industrial invention entitled: « SEMICONDUCTOR DEVICE Designated Inventor: ____________ Wilhelmus Gerlachus VONCKEN - of nationality Countries Rates - at: Pieter Zeemanstraat 6, Eindhoven (Netherlands) PRIORITY OF BR1VBTTO'S APPLICATION IN NETHERLANDS Ilo. 8006482 of 28 November 1980 the following documents are attached to this document: 1. - Description in duplicate. 2. - Drawings, 2 duplicate plates. 3. - - Reference to general power of attorney. 4. - Attention to payment of the required taxes. 6. - Haroa stamp of L. 2,000. β. - Act of designation of the inventor. 7. - Priority document with Italian translation (reservation) Milan, November 25, 1881 phl; 9904 4 / 66869 ve. Description of the invention entitled: SEMICONDUCTOR DEVICE in the name of: NV Philips · Gloeilampenfabrieken in: Eindhoven (Netherlands) β ì of Dutch nationality and electively dotni_ r registered for all legal purposes in Milan, Via Dogana, 1 - at the Patent Office Ing. C. Gregorj (Filed on 2 5 NOV, 1981 No. 2 5 28 7) A / 81 RIA55UKI0 In a dynamic memory cell, the mutual crosstalk is considerably reduced by using a selection line (12) obtained by diffusion under a thick oxide layer (4) consisting, for example, of a for example, from an IOCOS element. As a result of these measures, the capacitive coupling with other selection lines (13) is considerably reduced while the capacitance of the selection line (12) with respect to the channel stop regions (14) formed between the memory cells is also considerably reduced. DESCRIPTION OF THE INVENTION —2— The present invention relates to a semiconductor device having at least one memory cell comprising a body of semiconductor material having a surface region, of a first type of conductivity, covered with a thick insulating layer, having at least one opening in the insulating layer in correspondence with the area of ​​a storage element of the memory cell, such storage element comprising a capacitor having a first plate of electrically conductive material and a part of the body of semiconductor material which is separated from the first plate by a dielectric and forming a second plate of the capacitor and connected to a region of semiconductor material of a second type of conductivity opposite to the first, through a channel region controllable by means of a gate electrode, the insulating layer having a thickness greater than that of the dielectric,while the gate electrode is electrically connected, conductively, to a first selection line of conductive material of the memory cell, said selection line extending up to above the area of ​​semiconductor material formed, -3many part of a second memory cell selection line* These semiconductor devices are used in dynamic type memories, for illustrative purposes, which can be used in automatic calculators, microprocessors and various other data storage and data manipulation devices. A semiconductor device of the type described above has been described in Japanese Patent Application No. 53-76687. The device described in that application comprises a memory cell formed in an opening in a thick oxide layer on the semiconductor body. The memory cell consists, among other things, of a storage capacitor connected by means of a controllable channel region to a region of semiconductor material having a conductivity type opposite to that of the semiconductor body. The conductivity state of the channel region is determined by the electrical voltage applied to the gate electrode at the conduction channel area, the gate electrode being -4electrically connected, conductively, to a first memory cell selection line. This area of ​​semiconductor material forms part of a second memory cell selection line. The first selection line is designed so that, within the opening in the thick oxide layer, it can cross the second selection line while being separated from it by a thin oxide layer. This causes a high parasitic capacitance and the associated capacitive coupling between the two selection lines. This coupling can result in incorrect selection of the memory cell in question or can result in incorrect information being written or read. Furthermore, the device illustrated in the previously cited Japanese patent application comprises so-called channel stop regions, which are zones having the same type of conductivity in the semiconductor body but characterized by a higher doping of impurities, so as to prevent the formation of a channel between the various memory cells. The zone -5na of semiconductor material that forms part of the second selection line is, in general, very heavily doped, so as to prevent the development of a series resistance of too high a value in the selection line. In the device shown, the semiconductor material region is adjacent to a channel stop region and forms, with it, a α-n junction. Due to the mutual doping with high-value impurities, this α-n junction will have a comparatively low breakdown voltage. Furthermore, this α-n junction represents an additional parasitic capacitance whose value will be higher the higher the degree of doping in the channel stop region. An object of the invention is to provide a semiconductor device of the type indicated above, in which the capacitance between a zone of semiconductor material belonging to the second selection line and the surrounding body of semiconductor material in which the channel stop regions are formed, is of the minimum possible value while, at the same time, the breakdown voltage between the zone -6of semiconductor material and the surrounding semiconductor body has a maximum possible value. A further object of the invention is to provide a device of this type in which the capacitive coupling between the two selection lines is considerably reduced. The invention is based on the recognition that, in plan view, a channel stop region can be obtained substantially adjacent to the semiconductor material zone without forming a p-n junction between two heavily doped semiconductor material regions between said channel stop region and the semiconductor material zone. Furthermore, the present invention is based on the recognition that the capacitive coupling between the two selection lines can be considerably reduced by a favorable positioning of said lines relative to each other. For this purpose, a semiconductor device according to the invention is characterized in that the semiconductor material region -It is present substantially entirely beneath the thick layer of insulation, called the thick layer of insulation, in correspondence with the area of ​​the semiconductor material zone extending into the body of semiconductor material, downward to a depth different from the depth found in other areas in correspondence with the surface. It should be noted that a system consisting of providing a region of semiconductor material beneath a thick layer of oxide is known from IBM Technical Disclosure Bulletin, Vol. 15, No. 4, page 1163. As a result of this measure, the dielectric between the two selection lines has a thickness a few times, for example, 5-10 times greater than that found in the device constructed in accordance with the description in the previously cited Japanese patent application. In this regard, it should be noted that the capacitive coupling is also reduced by an equivalent factor, while the possibility of incorrect selection and incorrect writing or reading operations is considerably reduced. A preferred version compliant with the in -8invention is characterized by the fact that the insulating layer in the area of ​​the semiconductor material zone has a greater thickness than the remaining insulating layer. It should be noted that the capacitance between the semiconductor material region and the surrounding semiconductor body is essentially determined by the j-n junction between the semiconductor material region and the semiconductor body having a low doping level. Since the semiconductor body is lightly doped, the depletion layer of the j-n junction extends in the reverse direction to the semiconductor body. This means that the capacitance associated with the j-n junction is low while an increase in the associated breakdown voltage can be achieved. In addition, uniform channel stop regions may be formed beneath the less thick insulation layer, adjacent to the semiconductor material zones, the thick insulation layer extends into the semiconductor material zone area, preferably into the semiconductor material body, up to -sad a depth that is at least equal to the maximum depth of the channel's stop regions. The resulting advantage is that the channel stop region and the semiconductor material region, when viewed in plan, can be obtained substantially next to each other, without these regions having to come into contact with each other. This prevents the formation of a j£-n junction with a high reverse capacitance and a low breakdown voltage, as previously described. The same advantage is achieved in another preferred version of the invention, which is characterized in that the thick insulation layer extends beyond the region of the semiconductor material zone into the semiconductor body to a depth that is at least equal to the maximum depth of the junction j>-n between the semiconductor material zone and the semiconductor body. The present invention will become more apparent from the following detailed description relating to some specific versions of— -10the same, such treatment being considered in conjunction with the attached drawings, in which: Figure 1 is a plan view of a semiconductor device constructed in accordance with the teachings of the present invention; Figure 2 represents a section considered taken along the line II-II of Figure 1; Figures 3, 4, 5 illustrate some variants of the device shown in Figure 6; and Figures 6-9 illustrate the device schematized in Figure 2, during various stages of the manufacturing process thereof. The figures are diagrammatic and not drawn to scale. For obvious reasons of clarity, the cross-sectional dimensions, particularly the thickness dimensions, have been significantly exaggerated. Areas of semiconductor material exhibiting the same type of conductivity are generally shaded in the same direction. Furthermore, it should be noted that the various corresponding parts, in accordance with the various specific versions of the invention, have been generically identified by the same reference numbers. Figure 1 represents a plan view, while Figure 2 represents a section taken along the line II-II of Figure 1, of a semiconductor device featuring a memory cell. The semiconductor device represented in Figures 1 and 2 comprises a body of semiconductor material 1 consisting, in this case, of a silicon body equipped with a substrate 2. This substrate has a conductivity of the Ω type and is characterized by a resistivity of between 10 and 100 ohms.cm. The surface 3 of the substrate 2 is covered by a layer 4 of silicon oxide having a thickness of approximately 0.5 micrometers. In this thick oxide layer 4 there is an opening 5 corresponding to the area of ​​a storage element of a memory cell. This memory cell may form a single cell or may form part of a larger system having a crossbar system of a first and second set of selection lines in which the memory cells are present at the area corresponding to the intersections of the crossbar system. The surface 3 within the opening 5 is covered with a thin layer 6,8 of insulating material —12— consisting, in this particular specific example, of silicon oxide. When the portion 8 of this thin oxide layer acts as a dielectric, a first plate 7 of electrically conductive material and the underlying region 9 of the semiconductor material substrate 2 form a storage capacitance or memory element. The electrically conductive material of the first plate 7 consists, in this example, of polycrystalline silicon, having a surface resistance of between 20 and 30 ohms / square. The contents of the memory cell are determined by the charge stored in said capacitor. To permit charging or discharging of the capacitor, the device also includes a gate electrode 10 which is separated from an underlying channel region 11 in the substrate 2 by the thin oxide layer 6. In this example, the gate electrode 10 forms part of a first selection line 13 of conductive material, such as aluminum. By means of electrical voltages applied to the gate electrode 10, the underlying channel region 11 is either conductive or non-conductive, and thus the region 9 is electrically conductively connected to a region of semiconductor material 12 forming part of a second selection line.This heavily doped semiconductor material zone 12 has n-type conductivity while being characterized by a surface resistance of 30 ohms / square. In accordance with the principles of the present invention, the semiconductor material region 12 is present substantially entirely beneath the thick oxide layer 4. By virtue of the considerable thickness of this layer, the value of which is, for example, between 0.5 and 1 micrometer, the capacitive coupling between the first selection line 13 and the semiconductor material region 12 is very low. In a memory system having several of these cells, this means that the capacitive coupling between the word conveyor lines and the bit conveyor lines of the system is substantially negligible. The capacitive coupling previously indicated between the selection line 13 and the semiconductor material area 12 is further reduced, in the example currently considered, by the fact that the oxide layer 4, in correspondence with the— -14The area of ​​the semiconductor material zone 12 is thicker than that found elsewhere, approximately 0.8 micrometers. It should also be noted that it is possible to obtain a substantially uniform channel stop region 4 between the various memory cells without any negative effects. If, in practice, the oxide layer 4, corresponding to the area of ​​the semiconductor material zone 12, extends at least into the semiconductor body 1, until it reaches the maximum depth of the channel stop region 14, the semiconductor material zone 12 is circumferentially surrounded by the low-doped substrate.This means that the depletion region associated with the pn junction 15 between the semiconductor material area 12 and the substrate 2, when said pn junction 15 is operated in the reverse direction, extends into the substrate 2 for a considerable part. The parasitic capacitance associated with the pn junction 15 is therefore of limited value while the part of the pn junction 15 between the semiconductor material area 12 and the stop region of the channel 14 or the semiconductor substrate 12, as long as it is adjacent, is small. 15at the surface, it also has a very low value, which means that the memory cell is characterized by short writing and reading times. On the other hand, the breakdown voltage of the pn junction 15, 16 has a higher value, due to the measures adopted. The effects mentioned above, represented by short write and read times and a high breakdown voltage or hreakdown*, are obtained in addition to the slight coupling between the selection line 13 and the semiconductor material area 12, also in the version represented in figure 3 by the fact that the oxide layer 4 itself, in correspondence with the area of ​​a semiconductor material area 12, is sunk, in the semiconductor body, to a greater depth than occurs at other points, with reference to the surface. In this version, the oxide layer 4 has a substantially uniform thickness. It should be noted that the other reference numbers have the same meanings previously defined with reference to figure 2. In figure 4 another practical embodiment of a device is shown. -16 semiconductor constructed in accordance with the principles of the present invention. In this embodiment, the thick oxide layer 4, in the area of ​​the channel stop region 14, is embedded in the semiconductor body to a greater depth than in the area of ​​the semiconductor material zone 12. This oxide layer 4, which, also in this embodiment, has a substantially uniform thickness, extends into the substrate 2 to a depth at least equal to the depth of the £-n junction 15 between the semiconductor material zone 12 and the substrate 2. This latter condition is also obtained in the version shown in figure 5, in which the thick oxide layer 4 in correspondence with the area of ​​the stop regions of the channel 14 is thicker than in correspondence with the area of ​​the semiconductor material zone 12. The other reference numbers shown in figures 4 and 5 also in this case indicate the same elements shown in figure 2. The semiconductor device shown in Figures 1 and 2 can be manufactured by operating in accordance with what will now be described in detail. The starting material 1 consists of a body of semiconductor material 1 comprising a substrate with conductivity of the α type, oriented according to < 100 > , having a resistivity between 10 and 100 ohm.cm. A bilayer 17, 18 of a thick silicon oxide layer 17 approximately 40 nanometers thick and a thick silicon nitride layer 18 approximately 75 nanometers thick is formed on the surface 3 of the substrate 2. A pattern usable to define the semiconductor material zone 12 is then photolithographically created in said bilayer 17, 18. In this particular example, the semiconductor material zones 12 form the bit conveyor lines of a memory array. For this purpose, apertures 19 are created in the bilayer 17, 18. These line-shaped apertures are 2 - 3 micrometers wide. Through these openings, arsenic ion implantation processes are performed in the substrate 2 using a dose of 5 10 arsenic ions / cm , using an energy of 100 keV. This results in a surface resistance of approximately 30 ohms / square for the semiconductor material regions 12 (Figure 6). A silicon oxide layer 20 is then grown to a thickness of approximately 0.3 micrometers by means of a local oxidation process in the area of ​​the aperture 19. During this oxidation process, the donor atoms (arsenic) are forced forward by the grown oxide in the substrate 2 where, towards the edge of the oxide layer 20, along the so-called bird's beak, a doping of arsenic atoms is achieved which decreases in both thickness and concentration.To define the active regions of the semiconductor surface 3, a photosensitive protective layer 21 is formed on top of the surface 3 and is then configured appropriately by photolithography. To produce a good electrical separation between the memory elements, an implantation step for the channel stop is carried out using the same photosensitive protective layer 21 in the form of a mask, employing acceptor ions (boron) with a dose of. -1313 2 boron ions / cm and using an energy of kev. By doing so, the channel stop regions 14 are formed. To achieve low capacitance and high breakdown voltage, predominantly at the £-n junction, i.e., at the part of the £-n junction 15 between the semiconductor material region 12 and the substrate 2 immediately adjacent to the surface 3, this ion implantation step may, if desired, be carried out in a direction as indicated by the arrows 22* rather than performing this implantation in accordance with the vertex arrows ^ 22. Consequently, a portion of the substrate, having a low level of doping, between the semiconductor material zone 12 and the channel stop region 14, may extend up to the surface 3, for example along a width of approximately 0.1 micrometers. This distance is much smaller than that obtained by using exclusively photolithographic methods (Figure 7). The part of the nitride layer 18 not covered by the photosensitive protective layer 21 is then removed first. After removal of the photosensitive protective layer 21, the exposed surface is locally oxidized to a thickness of approximately 0.5 micrometers, using the remaining part of the bilayer 16, 18 as a mask. In the area of ​​the semiconductor material zone 12, the oxide layer 4 reaches a thickness of approximately 0.8 micrometers. The bilayer 17, 18 remaining in the opening 5 is then removed. The surface 3 in the opening 5 present in the thick oxide layer 4 is then provided with a thin transparent oxide layer having a thickness of approximately 50 nanometers. If desired, a boron ion implantation process can be performed using the oxide layer 4 as a mask to accurately adjust the threshold voltage that determines the conductivity of the channel region 11. In this state, appropriate windows can be made in the oxide in question to establish the various contacts at the desired points on the semiconductor body. The entire surface is then provided with a polycrystalline silicon layer 7 having a surface resistance of between 20 and 30 ohms / square, this layer being then appropriately configured by photolithography (fig. 21— figure 8) The assembly is then brought into an oxidizing atmosphere, such as a water vapor atmosphere. An oxide layer 23 is formed to protect the polycrystalline silicon. 7, while simultaneously, the oxide layer 6 in the area of ​​the channel region 11 reaches a slightly greater thickness (Figure 9). The oxide layer 23 grows approximately four times faster than the oxide layer 6, and thus good insulation can be achieved between the conductive plate 7 and the selection line to be formed subsequently, while at the same time, the oxide layer 6 remains sufficiently thin to maintain good control by the gate electrode 10. Between these last two steps, if desired, the memory cells can be temporarily shielded if, for example, to create transistors in the peripheral logic, appropriate ion implantation steps must be conducted to obtain the source and drain regions. After forming the required contact windows in this peripheral logic, the assembly is covered with an aluminum layer comprising 1% silicon —22— in order to create the wiring pattern. Among other things, the selection lines 13 and, in this example, the pure word lines comprising the gate electrode 10 are defined photolithographically. By doing this, the semiconductor device shown in Figures 1, 2 is created. After the opening 19 shown in Figure 6 has been defined, a groove having a depth of approximately 0.2 micrometers can also be obtained by etching the substrate. If desired, the first oxidation step carried out to obtain the oxide 20 can be omitted so as to obtain, in this case, the configuration shown in Figure 3. To obtain the semiconductor devices shown in figures 4 and 5, by way of example, the channel stop regions 14 are first formed by means of openings made in the double layer 17, 18. It is possible to obtain, by etching, a recess in correspondence with the area of ​​said channel stop regions 14 in which the channel stop regions 14 are then defined, while, subsequently, the double layer in correspondence 23— i: The area of ​​the semiconductor material zones 12 to be obtained is either removed photolithographically, and then, after the definition of the semiconductor material zones 12, a thick oxide layer 4 is obtained by means of a local oxidation process (Figure 4), or a local oxidation is first carried out in correspondence with the area of ​​the channel stop regions 14, and then, after the definition of the semiconductor material zones 12, the thick oxide layer 4 is completed (Figure 5). In all the illustrated examples, the distance between the channel stop region 14 and the semiconductor material zone 12, according to a plan view, is less than 0.5 micrometers and, normally, less than 0.1 micrometers, while it is possible to ensure that a low capacitance of the α-n junction 15, 16 between the semiconductor material zones 12 and the substrate 2 is obtained. respectively,and between the semiconductor material region 12 and the channel stop region 14, or an intermediate part of the substrate 2., Obviously, the invention is not limited to the examples given above. By way of example, the conductivity types in the semiconductor body can be simultaneously reversed. The memory cell can also be realized in an epitaxial layer formed on a substrate. Furthermore, in the partial region of the semiconductor body forming the second plate of the capacitor, an arsenic ion implantation process can be carried out, for example, simultaneously with the formation of the source and drain regions in the peripheral logic. The arsenic layer thus formed then constitutes the second plate of the capacitor. Furthermore, the polycrystalline silicon layers 7 forming the first plate of the various capacitors can be connected to a reference voltage represented, for example, by the voltage available at the circuit ground. It should be noted that numerous variations in the manufacturing method indicated are also possible. For example, the thick oxide layer does not necessarily have to be obtained by means of a local oxidation process, since, for example, this thick oxide layer can be formed over the entire surface, on which the semiconductor material areas have already been created. 25tore 12 and, possibly, also the channel stop regions. In this thick oxide layer 4, the openings 5 ​​can be obtained by means of a reactive ion etching process for the exposure of the surface 3 for the fabrication of the actual memory cell.

Claims

1. CLAIMS 1. A semiconductor device having at least one memory cell comprising a body of semiconductor material having a surface region, of a first type of conductivity, covered with a thick insulating layer, having at least one opening in the insulating layer corresponding to the area of ​​a storage element of the memory cell, said storage element comprising a capacitor having a first plate of electrically conductive material and a part of the body of semiconductor material which is separated from the first plate by a dielectric and forms a second plate of the capacitor and connected to a region of semiconductor material of a second type of conductivity opposite to the first, through a channel region controllable by means of a gate electrode, the insulating layer having a thickness greater than that of the dielectric,while the gate electrode is electrically connected, conductively, to a first selection line of conductive material of the memory cell, said selection line extending above the area of ​​semiconductor material forming part of a second selection line of the memory cell, characterized in that the area of ​​semiconductor material is present substantially entirely beneath the thick insulating layer, such thick insulating layer, in correspondence with the area of ​​the area of ​​semiconductor material, extending, in the semiconductor body, to a depth different from the depth found in correspondence with other points in correspondence with the surface, 2· Semiconductor device according to claim 1, characterized in that the thick insulating layer, in correspondence with the area of ​​the semiconductor material zone, has a greater thickness than that of the remaining insulating layer.

3. A semiconductor device according to claim 1 or claim 2, wherein substantially uniform channel stop regions are present between various memory cells, beneath the insulation layer, characterised in that the insulation layer, in correspondence with the area of ​​the semiconductor material zones, extends into the semiconductor body for a depth which is at least equal to the maximum depth of the channel stop regions.

4. A semiconductor device according to claim 1, wherein substantially uniform channel stop regions are present between several memory cells, beneath the insulation layer, characterized in that the insulation layer, beyond the region of the semiconductor material zone, extends into the semiconductor body for a depth that is at least equal to the maximum depth of the £-n junction between the semiconductor material zone and the semiconductor material body.

5. Semiconductor device according to claim 3 or claim 4, characterized in that the maximum distance, according to a plan view, between the semiconductor material zone and the channel stop region is equal to, at most, 0.5 micrometers.

6. A semiconductor device according to any of the preceding claims, characterized in that the semiconductor material zone forms part of the common selection line, of the sunken type, for various memory cells.

7. Semiconductor device according to any of the preceding claims, characterized in that the first plate of semiconductor material of the capacitor is made of polycrystalline silicon. 8 · Semiconductor device according to any of the preceding claims, characterized in that the first selection line belongs to a first group of lines which, together with a second group of lines to which the second selection line belongs, form a system of crossbars while the memory cells are present in correspondence with the area of ​​the intersections of the crossbar system. Milan, 25 November 1581Vi (Pietro M· ('Ufficia 1 4 / 81 1 / 2 & . V l'Ufficiale Rogante