RECESSED BIT LINE AND CYLINDRICAL GATE CELL AND ITS MANUFACTURING METHOD

Description

M Description of the industrial invention having as its title: TT / rt "RECESSED BIT LINE AND CYLINDRICAL GATE CELL, AND RELEVANT MANUFACTURING METHOD* in the name of : SAMSUNG ELECTRONICS CO. , LTlWi 9 4 A001047 Foundation of the 1 invention * * 2 4 MflG.1994 The present invention relates to a semiconductor device and to a method of manufacturing thereof, and more particularly, to a semiconductor device incorporating a recessed bit line and a cylindrical gate cell, and to the method of manufacturing thereof. Integrating a maximum number of devices into the minimum cell area is important to increase the integration of a semiconductor memory cell, and particularly of a dynamic random access memory (DRAM) cell. The memory cell of a one gigabit DRAM cell, which consti- . 2 see a later generation, it occupies an area less than 0.3 pm and is made up of a transistor and a capacitor. Therefore, it is the same area previously needed just for the contact hole for 1 ' interconnection in a one megabit DRAM cell. The formation of a transistor, a capacitor and a contact hole for 1 'interconnecting everything together in such a small area to form a unit cell is virtually impossible. In most memory cells incorporated into chips so far, a transistor, a capacitor and a contact hole are formed laterally according to a planar arrangement, and the relative total area serves as an element to determine the area of ​​the memory cell. Therefore, since a transistor, a capacitor, and a contact hole for connecting the source and drain zones are formed in an area of less than 0.3 pm to make a gigabit memory cell, a three-dimensional cell structure is needed to overcome the area limitations, and the cell structure must be changed from a lateral arrangement to a vertical arrangement structure. In addition, it is necessary to use a maximum effective active area, maximizing the active area by reducing the distance between the isolation zones, and forming the contact hole without losing other active area. K. Sunouchi et al. suggest an SGT cell in which all devices for the unit memory cell are formed in a single silicon column isolated by a trench matrix (see IEDM '89, "A Surrounding Gate Transistor (SGT) cell for 64 / 256Mbit DRAMs"). However, the SGT cell poses the following problems. First, the process of forming silicon column and capacitor is complex. Second, the insulation characteristics are poor. Third, there is a strong possibility of a short circuit between a capacitor plate node and the gate electrode during the process of forming the gate electrode. Summary of the invention Therefore, it is an object of the present invention to provide a highly integrated sinusoidal device which allows for re- 4 Studio Consulenza Brevettuale srl Bianchetti Giuseppe and others solve the problems of the conventional method described above. Another object of the present invention is to provide a method for the fabrication of a highly integrated semiconductor device, especially suitable for the fabrication of the aforementioned semiconductor device. To achieve the first mentioned purpose, a semiconductor device is envisaged comprising: a semiconductor substrate; a trench-like isolation zone formed to define an active zone in the semiconductor substrate; a bit line formed on the semiconductor substrate in which the trench insulation zone is realized; a silicon column formed on the bit line, and carrying a drain, a channel, and a source region of a transistor, which are formed sequentially from a lower part to an upper part of the silicon column; a gate insulating film and a gate line sequentially formed to surround the silicon column; a planarizing layer formed between adjacent goal lines; an insulating layer formed on the gate lines, which features a contact hole for exposing the source area of ​​the transistor; and a capacitor storage node formed on the insulating layer, which connects to the source zone of the transistor through the contact hole. To achieve the other purpose, a method for the manufacture is envisaged- zicne of a highly integrated semiconductor device comprising the stages of: form a trench isolation zone in order to define an active zone in a semiconductor substrate of a first conductivity type; form a bit line on the semiconductor substrate where the trench isolation zone is formed, form a column of insulating film, consisting of a first insulating layer and a second insulating layer stacked on the first insulating layer, only on the trench insulation area; form a silicon column in which a drain, a channel, and a source zone of transistors are sequentially formed from the bottom to the top of the silicon column, on the semiconductor substrate exposed by the insulating film column; remove the second insulating film; sequentially form a gate insulation film and a gate line, so as to surround the silicon column; deposit an insulating material on the resulting structure where the goal line is formed, and back-attach the insulating material to form a planarizing layer; form an insulating layer on the resulting structure in which the planarizing layer is formed; partially etch the insulating layer to form a contact hole to expose the source zone in the silicon column; and form a capacitor storage node, which connects to the source zone through the contact hole, on the resulting structure in which the contact hole is formed. The present invention, which uses a recessed bit line structure and a vertical gate structure surrounding a silicon column, allows the maximum effective active area to be utilized. Brief description of the drawings The objects and advantages of the present invention will become more clearly evident in the following detailed description of a preferred embodiment thereof, referred to in the attached drawings, in which: Figures 1A-1C through 10 are plan and sectional views illustrating a method of fabricating a semiconductor device in accordance with a first embodiment of the present invention; Figures 11 through 17 are plan and sectional views illustrating a method of fabricating a semiconductor device in accordance with a second embodiment of the present invention; and Figures 18 through 26 are plan and sectional views illustrating a method of fabricating a semiconductor device in accordance with a third embodiment of the present invention. Detailed description of the 1 invention The present invention is explained in more detail with reference to the attached drawings. Figures 1A to 1C illustrate the stages of formation of a trench isolation zone 12; in particular, Figures IB and 1C represent cross-sectional views taken along the line AA' and respecting 7 Patent Consulting Studio sr Bianchetti Giuseppe et al. vanente BB' of Figure 1A. A nitride is deposited on a semiconductor substrate 10 of a first conductivity type, for example of a p" type, and is patterned by a lithographic process, thereby forming a nitride pattern 11 on the area where an active zone of the semiconductor substrate 10 will be formed. Then, after etching the substrate 10 to a predetermined depth using the nitride pattern 11 as an etching mask to thus form a trench (not shown), ions of p" type purity are implanted. +to strengthen the electrical characteristics between the devices, thus forming a layer of purity p + 14 below the bottom area of ​​the trench. Then, an insulating material, for example an oxide, is deposited over the entire surface of the substrate 10 in which the trench is formed, and is back-attached, so as to fill the inside of the trench with the insulating material, thus forming a trench insulation layer 12. Figures 2A to 2C represent the formation stages of a bit line 18, and precisely Figures 2B and 2C are seen in cross-section along the line AA' and BB* respectively of Figure 2A. After removal of the nitride figure 11 on the active zone, ions of inpurity of the second conductivity type are implanted, for example of inpurity of the n-type. + over the entire surface of the semiconductor substrate 10, thus forming a zone of n-purity +16 in the surface of the substrate 10. The purity zone n 16 is intended to decrease the contact resistance between a bit line and a drain zone of a transistor, which will be formed in a subsequent process. After that, a conductive material, for example a polysilicon doped with inpurity, is deposited on the substrate 10 in which the purity zone 16 is formed. + , and is configured using a lithographic process, thus forming the 18 bit line. Figures 3A and 3B show the steps in the formation of a column (I) of insulating film; in particular, Figures 3A and 3B are cross-sections taken along the line AA' and BB' respectively of Figure 2A. For example, a nitride and an oxide are sequentially deposited over the entire surface of the resulting structure in which the bit line 18 is formed, thereby forming a first insulating film 20 and a second insulating film 22. Then, the second insulating film 22 and the first insulating film 20 are patterned by a lithographic process, thereby forming a column of insulating film (I). 4A through 4D depict the formation steps of a drain 23, a channel 24, and a source region 25 of a transistor; in particular, FIGS. 4B and 4C are cross-sections taken along the lines AA' and BB' of FIG. 4A, respectively, and FIG. 4D is a perspective view taken along the aforementioned line BB'. A first n-type epitaxial semiconductor layer 23 is grown using the semiconductor substrate exposed by the insulation film column (I) as a seed. Then, a second p-type epitaxial semiconductor layer 24 and a third n-type epitaxial semiconductor layer 25 are sequentially grown on the first n-type epitaxial semiconductor layer 23, thereby forming a silicon column. The first n-type epitaxial semiconductor layer 23 is used as a seed. of the nMOS transistor, and the second p-type epitaxial semiconductor layer 24 and the third n-type epitaxial semiconductor layer 25 are respectively used as the channel and the source of the nMOS transistor. In this case, the first n-type epitaxial semiconductor layer - 23 which serves as a well zone, is connected to bit line 18. A p-type epitaxial semiconductor layer which will be used as the channel of the nMOS transistor can be grown to the top of the column of insulating layers (I), using the substrate exposed by the column of insulating layers (I) as a seed. After that, n-type ions of purity are implanted twice, i.e., with a high energy and a low energy respectively, to form the drain 23 and the source region 25 on the bottom and the top respectively of the p-type epitaxial semiconductor layer. Subsequently, the second insulating film 22 which constitutes the insulating film column (I) is removed and the resulting structure is shown in Figure 4D. Figures 5A through 5C depict the stages of formation of a gate insulating film 26 and a gate line 28, in particular, Figures 5B and 5C are cross-sections taken along the lines AA' and BE' of Figure 5A, respectively. A thermal oxidation process is performed on the resulting structure, in which the silicon column used as drain 23, channel 24, and source 25 of the transistor is formed, to thereby form the gate insulating film 26 on the surface of the silicon column. Then, after deposition of a layer 10 Studio Consulenza Brevettuale srl Bianchetti Giuseppe et al conductive layer, for example a polysilicon doped with impurities, on the resulting structure in which the gate insulating film 26 is formed, the conductive layer is configured with a lithographic process, thus forming the gate line 28 which surrounds the silicon column. At this point the bit line 18 on the trench insulation layer 12 and the gate line 28 are mutually insulated by the first insulating film 20. Figures 6A and 6B show the steps in the formation of a planarizing layer 30. After deposition of an insulating material on the resulting structure in which the gate line 28 is formed, the layer of insulating material is back-etched until the upper surface of the gate line 28 is exposed, thereby forming the planarizing layer 30 for the control of a step difference due to the silicon column. Figures 7A and 7B depict the formation steps of a contact hole and a first conductive layer 40. Insulating materials, e.g. a high temperature oxide (HTO) and a nitride, are sequentially deposited on the resulting structure in which the planarizing layer 30 is formed, thereby forming a first insulating layer 32 and a second insulating layer 34. At this point, a third insulating layer, e.g. composed of a high temperature oxide, may be formed on the second insulating layer 34. Thereafter, the second insulating layer 34, the first insulating layer 32, the gate line 28, and the gate insulating film 26 are stacked on the source zone 25. of the transistor, are attached using a lithographic process, to thus forming a contact hole (not shown) to expose the source zone 25. Then, an insulating material, for example, a high temperature oxide, is deposited on the resulting structure where the contact hole is formed, and is attached to thus form an insulating spacer 36 on the side of the contact hole. In this case, the insulating spacer 36 is provided to prevent a short circuit between the gate line 28 and a capacitor storage node that will be formed by a subsequent process. After this, impurity particles of type n are implanted + on the resulting structure where the insulating spacer 36 is located, thus forming a cap layer 38 type n + in the upper surface of the source zone 25. The cap layer 38 type n +is intended to decrease the contact resistance between the source zone 25 and the storage node that will be formed in the subsequent process. Then, a conductive material, for example a polysilicon doped with inpurity, is deposited on the resulting structure in which the n-type cap layer 38 is formed. + , thus forming the first conductive layer 40. FIGS. 8A and 8B depict the steps in the formation of a material configuration 42 and a second conductive layer 44, FIG. 8A being a plan view of the material configuration illustrated in FIG. 8B. A material subject to a different etch rate than the material constituting the first conductive layer 40 with respect to any ani-tropic etching process, e.g., a high temperature oxide, is deposited to form a layer of material (not shown) on the resulting structure in where the first conductive layer 40 is formed. Then, the material layer is configured by a lithographic process to thereby form the material configuration 42. Thereafter, a conductive material, which is subject to an etch rate different from that of the material constituting the material configuration 42 and which has an etch rate equal to or similar to that of the material constituting the first conductive material 40, for example an inpurity-doped polysilicon, is deposited on the resulting structure in which the material configuration 42 is formed, to thereby form the second conductive layer 44. Figures 9 and 10 show the steps in forming a capacitor storage node 46. A first and second conductive layer 40 and 44 are back-etched using the etch mask material pattern 42 to form the double cylindrical storage node 46 that connects to the source region 25 of the transistor. The material pattern 42 is then removed. Figures 11 through 17 are plan views and cross-sectional views illustrating a method of fabricating a semiconductor device in accordance with a second embodiment of the present invention. Figure 11 represents the formation steps of a 52a n-type epitaxial semiconductor layer. + , and of a first and second layer of material 54 and 56. The n-type epitaxial semiconductor layer 52a + is grown on a 50 p-type semiconductor substrate, using the substrate as a seed. In this case, it is obvious that the seed layer 52a n-type epitaxial conductor + can be formed by a yesterday's implantation process. Then, for example, an oxide and a nitride are sequentially deposited on the resulting structure in which the n-type epitaxial semiconductor layer 52a is formed + , to thus form the first layer of material 54 and the second layer of material 56. At this point, it should be noted that the second layer of material 56 must be high enough to match the height of the area where the transistor will be formed. Figures 12A and 12B show the formation stage of a bit line 52 and a trench insulation layer 60, and Figure 12B being a cross-sectional view taken along the line AA' of Figure 12A. After etching of the portion of the second and first material layers 56 and 54 where an insulation layer will be formed by a lithographic process, the n-type epitaxial semiconductor layer 52a + is etched using the remainder of the second and first material layers 56 and 54 as a mask. Subsequently, the substrate 50 is etched to a predetermined depth, thus forming a trench (not shown). At this point, the n-type epitaxial semiconductor layer 52a +is configured by the above mentioned etching process to form a recessed bit line 52, and simultaneously, a trench is formed which will be used as an isolation zone. Thus, an active zone and the recessed bit line 52 are formed at the same time. The active zones in the direction of the bit line (direction BB' in figure 12A) are connected without the isolation zone. chin. After that, to strengthen the electrical insulation between the devices, 57 ions of p-type purity are implanted. + on the resulting structure where the 52 bit line and the trench are formed, thus forming a p-type purity layer +58 below the bottom area of ​​the trench. Then, an insulating material, for example an oxide, is deposited over the entire surface of the substrate 50, and is back-attached, so as to fill the inside of the trench with the insulating material, thus forming the trench insulation zone 60. At this point, the layer of insulating material filling the trench insulation zone 60 is raised a little, in consideration of the second layer of fairly high material 56. Figure 13 depicts the formation steps of a drain 62, a channel 64, and a source region 66 of a transistor. After removal of the first and second material layers 54 and 56, a first n-type epitaxial semiconductor layer 62 is grown on the semiconductor substrate, except in the trench insulation region 60, using the substrate as a seed. Subsequently, a second p-type epitaxial semiconductor layer 64 and a third n-type epitaxial semiconductor layer 66 are grown on the semiconductor substrate, except in the trench insulation region 60, using the substrate as a seed. - are grown sequentially on the first n-type epitaxial semiconductor layer 62, thus forming a silicon column. The first n-type epitaxial semiconductor layer 62 is used as the drain of the nMCG transistor, and the second p-type epitaxial semiconductor layer 64 and the third n-type epitaxial semiconductor layer 66 are used as the channel and the source, respectively. people of the nMOS transistor. In this case, the first semiconductor layer n-type epitaxial tore - 62 which serves as the well zone, is connected to the n-type epitaxial semiconductor layer + which serves as bit line 52. Furthermore, a p-type epitaxial semiconductor layer - which will be used as the channel of the nMOS transistor, can be grown up to the top of the trench isolation zone 60, using the substrate, except the trench isolation zone 60, as a seed. After that, n~-type impurity ions are implanted twice, i.e., with high energy and low energy respectively, to thus form the drain 62 and the source zone 66 on the bottom and top respectively of the p~-type epitaxial semiconductor layer. Figure 14 shows the steps in the formation of a gate insulating film 68. To expose the silicon column used in the well 62, channel 64 and source 66 of the transistor, the layer of insulating material within the trench insulation zone 60 is etched up to the well zone 62. After this, a thermal oxidation process is performed on the resulting structure, thereby forming the gate insulating film 68 on the surface of the silicon column. Figures 15A and 15B show the stages of formation of a gate line 70; in particular, Figure 15A is a cross-section taken along line AA' of the plan view in Figure 15B, and the cross-sectional view shown in Figure 15B is taken along line BB. 1 of the above plan view. After deposition of a conductive layer, for example of pure doped polysilicon, on the resulting structure in which the gate insulation film 68 is formed, the conductive layer, the gate insulating film 68 and the silicon column are etched by a lithographic process, thereby forming the gate line 70 surrounding the silicon column. At this point, to insulate each transistor in the (BB* ) direction of the gate line, the above etching process to form the gate line 70 is continued up to the drain region 62 of the silicon column. Figure 16 shows the steps in the formation of a planarizing layer 72. After deposition of an insulating material on the resulting structure where the gate line 70 is formed, the insulating material layer is back-etched until the top surface of the gate line 70 is exposed, thus forming the planarizing layer 72 to control the step difference caused by the silicon column. At this point, the planarizing layer 72 completely fills the hole that was formed during the above etching process to form the gate line. Figure 17 depicts the steps in forming a contact hole and a first conductive layer 82. Insulating materials, for example, a high temperature oxide and a nitride, are sequentially deposited on the resulting structure in which the planarizing layer 72 is formed, thereby forming a first insulating layer 74 and a second insulating layer 76. Thereafter, the second insulating layer 76, the first insulating layer 74, the gate line 70, and the gate insulating film 68, which are stacked on the source region 66 of the transistor, are etched by a lithographic process, thereby forming a contact hole (not shown) to expose the source zena 66. Then, an insulating material, for example, a high-temperature oxide, is deposited on the resulting structure where the contact hole is formed, and is attached to form an insulating spacer 78 on the side of the contact hole. Subsequently, ions of n-type purity are implanted. + on the resulting structure where the insulating spacer 78 is formed, thus forming a type n cap layer + 80 in the upper surface of the source zone 66. Then, a conductive material, for example a polysilicon doped with inpurity, is deposited on the resulting structure hosting the n-type cap layer 80. + , thus forming the first conductive layer 82. After this, although not illustrated, the manufacturing process of the capacitor storage node is completed, according to the method described with reference to the first embodiment. According to the second embodiment of the present invention, the highly doped epitaxial semiconductor layer is simultaneously used as the active zone and the bit line, and the trench insulation zone and the silicon column can be formed by a single lithographic process, thereby omitting two lithographic processes. (According to the first embodiment, after the trench insulation zone is formed, a lithographic process of forming the insulating film column is required to form the bit line and the silicon column.) Figures 18 to 26 are plan views and cross-sectional views illustrating a method of manufacturing a self-contained device. microconductor according to a third embodiment of the present invention. Figure 18 represents the stages of formation of a layer of impurities type n. + cashed 102. A first hyena of type n inpurity +101 is implanted at high energy over the entire surface of a p-type semiconductor substrate - 100, to thus form the impurity layer type n + embedded 102 at a predetermined depth of the substrate 100. At this point, the embedded n-type impurity layer + 102 may be formed by an epitaxial process, and in this case, the recessed purity layer 102 is formed on the substrate 100. Figure 19 represents the formation phase of a surface impurity layer of type n 104. A second layer of impurity type n + 103 is implanted over the entire surface of the substrate 100 in which the embedded impurity layer type n is formed. + 102, thus forming the layer d 1 surface impurity type n + 104 in the surface of the substrate 100. The surface impurity layer type n + 104 is used as the source zone of an nMOS transistor, the n-type recessed impurity layer+ 102 is used as the well zone, and the p~ 100 type substrate placed between the two is used as the channel zone. In this case, when the embedded impurity layer type n + 102 is formed by an epitaxial process as described in Figure 18, a p-type epitaxial semiconductor layer is grown on the embedded n-type pure layer. + 102, and then an n-type epitaxial semiconductor layer is grown on top of it. + , so as to form the surface impurity layer type n + 104. furthermore, the surface impurity layer type n + 104 can be formed by depositing a doped polysilicon with n-type purity + on the substrate 100. Figures 20A and 20B show the formation step of a trench insulation layer 116. On the resulting structure where the well 102, the channel 100, and the source zone 104 are formed, a first oxide film 106, a polysil acetate film 108, a second oxide film 110, and a nitride film 112 are sequentially formed as a mask layer to form a trench insulation layer. Subsequently, the mask layer is etched by a lithographic process and the substrate 100 is etched deeper than the well zone 102 using the remaining mask layer as an etch mask, thereby forming a first trench (not shown). Then, to reinforce the electrical insulation between the devices, p-type ions are implanted. + 113 on the resulting structure in which the first trench is formed, thus creating a layer of impurities p +114 below the bottom area of ​​the first trench. After this, an insulating material, for example an oxide, is deposited over the entire surface of the resulting structure, and is back-attached so as to fill the inside of the first trench with the insulating material, thus forming the trench insulation zone 116. At this point, the layer of insulating material is back-attached to the first oxide film 106. Figures 21A through 21C represent the stages in the formation of a recessed bit line 122; in particular, Figures 21B and 21C are cross-sectional views taken along the lines AA' and BB' of Figure 21A. A predetermined portion of an active zone defined by the zena Trench insulation 116 is etched up to the well 102 using a lithographic process, thus forming a second trench (not shown) to form a recessed bit line. At this point, during the second trench etching process, the etch selectivity of the silicon and oxide filling the trench insulation 116 must be maintained at 1:1 to prevent the formation of a stepped portion in the recessed bit line. So, n-type impurity ions + 121 are implanted on the entire surface of the resulting structure where the second trench is formed, thus forming a layer of impurities type n +(not shown) under the bottom of the second trench. Next, a conductive material, such as a low-dope polysilicon, is deposited on the resulting structure where the second trench is formed, and is back-etched to embed bit line 122. Then, an oxide is deposited on the resulting structure where bit line 122 is formed, and said oxide is back-etched to form a first insulating film 124. A nitride is deposited on the first insulating film 124 and is back-etched to form a second insulating film 126. At this point, the nitride film 112 used as the mask layer is removed. After that, an oxide is deposited on the resulting structure and is back-etched to form a third insulating film 128. At this point, the second oxide film 110 used as the mask layer is removed.In this specific case, the location of the second insulating layer 126 composed of a nitride determines . the thicknesses of the bit line 122 and of the first insulating film 124 during a subsequent silicon column formation process, and prevents the generation of a goal post during a subsequent goal line etching process. Figures 22A and 22B represent the steps in the formation of a silicon column, in particular, Figures 22A and 22B are cross-sectional views taken along the lines AA' and BB' of Figure 21A. The insulating material layer within the trench insulation zone 116 is etched up to the well zone 102, thereby forming the silicon column composed of the well 102, the channel 100, and the source 104. At this point, the second insulating film 128 is also removed during this etching process, and the polysilicon film 108, used as a mask layer to form the trench insulation zone 116, prevents etching of the substrate zone where the silicon column will be formed. Thereafter, the polysilicon film 108 and the first oxide film 106 are all removed by a wet etching process. Figures 23A and 23B show the steps in the formation of a gate insulator film 130 and a bit line 132. A thermal oxidation process is performed on the resulting structure in which the silicon column is formed, thereby forming the gate insulator film 130 on the surface of the silicon column. Then, after deposition of a conductive layer, for example of a polysilicon doped with low purity, on the resulting structure in which the gate insulator film 130 is formed, the conductive layer is at- printed using a lithographic process, thus forming the line of gate 132 surrounding the silicon column. Figure 24 is a perspective view illustrating the resulting structure in which the gate line 132 is formed. Figure 25 shows the steps in the formation of a planarizing layer 134. After deposition of an insulating material on the resulting structure in which the gate line 132 is formed, the layer of insulating material is back-etched until the upper surface of the gate line 132 is exposed, thus forming the planarizing layer 134 to control the step difference caused by the silicon column. Figure 26 depicts the steps in forming a contact hole and a first conductive layer 144. Insulating materials, such as a high temperature oxide and a nitride, are sequentially deposited on the resulting structure in which the planarizing layer 134 is held, thereby forming a first insulating layer 136 and a second insulating layer 138. Thereafter, the second insulating layer 138, the first insulating layer 136, the gate line 132, and the gate insulating film 130 which are stacked on the source zone 104 of the transistor, are etched to form a contact hole (not shown) to expose the source zone 104. Then, an insulating material, such as a high temperature oxide, is deposited on the resulting structure in which the contact hole is formed, and is etched to form an insulating spacer 140 on the side of the contact hole. Next, n-type ions of inpurity + come im planted on the resulting structure in which the spacer is formed insulator 140, to form a narrow type n-shaped plug + 142 in the upper surface of the source zone 104. Then, a conductive material, for example, a pure doped polysilicon, is deposited on the resulting structure in which the n-type cap layer 142 is formed, thereby forming the first conductive layer 144. Subsequently, not illustrated, the fabrication process of the capacitor storage node is completed, according to the method described with reference to the first embodiment. According to the third embodiment of the present invention, the recessed bit line and the silicon column can be formed without selectively growing an epitaxial semiconductor layer. In addition, the contact hole area is reduced due to the recessed bit line area being located in the central part of the silicon column. Therefore, according to the invention described above, a recessed bit line structure and a vertical gate structure surrounding a silicon column are formed, thus making it possible to utilize the maximum effective active area. It is evident that, based on the above-mentioned example of preferred embodiment of the device according to the invention, the person skilled in the art will easily identify various changes and modifications that can be made to the executive details without departing from the spirit and scope of the invention. of the invention itself. RIYEHJICAZICNI 1. Semiconductor device comprising: a semiconductor substrate; a trench-like isolation zone formed to define an active zone in said semiconductor substrate; a bit line formed on said semiconductor substrate wherein said trench isolation zone is formed; a silicon column formed on said bit line, said silicon column containing the drain, channel, and source regions of a transistor, which are formed sequentially from a lower portion of said silicon column to an upper portion thereof; a gate insulating film and a gate line sequentially formed to surround said silicon column; a planarizing layer formed between said adjacent goal lines; an insulating layer formed over said gate lines, comprising a contact hole for exposing said transistor source zone; and a capacitor storage node formed on said insulating layer, which connects to said source node of said transistor through said contact hole.

Claims

2. A semiconductor device according to claim 1, wherein said bit line is formed by an epitaxial semiconductor layer.

3. A semiconductor device according to claim 1, wherein said bit line is formed with the same configuration as that of said active zone 4. A semiconductor device according to claim 1, wherein said silicon column is covered with an epitaxial semiconductor layer.

5. Semiconductor device comprising: a semiconductor substrate; a plurality of first trench isolation zones formed for the purpose of defining an active zone in said semiconductor substrate; a silicon column formed between said first trench insulation zones, said silicon column being composed of a source, a channel, and a drain of transistors, which are sequentially formed extending from a surface portion of said semiconductor substrate to a bulk thereof; a second trench formed up to said well zone of said silicon column, so as to connect one side of said silicon column; a bit line formed in a lower portion of said second trench; an insulating film formed so as to fill the inside of said second trench; a gate insulating film and a gate line sequentially formed to surround another side of said silicon column; a planarizing layer formed between said adjacent goal lines; an insulating layer formed on said gate lines, which ccrrporta a contact hole to expose said source area of ​​the transistor; and a capacitor storage node formed on said insulating layer, which connects to said source zone of said transistor through said contact hole.

6. A method of manufacturing a semiconductor device comprising the steps of: to form a trench isolation zone in order to define an active zone in a semiconductor substrate of a first conductivity type; forming a bit line on said semiconductor substrate where said trench isolation zone is formed; form a column of insulating film, consisting of a first insulating layer and a second insulating layer stacked on said first insulating layer, only on said trench insulation area; forming a silicon column, wherein the drain, channel and source regions of a transistor are formed sequentially from a lower portion of said silicon column to an upper portion thereof, on said semiconductor substrate exposed by said insulating film column; remove said second insulating film; forming a gate insulating film and a gate line sequentially so as to surround said silicon column; deposit an insulating material on the resulting structure in which said goal line is formed, and retro-attach said material insulator to form a planarizing layer; form an insulating layer on the resulting structure in which said planarizing layer is formed; partially etching said insulating layer thereby forming a contact hole to expose said source zone in said silicon column, and form a capacitor storage node, which connects to said source node through said contact hole, on the resulting structure in which said contact hole is formed.

7. A method of manufacturing a semiconductor device according to claim 6, wherein said bit line is composed of a layer of inpurity doped polysilicon.

8. A method of manufacturing a semiconductor device according to claim 6, wherein said step of forming said silicon column comprises the steps of: forming, on said semiconductor substrate exposed by said column of insulating film, a first epitaxial semiconductor layer of a second conductivity type, which is used in the drain region of a transistor; forming, on said first epitaxial semiconductor layer, a second epitaxial semiconductor layer of said first conductivity type, which is used as a channel of the transistor; and form on said second epitaxial semiconductor layer a third epitaxial semiconductor layer of said second type of conductivity, which is used in the source area of ​​the transistor.

9. Method for the manufacture of a semiconductor device if according to claim 6, wherein said step of forming said silicon column comprises the steps of: forming an epitaxial semiconductor layer of said first conductivity type on said semiconductor substrate exposed by said column of insulating film; implanting a first ion of purity of a second conductivity type, with a first energy, onto the resulting structure in which said epitaxial semiconductor layer is formed, thereby forming a transistor well zone in a lower portion of said epitaxial semiconductor layer; and implanting a second purity hyphen of a second conductivity type, with a second energy which is lower than said first energy, onto the resulting structure in which said drain zone is formed, to thereby form a source zone of the transistor in an upper portion of said epitaxial semiconductor layer.

10. A method of manufacturing a semiconductor device according to claim 6, wherein said step of forming said storage node of said capacitor comprises the steps of: form a first conductive layer on the resulting structure in which said contact hole is formed; forming a material configuration on said first conductive layer; form a second conductive layer on the resulting structure in which this material configuration is formed; retro-attach said second and first conductive layers; and remove said material configuration.

11. A method of manufacturing a semiconductor device comprising the steps of: forming a conductive layer and a material layer sequentially on a semiconductor substrate of a first conductivity type; attaching said material layer, said conductive layer, and said semiconductor substrate to thereby form a bit line and a trench, simultaneously; fill the inside of said trench with an insulating material, thus forming a trench insulation zone; remove said layer of material; forming a silicon column wherein the drain, channel, and source regions of a transistor are formed sequentially from a lower portion of said silicon column to an upper portion thereof, on said semiconductor substrate except in said trench insulation region; attaching said layer of insulating material within said trench insulation zone up to said well zone in said silicon column; form a gate insulating film and a gate line sequentially so as to surround the «silicon column slice; deposit an insulating material on the resulting structure in which said goal line is formed, and back-attach said insulating material lante to form a planarizing layer; form an insulating layer on the resulting structure in which it is format called planarizing layer; partially attach, said insulating layer, thus forming a contact hole for exposing said source zone in said silicon column, and form a capacitor storage node, which connects to said source zone through said contact hole, on the resulting structure in which said contact hole is formed.

12. A method of manufacturing a semiconductor device according to claim 11, wherein said bit line is formed by an epitaxial process.

13. A method of manufacturing a semiconductor device according to claim 11, wherein said step of forming said gate insulating film and said gate line comprises the steps of: form an insulating film of door on a surface of said silicon column; form a conductive layer on the resulting structure in which it is formed said door insulating film; and attaching said conductive layer, said gate insulating film, and said silicon column up to said well region, thereby forming a gate line surrounding said silicon column.

14. A method of manufacturing a semiconductor device comprising the steps of: form a layer of embedded impurities of a second type of con- 31 Studio Consulenza Brevettuale srl Bianchetti Giuseppe et al conductivity in a semiconductor substrate of a first type of conductivity; forming a surface impurity layer of said second conductivity type in a surface of said semiconductor substrate in which said embedded impurity layer is formed; forming a first trench isolation zone in order to define an active zone in said semiconductor substrate in which said surface impurity layer is stopped; attaching the «semiconductor substrate roof of said active zone portion to a depth greater than that of said embedded impurity layer, thereby forming a second trench; form a bit line in a lower part of «second trench breast; fill the inside of the second chamber with an insulating material cea in which a certain bit line is formed; attaching said first trench insulation zone up to the «top» recessed layer of impurity, thereby forming a silicon column consisting of said recessed layer of impurity of said second conductivity type, said semiconductor substrate of «top» first conductivity type, and «top» surface layer of impurity of said second conductivity type; form a gate insulating film and a gate line sequentially, so as to surround said silicon column; «to place an insulating material on the resulting structure in which is formed the so-called goal line, and to attach back «roof insulating material lante to form a planarizing layer; form an insulating layer on the resulting structure where said planarizing layer is formed; partially etching said insulating layer to thereby form a contact hole to expose said surface purity layer in said silicon column; and forming a capacitor storage node, which connects to said surface layer of impurity through said contact hole, on the resulting structure in which said contact hole is formed.

15. A method of manufacturing a semiconductor device according to claim 14, wherein said recessed pure layer and said surface pure layer of said second conductivity type are formed by an epitaxial process.

16. A method of manufacturing a semiconductor device according to claim 14, wherein said embedded impurity layer of said second conductivity type is formed by implanting a first impurity layer of said second conductivity type with a first energy onto said semiconductor substrate, and said surface impurity layer of said second conductivity type is formed by implanting onto said semiconductor substrate a second impurity layer of said second conductivity type, with a second energy which is lower than the first energy. of the said first energy Milan, May 24, 1994 The Agent (Bracco Mauro) of Studio Consulenza Brevettuale srl