DISPOSITIVO A SEMICONDUTTORE AVENTE UNA PELLICOLA DI SILICIO FORTEMENTE DROGATA

Abstract

A method for manufacturing a semiconductor device comprising the steps of depositing a silicon film on an underlying layer while doping with phosphorus to a concentration of 7 x 1020 to 2 x 1021 atoms / cm3, and then heating the film of silicon. A semiconductor device having a silicon film with a sufficiently small resistance is envisaged ( Fig. 1 ).

Description

. 2 _ STUDIO PATENTS JAUMANN di Baumann P. & C. snc MILAN - P_2a Castello n. 2 - Company: FUJ-I-TSU—L-1M-TT-ED____________________________________a &________ Mi 94 A 0 sede 'T'.K'awasaki-shi; Kanàgìawa (Giappone) 02678 **** #*#* ***-«- nA ia A 4 no / 3u D TECHNICAL BACKGROUND OF THE INVENTION C .1994 « a) Field of the invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device comprising - a step for depositing a silicon film. b) Description of the related technique A silicon film doped with impurities is electrically conductive and can be used as a conductive element. It can be doped with impurities simultaneously when a film is formed or by ion implantation or diffusion after the film has been formed.Impurity-doped silicon films are used as MOSFET gate electrodes, polycide gate electrode parts (polycrystalline silicon and silicide lamination), DRAM capacitor electrodes, circuit boards, and polycide circuit parts. The resistivity of a silicon film used as a conductive element is preferably made as low as possible. The resistivity depends on the mobility of the carriers and the concentration of the carriers. It is more . It is preferable to use polycrystalline silicon over amorphous silicon in order to increase the mobility of carrier elements. Although higher mobility has been achieved using monocrystalline silicon, it is generally and practically difficult to form a monocrystalline silicon film on the surface of a substance other than silicon. A contraction of carrier elements is essentially proportional to a doped amount of impurity, and is limited by a solid solubility of an impurity element in silicon. Therefore, in order to form a silicon film having a low resistivity, a polycrystalline silicon film is formed doped with impurities to a concentration close to solid solubility. Phenylephrine is most commonly used as the n-type impurity of a silicon film, and boron as the p-type impurity.In a DRAM, a memory cell unit consists of n-type MOSFETs and a peripheral circuit unit consists of CMOS circuits of n- and p-channel MOSFETs. Phosphorus as an n-type impurity is therefore the most important. BRIEF SUMMARY OF THE INVENTION As will be explained in detail later, it has been found that the resistivity of a silicon film doped with phosphorus to a concentration close to a solid solubility limit becomes higher than a design value after the fabrication processes are completed. It is an object of the present invention to provide a method for fabricating a semiconductor device having a silicon film having a sufficiently low resistivity after completion of the device fabrication processes. According to one aspect of the present invention, a method of fabricating a semiconductor device is provided comprising the steps of depositing a silicon film on an underlying layer by doping with phosphorus up to a concentration of 7 x 10⁰ to 2 x 10⁰ atoms / cm⁰, and subsequently heating the silicon film. The phosphorus with a density of 7 x 10⁰ atoms / cm⁰ significantly exceeds the solid solubility limit of silicon.However, even if the phosphorus comes out of the silicon film in the final heat treatment, a sufficient amount of phosphorus is retained in the silicon film and a low resistivity is achieved because the phosphorus initially overdopes the silicon film. In this way, it is possible to have a desired low resistivity of a thin silicon film of a semiconductor device after the completion of fabrication processes. It is also possible for a capacitor using a thin silicon film to suppress a depletion width and reduce a change in capacitance. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A through 1C are a graph showing the resistivity of a thin film of phosphorus-doped silicon as a function of phosphorus concentration, and simplified cross-sectional views showing sample structures. FIGS. 2A and 2B are a graph explaining a definition of a depletion ratio of a capacitor using a thin film of silicon and a graph showing a depletion ratio as a function of phosphorus concentration immediately after the film has been doped. FIGS. 3A through 3L are simplified cross-sectional views explaining a method of fabricating a DRAM in accordance with an embodiment of the invention. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS As the degree of integration of semiconductor integrated circuit devices increases, their structure tends to have many layers.In order to ensure good coverage of a film formed by a method of fabricating a semiconductor device having a multilayer structure, it is desired that the thickness of each layer of the device be as thin as possible. If it is desired that the resistance of a silicon film having a thin structure be low, the resistivity is required. of silicon is as thin as possible. It was found that the resistivity of a thin silicon film used in a semiconductor device becomes higher than a design value after the device's fabrication processes are completed. 3 To study the causes of this phenomenon, the inventors performed the following experiments. Thin films of amorphous (a-) silicon were formed while simultaneously doping them with impurities. An oxide film was deposited at low temperature on the surface of each thin amorphous silicon film to encapsulate the doped impurities. The device was then annealed at a temperature of 850°C for 20 minutes in an atmosphere of N oto transform amorphous silicon into polycrystalline silicon, and then the oxide film was removed using an aqueous HF solution. Subsequently, the surface resistances were measured. Each surface resistance is usually used as a standard design data. In order to simulate a silicon film in a real device, a structure was formed ; I correspond 1 1. A DRAM fin-type capacitor was used using a phosphorus-doped amorphous silicon film, subjected to a heat treatment similar to a DRAM manufacturing process, and the resistance was then measured. Surface resistance of the silicon film. The results are shown in Fig. 1A. In Fig. 1A, the x-axis represents a phosphorus concentration on a linear scale immediately after film formation, and the y-axis represents a resistivity xxcm on a linear scale. A r2 curve represents the resistivity of samples that have an impurity-doped amorphous silicon film, covered with an oxide film, and annealed at 850°C for 20 minutes. A r2 curve represents the resistivity of samples that have an impurity-doped amorphous silicon film, having a structure equivalent to a DRAM fin-type capacitor electrode, and subjected to a heat treatment process that real devices undergo. Figs. 1B and 1C show the structures of samples used in the experiments. The structure of the samples used for measuring the r2 curve is shown in Fig. 1B.A silicon oxide film 43 was formed on a silicon substrate 42, and an amorphous film 44 was formed on the silicon oxide film 43. The amorphous silicon surface 43 was covered with an oxide film, and the device was annealed (to change the amorphous silicon to polycrystalline silicon). The surface oxide film was then peeled away, again assuming the structure shown in Fig. 1B. Under this condition, the re- . The strength of film 44 was measured by a 4-probe method. Fig. 1C shows the main structure of the sample used for measuring the r2 curve. This structure is similar to a film 22 shown in Fig. 5, which will be described later. An amorphous silicon structure 46 was tested on a region 45 of silicon oxide film, and the surface of structure 46 was covered with a silicon oxide film 47. Contact holes 48a and 48b were formed in silicon oxide film 47, and conducting electrodes 49a and 49b were joined to structure 46. The silicon film was formed at a substrate temperature of 500°C by flowing disilane (SiH2) at 50 sccm as the silicon source and flowing a mixed gas of a gas and a mixed gas with 2% phosphine (PH2) at 270 sccm as the phosphorus source.The flow of silane was kept constant, and the total flux of PH^ / N^ was also kept constant. A variety of phosphorus concentrations were prepared by changing the flow ratio of PH^ / N^ gas to N^ gas. The silicon film of the sample for curve r1 has a large area with a thickness of approximately 1000 angstroms, and the resistivities were measured with 4 probes. The silicon film of the sample for curve r2 has a thickness of approximately 50 nm and has a stripe shape of 6.5y^m x 65 / C / m. As seen in Fig. 1A, the resistivities of the r2 curve are twice or greater than the resistivities of the r1 curve. The resistivities of the r2 curve become 5 times or greater than those of the r1 curve, especially for a phosphorus concentration near a solid solubility limit of phosphorus in silicon of 3 - 4 x 10 atoms / cm². It is preferable to select the phosphorus concentration using the r2 curve in order to use a fin-type capacitor and achieve the lowest possible reactivity there. In this case, the optimum phosphorus concentration is approximately 1 x 10 atoms / cm², and it is preferable to select the concentration in the range from 20.3 to 7 x 10 atoms / cm² to 2.0 x 10 atoms / cm². The difference between the resistivities can result from the following causes.The phosphorus in a thin silicon film covered (at least partially covered) with another film diffuses into the other film by heat treatment of the thin film, by subsequent heat treatments, or by external diffusion as the other film is being formed. Thus, the phosphorus concentration gradually decreases immediately after film formation, and the phosphorus concentration after completion of the device manufacturing processes deviates significantly from that immediately after film formation. _____________The reason why the minimum resistivity value of the r2 curve is much larger than the minimum resistivity value of the r curve is presumed to be due to a difference in film thickness between the samples: a difference in crystal properties between polycrystalline silicon changed from amorphous silicon by heat treatment, and the like. A DRAM capacitor is desired to have a low electrode resistivity and a design capacitance. If the capacitor electrodes are made of silicon films and the impurity concentration is low, a depletion layer grows from the capacitor electrode surface when a reverse bias voltage is applied, and the gap between the electrodes becomes large and consequently the capacitance is lowered. As shown in Fig.2A, capacitances were measured by setting a capacitance electrode to 0 V and changing a voltage at an opposite electrode from -1.5 to 1.5 V. A depletion ratio is defined as dC / Co where Co is a capacitance for a forward bias of +1.5 V at the opposite electrode and -i^C is a reduction in capacitance when the voltage at the opposite electrode is changed to a reverse bias of -1.5 V. a As a sample, a silicon nitride (SIN-) film was formed on a silicon film until . a thickness of 7 nm, and was oxidized to fill a silicon oxynitride film having a thickness of about 6 nm based on one unit of SiO^ (calculated from a measured capacitance), -------------- an opposing electrode was formed on the silicon oxynitride film by phosphorus to dope up to a 20, 3, concentration of about 7 x 10 atoms / cm ). When a voltage of -1.5 V is applied to the opposite electrode, a reverse bias voltage is applied to the surface of the capacitor electrode and a depletion layer grows on the surface of the capacitor electrode. The height of the depletion layer becomes large as the impurity concentration is lowered. - silicon film quality of the capacitor electrode. Fig. 2B is a graph showing a change in the depletion ratio as a function of phosphorus concentration in the capacitor electrode immediately after film formation. The x-axis represents the phosphorus concentration in atoms / cm immediately after film formation, and the y-axis represents the depletion ratio in percent.The experimental sample is similar to a fin-type condenser shown in Fig. 1C. The depletion ratio indicated in curve d is approximately 10% for a solid solubility limit of . 20 , 3 phosphorus from 3 to 4 x 10 atoms / cm . The shift ratio decreases as the phosphorus concentration increases and ranges from about 1 to 3% for about 7.0 x 10 atoms / cm and a negligible value at 1.5 x 10 atoms / cm or greater. Therefore, to have a constant value of a capacitor, a silicon film for a capacitor electrode is made to have at least a phosphorus concentration of 7.0 x 10 atoms / cm and preferably a higher concentration. It is also preferable that the phosphorus concentration does not exceed 2 x 10 atoms / cm . Phosphorus can be doped into a silicon film up to a concentration of 20 . 3 at least 7.0 x 10 atoms / cm corresponds to phosphors to dope equal to about twice the solid solubility limit of phosphorus immediately after film formation.The fabrication processes of a DRAM will be described with reference to Figs. 3A to 31. As shown in Fig. 3A, on the surface of a T-type silicon substrate 1, a field oxide film 2 up to a thickness of about 400 nm is formed by LOCOS oxidation using a silicon nitride film as a mask. After LOCOS oxidation, the silicon nitride film is removed and a gate oxide film 3 up to a thickness of about 10 nm is formed on the exposed silicon surface, for example by dry oxidation at a temperature of about 1000 °C. — ______________A Si gate electrode oxide layer 4 is formed to a thickness of approximately 300 nm over the gate oxide film and the field oxide film 2 by low pressure CVD at 0.2 Torr, at a substrate temperature of 500°C, by flowing SiH at 50 sccm and flowing 2% PH / N + N at 270 sccm. A spare configuration is formed on the gate electrode layer and is configured to form gate electrodes 4a and 4c and electrical connections 4b. The gate length of gate electrodes 4a and 4c is, for example, about 0.5 A / m. A MOSFET using gate electrode 4c is a peripheral circuit transistor and is formed in a peripheral circuit region of a DRAM. A MOSFET using gate electrode 4a is shown on the left side of Fig. 3B.and electrical connection 4b are formed in a memory cell region of the DRAM. In Figs. 3A to 3L they are shown in adjacent areas to simplify the drawings. Next, as shown in Fig. 3B, using gate electrodes 4a and 4b as a mask, phosphorus ions with an acceleration energy of 13-2 . ​​-. . 20 keV and a dose of 10 cm 3 are implanted to form n-• type regions 6 and 7 which are source / drain regions of the MOSFET in the memory region and impurity concentration regions of an LDD structure of the MOSFET in the peripheral circuit region. rico. As shown in fig. 3C, a film 8 of <Xa5ido per alta temperatura (HTO) viene formata sopra la super ficie di substrato fino ad uno spessore di circa 100 nm media i te CVD ad una temperatura di substrato di circa 800 °C.impieg m do SiH + N 0. Successivamente, una maschera 9 di riserva vie 4 2 - • - - - - - — ne formata sulla superficie di substrato per coprire la regio ne di memoria. Impiegando la maschera 9 di riserva come masch ra di incisione, la pellicola 8 HTO viene incisa verticalmen- te mediante incisione di ioni reattivi. Viene asportata la pe; licola 8 HTO formata su un piano piatto dell'area di circuito periferico, e la pellicola 8 HTO formata sui lati dell'elettro do 4c di gate viene lasciata non incisa per formare pareti la terali 8W. In seguito, viene asportata la maschera 9 di riser- va. Come mostrato nella fig. 3D, viene depositata una altra pellicola 10 HTO fino ad uno spessore di 100 nm median- te un processo simile.As shown in Fig. 3E, the 10 HTO film is subjected to reactive ion etching to remove the HTO film on the flat plane and to leave the HT( film in the stepped portions to form 10w sidewalls. Using the high-temperature oxide film, sidewalls, and gate electrodes as a mask, phosphorus ions with an energy of are implanted. 15 -2 acceleration of 20 KeW and with a dose of 10 cm to form 11 regions of the n-type +which are source / drain regions in a peripheral circuit transistor. As shown in Fig. 3F, another HTO film 12 is formed to a thickness of about 100 nm by a similar process. A reserve mask is then formed on the HTO film 12, and apertures 13 are formed in contact regions of the MOSFETs. The size of the aperture is, for example, 0.5 square µm. As shown in Fig. 3G, an amorphous silicon layer 14 having a thickness of about 50 nm and a WSi layer 1E having a thickness of about 100 nm are deposited by low-pressure CVD in that order over the substrate surface while embedding the silicon surface covered in the apertures 13. A reserve mask is then formed on the surface. The etching is performed to configure the amorphous silicon layer 14 and the WSi layer 15 to form polycide electrodes.Depositing the amorphous silicon layer 14 can be accomplished by a procedure similar to depositing the amorphous silicon layer shown in Fig. 3A. As shown in Fig. 3H, another HTO film 16 is deposited and the HTO film on a flat plane is removed by RIE to form sidewalls 16 on the sides. of the electrodes. Another HTO film 17 is deposited to a thickness of about 100 nm. Deposition of these HTO films can be accomplished at substrate temperatures of 800°C as HTO films 8, 10, and 12. A SiN film 18 is formed on the HTO film 17 to a thickness of about 50 nm at a substrate temperature of 775°C. An HTO film 20 is deposited to a thickness of about 50 nm at a substrate temperature of 800°C. Next, a layer 22 of amorphous silicon 20 is doped with phosphorus to a concentration of 7 x 10 .3d. atoms / cm / larger is deposited up to a thickness of about 50 nm at a substrate temperature of 500°C under the conditions of a pressure of 0.2 Torr, a flow of SiH - . 9 £ . PH / N 3 2 at 50 sccm, a flow of / at 2% at 110 sccm, and a flow of N at 160 sccm.Next, an HTO film 24 is deposited to a thickness of about 50 nm at a substrate temperature of 800°C. After these deposition processes are completed, a reserve mask is formed on the substrate surface, and an opening * 25 of about 0.5 ^m square is formed, reaching one of the source / drain regions 6 of the MOSFET in the memory region. The reserve is then removed. As shown in Fig. 31, a sili layer 28. This amorphous silicon layer 22 is doped with phosphorus to a concentration of 20.3 7 x 10 atoms / cm or greater and deposited to a thickness of about 50 nm on the surface of the HTO film 25 under the same conditions as the amorphous silicon layer 22 shown in Fig. 3H (at a substrate temperature of 500°C, at a pressure of 0.2 μmol / L, for a SiH flow at 50 sccm, for a 2% PH / N flow at 110 sccm, and for a N flow at 160 sccm). Subsequently, annealing is performed at a temperature of about 800°C in a β atmosphere to transform the amorphous silicon layers 22 and 28 into polycrystalline silicon. The previously formed amorphous silicon layers 4 and 14 are also transformed into polycrystalline silicon by this annealing process or by subsequent heat treatments.A backup mask is then formed on the substrate surface, and amorphous silicon layers 28 and 22 and the HTO film 24 between them are patterned by RIE. In this way, a capacitor electrode of a DRAM memory cell capacitor is formed. As shown in Fig. 3J, the substrate is immersed in an aqueous HF solution to remove the exposed HTO films 20 and 24 on the substrate surface. When the HTO films 20 and 24 are removed, the hidden fin-like surfaces are exposed. — A SiN film 29 to a thickness of about 6 nm is formed by high-pressure CVD at a substrate temperature of 725°C. The fin-coated surfaces are covered with the SiN film 29. Subsequently, the surface of the SiN film 29 is oxidized at a substrate temperature of approximately 800°C in a humid oxidizing atmosphere. In this way, a capacitor insulating film 29 is formed. As shown in Fig. 3K, by a similar process for depositing amorphous silicon layers shown in Figs. 3H and 3Z, a layer 30 of amorphous silicon doped with phosphorus impurities to a concentration of 7.0 x 10 to 1.2 x 10 atoms / cm is deposited to a thickness of, for example, 100 nm to bury the fin spacing and to cover the entire fin surface.A backup mask is formed on the deposited amorphous silicon layer 30 to configure the amorphous silicon layer 30 and to deposit beneath the SiN layer 18. -----------------------------------—--------—---------x-- Next, the backup mask is removed. — As shown in Fig. 3L, an HTO film is deposited to a thickness of about 50 nm at a substrate temperature of 800°C and then a BPSG (boron phosphorus silicate glass) layer 32 is deposited to a thickness of about 400 nm. Next, the substrate is heated to 850°C to melt the BPSG layer 32. and to flatten or planarize its surface. A reserve mask is formed on the flattened BPSG layer 32, and an aperture 33 is formed by RIE in the output electrode region of the MOSFET in the peripheral circuit unit by RIE. Next, an Al electrode layer is deposited and patterned to form Al electrical connections 35. By the above processes, a DRAM device is fabricated. In the above description, phosphorus is doped into the silicon electrode of a DRAM capacitor up to 20 3 at a concentration (7 x 10 atoms / cm or greater) twice or greater than the solid solubility limit of the phosphorus. The concentration of the doped phosphorus is preferably chosen taking into account a thickness of the silicon film to be deposited, and the subsequent heat treatments.Phosphorus twice or greater than the solid solubility limit can be doped when the silicon layer 4 of the gate electrode and the underlying silicon layer 14 of the polycide electrodes are formed. To form a polycrystalline silicon or amorphous silicon electrode, it is preferable to set the initial phosphorus concentration of the silicon layer from 7.0 x 10 to 21.0 x 10 atoms / cm . In the case of a polycide electrode formed by laminating a polycrystalline silicon layer and . of a silicide layer, it is preferable to set the initial phosphorus concentration from 1.0 x 10 to 2.0 x 10 atoms / 3 x n... because the phosphorus in the silicide layer, <od esempio silicuro di tungsteno (WSi) tende a uscire e ciò , dàllo, sttòto. Nel formare un elettrodo di condensatore di un cor densatore, è preferibile fissare la concentrazione iniziale di 2121. 3 phosphorus concentration from 1.2 x 10 to 1.6 x 10 atoms / cm because the effect of depletion on device performance is large and phosphorus leaks out (leaves) during formation of an HTO film or during annealing. When forming an opposite electrode of a capacitor, it is preferable to set the initial phosphorus concentration from 7.0 x 10 to 1.2 x 10 atoms / cm because the effect of depletion on device performance is large even though the film thickness is relatively large. The present invention has been described with reference to preferred embodiments. The invention is not limited to the foregoing embodiments. For example, instead of disilane, other silicon sources, such as monosilane, may be used, although the deposition rate is slower.Instead of an HTO film, any other insulating film can be used. The invention is applicable not only to DRAM devices but also to other . Semiconductor devices employing conductive silicon films. It is apparent to those skilled in the art that various modifications, improvements, combinations, and the like may be made without departing from the scope of the appended claims. 12. The method according to claim 1, wherein said silicon film is used for a capacitor electrode of a capacitor, and said phosphorus concentration is set from 1.2 x 10 to 1.6 x 10 atoms / cm 2 . 13. The method according to claim 1, wherein said silicon film is used for an opposing electrode of a capacitor, and said phosphorus concentration is set from 7.0 x 10 to 1.2 x 10 atoms / cm 2 . The Representative (Paolo Jaumann) of the f} A \IL / .____ stO| - ______________________________Ai launu -- intr'p. & C- Sn-C*___________ —

Claims

CLAIMS I. Method of manufacturing a semiconductor device comprises the steps of: depositing a silicon film on an underlying layer by means of phosphor to spread up to a concentration of 7 x 10 to 2 x 10 atoms / cm; and thereafter heating said silicon film 2. A method according to claim 1, wherein said silicon film is an amorphous silicon film and said heating step is performed at a temperature which allows the amorphous silicon to change into polycrystalline silicon.

3. Method according to claim 2, wherein said heating step comprises a step of depositing a film on said amorphous silicon film. The method according to claim 2, wherein said heating step comprises a step of depositing a silicide film on said amorphous silicon film.

5. Method according to claim 2, wherein said deposition step of said amorphous silicon is a CVD using disilane (Si ^ H ^) and phosphine (PH o ) as source gas. The method according to claim 3, wherein said underlying layer is a gate oxide film formed on a silicon substrate and the method further comprises the step of configuring said amorphous silicon film and forming sea ​​a gate electrode. The method according to claim 3, wherein said underlying layer is formed on a silicon substrate and has a laminated layer structure with an insulating film between the layers as the top layer and a contact hole which exposes the surface of the silicon substrate.

8. Method according to claim 7, further comprising the step of depositing a silicon film on said insulating film between the layers, said silicon film being doped with phosphorus up to a concentration of 20 21, 3. 7 x 10 to 2 x 10 atoms / cm.

9. The method according to claim 4, wherein said underlying layer is an insulating film between layers formed on top of a substrate / semiconductor, and the method further comprises the step of configuring said silicon film and said amorphous silicon film to form a configuration. of electrical connections.

10. A method according to claim 1, wherein said silicon film forms an electrode of polycrystalline or amorphous silicon, and said concentration of phosphorus is fixed from 7.0 x 10 to 1.0 x 10 atoms. cm.

11. A method according to claim 1, wherein said silicon film forms a part of a polyci de 21 electrode and said phosphorus concentration is fixed at 1.0 x 10 £ 1 3_a 2, 0_x 10 atoms / cm