Integrated circuit (IC) package employing a wire bond channel above a package substrate, and related manufacturing method

Abstract

An integrated circuit (IC) package employing a wire bond channel above a package substrate, and related manufacturing methods. The IC package includes a first semiconductor die (“the first die”) and a first electronic device each coupled to the package substrate. To provide a signal routing path between the first die and the first electronic device, the IC package includes a wire bond channel including a wire bond coupled between a first metal pad and a second metal pad respectively coupled to the first die and the first electronic device to provide a signal routing path between the first die and the first electronic device. The wire bond extends outwardly from the package substrate in a vertical direction. The wire bond channel can support a more direct signal routing path between the first die and the first electronic device without the need to route such a signal routing path around the KoZ within the package substrate.

Description

Technical Field

[0001] Priority Application This application claims priority to U.S. Patent Application No. 17 / 809,675, filed Jun. 29, 2022, entitled "INTEGRATED CIRCUIT (IC) PACKAGES EMPLOYING WIRE BOND CHANNEL OVER PACKAGE SUBSTRATE, AND RELATED FABRICATION METHODS", which is incorporated herein by reference in its entirety.

Background Art

[0002] Field of Disclosure The technical field of the present disclosure relates to integrated circuit (IC) packages including one or more semiconductor dies supported by a package substrate, and more particularly, to communicatively coupling semiconductor dies within an IC package to another electronic device (e.g., another die) within the IC package.

[0003] Background Integrated circuits (ICs) are the foundation of electronic devices. An IC is packaged in an IC package, also called a "semiconductor package" or "chip package". The IC package is attached to and electrically coupled to a package substrate to provide physical support and an electrical interface for one or more semiconductor dies (the "dies" or "dice"). The die(s) are electrically interface-connected to metal interconnects (e.g., metal traces, metal wires) in the topmost metallization layer of the package substrate. The package substrate of the IC package may also include one or more other metallization layers including metal interconnects (e.g., metal traces, metal wires) with vertical interconnect access (vias) that couple the metal interconnects to each other between adjacent metallization layers to provide an electrical interface to the die(s) through the package substrate. The package substrate also includes a bottom outer metallization layer including metal interconnects coupled to external metal interconnects (e.g., ball grid array (BGA) interconnects) to provide an external interface between the die(s) within the IC package. The external metal interconnects may also be coupled (e.g., soldered) to traces in a printed circuit board (PCB) to attach the IC package to the PCB and interface-connect its die(s) to other circuit components coupled to the PCB.

[0004] A plurality of ICs can be mounted on a package substrate within an IC package. For example, the IC package can include a system-on-a-chip (SoC) die and a second die coupled to the package substrate. The second die can include, for example, a security circuit, memory, or other circuitry that is desired to be provided within a die separate from the SoC within the IC package. To provide a communication interface to the second die, the second die is coupled to metal lines (e.g., metal traces) within one or more metallization layers of the package substrate. These metal lines provide signal routing through the package substrate to and from the second die. For example, some of these metal track lines can be routed and coupled to the SoC die to support die-to-die (D2D) communication between the SoC die and the second die. The second die can be disposed on or adjacent to an outer metallization layer of the package substrate to enable closer connectivity to the SoC die. The second die can also be coupled to metal lines within a lower metallization layer of the package substrate below the outer metallization layer. The placement of the second die on the package substrate results in a keep out zone (KoZ) region within the package substrate, where other metal lines for routing other signals to other electronic devices within the IC package avoid it and are routed to bypass it in the first, horizontal directions (X-axis and Y-axis directions). For example, the metal lines within the metallization layer of the package substrate that route signals between the SoC die and other electronic devices within the IC package may need to be routed to bypass the KoZ region of the second die within the package substrate. This results in longer lengths of these signals being conveyed through these other metal lines routed to bypass the KoZ region, thereby increasing the signal path impedance and causing further signal delay in such signals. Also, the routing of the metal lines that bypass the KoZ region may require the metal lines to have more bends, which contributes to an increase in parasitic capacitance.Routing of metal lines that detour around the KoZ region can also result in a decrease in the efficiency of signal routing and the use of routing space within the package substrate, which can lead to an increase in the area (the first in the horizontal direction, in the X and Y axis directions) and / or the number of metallization layers (in the vertical height, in the Z axis direction) required within the package substrate to provide sufficient signal routing, increasing costs.

Summary of the Invention

[0005] Aspects disclosed herein include integrated circuit (IC) packages employing wire bond channels above a package substrate. Related manufacturing methods are also disclosed. The IC package includes a first semiconductor die ("first die") (e.g., a system-on-chip (SoC) die) coupled to a first, horizontally extending package substrate. The first die is coupled to metal interconnects within the metallization layer(s) of the package substrate for routing signals through metal lines within the metallization layer(s) to and from the first die. The IC package also includes a first electronic device coupled to the package substrate. The first electronic device can be disposed on the package substrate such that a keep-out zone (KoZ) within the package substrate is wholly or partially within a direct signal routing path between the first electronic device and the first die within the package substrate. For example, the KoZ can be the result of another electronic device disposed on the package substrate between the first die and the first electronic device. In another example, the KoZ can be the result of other signal routing paths within the package substrate. In an exemplary aspect, to provide a signal routing path between the first die and the first electronic device within the IC package, the IC package includes a wire bond channel coupled to the first die and the first electronic device. The wire bond channel includes a first metal pad coupled to the package substrate and the first die. The wire bond channel also includes a second metal pad coupled to the package substrate and the first electronic device. The wire bond channel includes wire bonds coupled to the respective first and second metal pads to provide signal routing pads and to provide a signal routing path between the first metal pad and the second metal pad. The wire bonds extend from the first metal pad to the second metal pad outside of the package substrate in a second, vertical direction orthogonal to the first direction.In this way, the wire bond channel can support a more direct signal routing path between the first die and the first electronic device without the need to route such a signal routing path to bypass the KoZ within the package substrate.

[0006] In one example, the IC package also includes a second electronic device (e.g., a second die or a deep trench capacitor (DTC)) coupled to the package substrate and adjacent to the first die. The second electronic device is also coupled to metal interconnects within the metallization layer(s) of the package substrate to provide a signal routing path through the metal line(s) within the metallization layer(s) to and from the second electronic device. The second electronic device is disposed on the package substrate such that a signal routing KoZ for the second electronic device exists within the package substrate and, in whole or in part, within the direct signal routing path between the first die and the first electronic device within the package substrate. In this regard, the first metal pad of the wire bond channel is disposed adjacent to the first side of the second electronic device between the first die and the second electronic device in the first, horizontal direction of the package substrate. The second metal pad is disposed adjacent to the second side of the second electronic device and is coupled to the package substrate and the first electronic device. The wire bond of the wire bond channel extends from the first metal pad to the second metal pad outside of the package substrate and above the second, vertical direction of the second electronic device. In this way, the wire bond channel supports a more direct routing of signals between the first die and the first electronic device that does not require a more circuitous signal routing path that bypasses the signal routing KoZ within the package substrate.

[0007] In another example, the package substrate of the IC package includes other signal routing paths in the metallization layer of the package substrate that result in a signal routing KoZ within the package substrate between a first metal pad and a second metal pad of a wire bond channel in a first, horizontal direction (X-axis and Y-axis directions). The wire bond of the wire bond channel extends from the first metal pad to the second metal pad outside the package substrate and above the signal routing KoZ in a second, vertical direction. Thus, the wire bond channel can support a more direct routing of signals between the first die and the first electronic device without the need to provide a more circuitous signal routing path within the package substrate due to the need to route around the signal routing KoZ within the package substrate.

[0008] In this regard, in one exemplary aspect, an IC package is provided. The IC package includes a package substrate including a first surface extending in a first direction. The IC package also includes a first die coupled to the first surface of the package substrate. The IC package also includes a wire bond channel. The wire bond channel includes one or more first metal pads coupled to the first surface of the package substrate and coupled to the first die. The wire bond channel also includes one or more second metal pads coupled to the first surface of the package substrate. The wire bond channel also includes one or more wire bonds disposed outside the package substrate, where each of the one or more wire bonds couples a respective first metal pad of the one or more first metal pads to a respective second metal pad of the one or more second metal pads.

[0009] In another exemplary aspect, a method of manufacturing an integrated circuit (IC) package is provided. The method includes providing a package substrate that includes a first surface extending in a first direction. The method also includes coupling a first die to the first surface of the package substrate. The method also includes forming a wire bond channel, including forming one or more first metal pads coupled to the first surface of the package substrate and coupled to the first die, forming one or more second metal pads coupled to the first surface of the package substrate, coupling a first end of each of one or more wire bonds outside the package substrate to one or more first metal pads outside the package substrate, and coupling a second end of each of one or more wire bonds outside the package substrate to one or more second metal pads.

Brief Description of the Drawings

[0010]

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DETAILED DESCRIPTION

[0011] Next, some exemplary aspects of the present disclosure will be described with reference to the drawings. The term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other aspects.

[0012] Aspects disclosed herein include integrated circuit (IC) packages employing wire bond channels above a package substrate. Related manufacturing methods are also disclosed. The IC package includes a first semiconductor die (the “first die”) (e.g., a system-on-chip (SoC) die) coupled to a first, horizontally extending package substrate. The first die is coupled to metal interconnects within the metallization layer(s) of the package substrate for routing signals through metal lines within the metallization layer(s) to and from the first die. The IC package also includes a first electronic device coupled to the package substrate. The first electronic device can be placed on the package substrate such that a keep-out zone (KoZ) within the package substrate is wholly or partially within a direct signal routing path between the first electronic device and the first die within the package substrate. For example, the KoZ can be the result of another electronic device placed on the package substrate between the first die and the first electronic device. In another example, the KoZ can be the result of other signal routing paths within the package substrate. In an exemplary aspect, to provide a signal routing path between the first die and the first electronic device within the IC package, the IC package includes a wire bond channel coupled to the first die and the first electronic device. The wire bond channel includes a first metal pad coupled to the package substrate and the first die. The wire bond channel also includes a second metal pad coupled to the package substrate and the first electronic device. The wire bond channel includes wire bonds coupled to the respective first and second metal pads to provide signal routing pads and a signal routing path between the first and second metal pads for routing signals between the first die and the first electronic device. The wire bonds extend from the first metal pad to the second metal pad outside the package substrate in a second, vertical direction orthogonal to the first direction.Thus, the wire bond channel can support a more direct signal routing path between the first die and the first electronic device without the need to route such a signal routing path to bypass the KoZ within the package substrate.

[0013] Before describing an example of an IC package including a wire bond channel starting in FIG. 2A and including wire bonds extending above the package substrate to support a more direct signal routing path to the first die, first, an example of an IC package including a wire bond channel outside the package substrate is described with respect to FIG. 1 below.

[0014] FIG. 1 is a top view of an exemplary integrated circuit (IC) package 100 that includes a first semiconductor die (a “die”) 102 coupled to a package substrate 104. The first die 102 is coupled to a first, outer surface 106 of the package substrate 104. For example, the first die 102 can be a system-on-chip (SoC) die. The first die 102 is coupled to an outer metallization layer 108 of the package substrate 104. The outer metallization layer 108, and other metallization layers within the package substrate 104 that are disposed directly below the outer metallization layer 108 in a first, vertical direction (the Z-axis direction), include metal lines that are interconnected by metal interconnects to provide signal routing paths within the package substrate 104. The package substrate 104 includes metal lines that provide signal routing paths for communication to the first die 102. The IC package 100 also includes a second die 110 that is also coupled to the package substrate 104. For example, the second die 110 can include a security circuit, memory, or other circuitry that is desired to be provided in a die separate from the first die 102 within the IC package 100. The second die 110 is also coupled to the outer metallization layer 108 of the package substrate 104. The package substrate 104 also includes metal lines that provide signal routing paths for communication to the second die 110. For example, some of the metal lines within the package substrate 104 can be coupled to both the first die 102 and the second die 110 to support die-to-die (D2D) communication between the first die 102 and the second die 110.

[0015] Continuing to refer to FIG. 1, the second die 110 is installed on the package substrate 104 adjacent to the first die 102. The installation of the second die 110 on the package substrate 104 can result in a keep-out zone (KoZ) region 112 directly below the second die 110 in the first, vertical direction (Z-axis direction) within the outer metallization layer 108 and / or other metallization layers of the package substrate 104. Other metal lines for routing other signals from the first die 102 to other electronic devices within the IC package 100 may need to avoid the KoZ region 112 and be routed to bypass the KoZ region 112 in the first, horizontal directions (X-axis and Y-axis directions). This is shown in FIG. 1, where the metal lines 114 (shown as hidden lines) within the package substrate 104, within metallization layers such as the outer metallization layer 108, and coupled to the first die 102 are routed to bypass the KoZ region 112 within the package substrate 104. As a result, these metal lines 114 are longer than they would otherwise be if the metal lines 114 could be routed within the package substrate directly below the second die 110 (i.e., within the package substrate 104 within the vertical space (Z-axis) of the footprint of the second die 110), thereby increasing the impedance of the metal lines 114. This causes the signals carried through the metal lines 114 to experience additional delay. Also, as the metal lines 114 are bent to bypass the KoZ region 112, the metal lines 114 may have increased parasitic capacitance, which also results in signal delay. Further, the routing of the metal lines 114 that bypass the KoZ region 112 can also result in a decrease in the efficiency of signal routing and the use of routing space within the package substrate 104. This can lead to an increase in the area (in the first, horizontal directions of the X-axis and Y-axis) and / or the number of metallization layers (in the vertical height, Z-axis direction) required within the package substrate 104 to provide sufficient signal routing, increasing the cost.

[0016] Figures 2A and 2B are side and top views, respectively, of an exemplary IC package 200 that includes a wire bond channel 202 coupled to a first die 204 to provide a communication channel to the first die 204. The wire bond channel 202 includes wire bonds 206 that extend above a package substrate 208 to support a more direct signal routing path to the first die 204. For example, the wire bond channel 202 can be coupled to another component coupled to the package substrate 208 to provide a communication link between the first die 204 and such other component. In this example, the first die 204 is coupled to a first surface 210 of the package substrate 208. The package substrate 208 can be, by way of example, a core package substrate or a coreless package substrate. The package substrate 208 can be formed by a laminated metallization layer or by a build-up process in which metallization layers are formed on top of one another. The first surface 210 is a planar or substantially planar surface that extends horizontally in the X and Y axis directions in this example. For example, the first surface 210 can be the outer surface of an outer metallization layer 212(1) of the package substrate 208. As shown in FIG. 2A, the first die 204 can be coupled to a metal interconnect 214(1) within the outer metallization layer 212(1) to couple the first die 204 to the package substrate 208 to provide a signal routing path between the package substrate 208 and the first die 204. The outer metallization layer 212(1) can be formed, by way of example, as an embedded trace substrate (ETS) layer. The metal interconnect 214(1) forms or is coupled to metal lines 216(1) within the outer metallization layer 212(1) that provide a signal routing path within the package substrate 208. The metal lines 216(1) can be formed, by way of example, as redistributed lines (RDLs).The metal wire 216(1) within the outer metallization layer 212(1) can also be coupled to the metal wires 216(2) - 216(4) within other metallization layers 212(2) - 212(4) for providing signal routing paths within the package substrate 208 via metal interconnects 214(2) - 214(4) (e.g., vias, metal posts).

[0017] Continuing to refer to FIGS. 2A and 2B, a second electronic device 218 in the form of a second die 220 is also coupled to the first surface 210 of the package substrate 208. As an alternative, the second electronic device 218 could be a deep trench capacitor (DTC) including a capacitor formed in a trench embedded within a semiconductor substrate similar to the semiconductor substrate of the die. The second die 220 is disposed on the first surface 210 of the package substrate 208 adjacent to the first die 204. In this example, the first side 222 of the second die 220 is adjacent to the first die 204. The second die 220 is also coupled to a metal interconnect 214(1) within the outer metallization layer 212(1) to couple the second die 220 to the package substrate 208 to provide a signal routing path between the package substrate 208 and the second die 220. The metal interconnect 214(1) forms or is coupled to metal lines 216(5) within the outer metallization layer 212(1) below the second die 220 in a second, vertical (Z-axis) direction that provides a signal routing path for the second die 220 within the package substrate 208. The metal lines 216(5) within the outer metallization layer 212(1) can also be coupled to other metal lines 216(2)-216(4) within other metallization layers 212(2)-212(4) to provide signal routing paths within the package substrate 208 via metal interconnects 214(2) (e.g., vias, metal posts). In this example, due to the metal lines 216(5), 216(6) provided within the KoZ region 224 dedicated to routing signals to the second die 220, as shown in the side view of the IC package 200 in FIG. 2A, the second die 220 creates the KoZ region 224 within the package substrate 208. The KoZ region 224 is indicated by hidden lines in the top view of the IC package 200 in FIG. 2B. Therefore, the KoZ region 224 is a region defined by the metal lines 216(5), 216(6) within the metallization layers 212(1), 212(2) that are not used to route signals to other components independent of the second die 220 in this example. The KoZ region 224 extends horizontally in a first, X-axis and Y-axis direction along with the package substrate 208.The KoZ region 224 also extends vertically (in the Z-axis direction) within the package substrate 208. Therefore, the KoZ region 224 has a first, horizontal area footprint in the horizontal X-axis and Y-axis directions that extends vertically (in the Z-axis direction). Other signal routing paths that must cross within the area of the KoZ region 224 must be routed outside the KoZ region 224 so as not to interfere with the signal routing paths provided by the metal lines 216(5), 216(6).

[0018] Continuing to refer to FIGS. 2A and 2B, a wire bond channel 202 is provided to provide a signal routing path to the first die 204 that is desired to be routed through the KoZ region 224 of the package substrate 208, so as to avoid the need to route such a signal routing path around the KoZ region 224 (as shown in the example in FIG. 1). In this example, the wire bond channel 202 is formed by a first metal pad 226(1) and a second metal pad 226(2) formed on the package substrate 208. For example, the first metal pad 226(1) and the second metal pad 226(2) can be formed on the first surface 210 of the package substrate 208. The first and second metal pads 226(1), 226(2) can be bonding pads made of metal, such as lead material to which a wire can be bonded (e.g., soldered). The first metal pad 226(1) and the second metal pad 226(2) are coupled to respective metal lines 216(5) within the outer metallization layer 212(1) of the package substrate 208 to provide a signal routing path between the first and second metal pads 226(1), 226(2) and the package substrate 208. In this example, the first metal pad 226(1) is disposed adjacent to the first die 204 between the first die 204 and the first side 222 of the second die 220. The second metal pad 226(2) is disposed adjacent to the second die 220 adjacent to the second side 222(2) of the second die 220 opposite the first side 222(1) of the second die 220. The first metal pad 226(1) is coupled to the first die 204 by being coupled to a metal interconnect 214(1) of the first metal line 216(1) exposed from the first surface 210 of the package substrate 208. The second metal pad 226(2) is coupled to the metal interconnect 214(1) of the metal line 216(1) exposed from the first surface 210 of the package substrate 208.As shown in more detail in the top view of the IC package 200 in FIG. 2B and FIG. 2C, wire bonds 206 are provided on the first and second ends 228(1) and 228(2) of the first and second metal pads 226(1) and 226(2) respectively (e.g., bonded) to provide a conductive connection between the first metal pad 226(1) and the second metal pad 226(2). The wire bonds 206 are outside and external to the package substrate 208. The wire bonds 206 in this example extend above the first surface 210 of the package substrate 208 and above the second die 220 in a second, vertical direction (Z-axis direction) that is orthogonal to the first, horizontal directions (X-axis and Y-axis directions) of the first surface 210. In this example, each of the wire bonds 206 intersects a vertical plane P1 in the vertical direction (Z-axis direction) that also intersects the second die 220. The vertical plane P1 is orthogonal to the first, horizontal directions (X-axis and Y-axis directions) of the package substrate 208. However, it is not necessary for each wire bond 206 to intersect the vertical plane P1 that also intersects the second die 220.

[0019] Thus, the wire bonds 206 provide a signal routing path to the first die 204 that can extend above the second die 220 outside the package substrate 208 to provide a more direct signal routing path between the first die 204 and the second metal pad 226(2). The signal routing path may not be routed to bypass the KoZ region 224 in the package substrate 208 due to the presence of the second die 220 and its connectivity to the metal lines 216(5) and 216(6) in the package substrate 208. In this example, the wire bonds 206 are routed in a direction different from the direction of signal routing through the metal line 216(1) between the first die 204 and the first metal pad 226(1) between the first and second metal pads 226(1) and 226(2).

[0020] The KoZ region can exist within the package substrate even if it is not directly beneath another component, such as a die, coupled to the package substrate. To avoid the need to route signal routing paths around the KoZ region, wire bond channels can similarly be provided within such a package substrate. In this regard, FIG. 3 is a top view of another package substrate 300 that can be provided within an IC package including metal lines 306 within an outer metallization layer 302 that are routed to bypass a signal routing KoZ region 308 within the outer metallization layer 302. Other metal lines 309 forming the KoZ region 308 are disposed within the outer metallization layer 302. The package substrate 300 is designed such that another die or other electronic component is mounted on the package substrate 300 above the metal lines 306 in the vertical direction (in the Z-axis direction) (out of the plane of the paper in FIG. 3), so the metal lines 309 within the KoZ region 308 do not exist within the outer metallization layer 302. As shown in FIG. 3, the package substrate 300 includes other metal lines 310 coupled to metal interconnects 312 as part of a landing area 314 for a die to be coupled to the outer metallization layer 302. These other metal lines 310 are routed to bypass the KoZ region 308 to other metal interconnects 312 within the outer metallization layer 302.

[0021] FIG. 4A and FIG. 4B are side and top views, respectively, of an exemplary IC package 400 including wire bond channels 402 that provide a communication channel to a first die 404 without the need to route such a communication channel around a KoZ region within package substrate 408 of IC package 400. For example, it may be desirable to provide a signal routing path between a first die 404 and another component within IC package 400, where a KoZ region 424 is present within the desired signal routing path, but such a KoZ region is not due to metal lines present within package substrate 408 resulting from the placement of a second electronic component on package substrate 408 above KoZ region 424. The signal routing path between the first die 404 and such other components may include both a signal routing path that extends through package substrate 408 and a signal routing path that extends through wire bond channel 402 that extends outside of package substrate 408.

[0022] With respect to this point, as shown in FIGS. 4A and 4B, wire bond channel 402 includes a wire bond 406 that extends above package substrate 408 to support a signal routing path to first die 404. For example, wire bond channel 402 can be coupled to another component coupled to package substrate 408 to provide a communication link between first die 404 and such other component. In this example, first die 404 is coupled to a first surface 410 of package substrate 408. Package substrate 408 can be, by way of example, a core package substrate or a coreless package substrate. Package substrate 408 can be formed by a laminated metallization layer or by a build-up process in which metallization layers are formed on top of each other. First surface 410 is a planar or substantially planar surface that extends in a horizontal direction in the X-axis and Y-axis directions in this example. For example, first surface 410 can be an outer surface of outer metallization layer 412(1) of package substrate 408. Outer metallization layer 412(1) can be formed as an ETS layer, by way of example. As shown in FIG. 4A, first die 404 can be coupled to a metal interconnect 414(1) within outer metallization layer 412(1) to couple first die 404 to package substrate 408 to provide a signal routing path between package substrate 408 and first die 404. Metal interconnect 414(1) forms or is coupled to a first metal line 416(1) within outer metallization layer 412(1) that provides a signal routing path within package substrate 408. First metal line 416(1) can be formed as an RDL, by way of example. Metal lines 416(1) within first outer metallization layer 412(1) can also be coupled to other metal lines 416(2)-416(4) within other metallization layers 412(2)-412(4) that provide signal routing paths within package substrate 408 via metal interconnects 414(2)-414(4) (e.g., vias, metal posts).

[0023] Referring to FIG. 4B, the KoZ region 424 exists within the package substrate 408 due to the presence of metal lines dedicated to routing signals that are not routed on the first metal line 416(1). Therefore, the KoZ region 224 is a region defined by metal lines in the metallization layer(s) 412(1) to 412(4) that are used to route other signals than those routed through the first metal line 416(1). The KoZ region 424 extends horizontally in a first, X-axis and Y-axis direction together with the package substrate 408. The KoZ region 424 also extends vertically (in the Z-axis direction) within the package substrate 408. Therefore, the KoZ region 424 has a first, horizontal area footprint in the horizontal direction in the X-axis and Y-axis directions that extends vertically (in the Z-axis direction). Other signal routing paths that must cross within the area of the KoZ region 424 must be routed outside the KoZ region 424.

[0024] Continuing to refer to FIGS. 2A and 2B, a wire bond channel 402 is provided to provide a signal routing path to a first die 404 desired to be routed through a KoZ region 424 of a package substrate 408 to avoid the need to route such a signal routing path (as shown in the example in FIG. 3) around the KoZ region 424. In this example, the wire bond channel 402 is formed by a first metal pad 426(1) and a second metal pad 426(2) formed on the package substrate 408. For example, the first metal pad 426(1) and the second metal pad 426(2) may be formed on a first surface 410 of the package substrate 408. The first and second metal pads 426(1), 426(2) can be bonding pads made of metal, such as lead material to which a wire can be bonded (e.g., soldered). The first metal pad 426(1) is coupled to respective first metal lines 416(1) within an outer metallization layer 412(1) of the package substrate 408 to provide a signal routing path between the first metal pad 426(1) and the first die 404. In this example, the first metal pad 426(1) is disposed adjacent to a first side 427(1) of the first die 404. The second metal pad 426(2) is disposed adjacent to a second side 427(2) of the first die 404. The first metal pad 426(1) is coupled to the first die 404 by being coupled to a metal interconnect 414(1) coupled to the first metal line 416(1), and the metal interconnect 414(1) is exposed from the first surface 410 of the package substrate 408. As shown in FIG. 4B, a wire bond 406 is provided, which is a metal wire (e.g., bonded) coupled to the first and second metal pads 426(1), 426(2) on their respective first and second ends 428(1), 428(2) to provide an electrically conductive connection between the first metal pad 426(1) and the second pad 426(2). The wire bond 406 is external and outside of the package substrate 408.In this example, the wire bond 406 extends above the first surface 410 of the package substrate 408 in a second, vertical direction (Z-axis direction) that is orthogonal to the first, horizontal directions (X-axis and Y-axis directions) of the first surface 410. In this example, each of the wire bonds 406 intersects a vertical plane P2 in the vertical direction (Z-axis direction) that also intersects the KoZ region 424. The vertical plane P2 is orthogonal to the first, horizontal directions (X-axis and Y-axis directions) of the package substrate 408. However, each wire bond 406 is not required to intersect the vertical plane P2 that also intersects the KoZ region 424.

[0025] Thus, the wire bond 406 provides a signal routing path to the first die 404 that can extend to the second metal pad 426(2) above the KoZ region 424 outside the package substrate 408 in order to provide a signal routing path between the first die 404 and the second metal pad 426(2). The signal routing path provided by the wire bond 406 may not be routed to bypass the KoZ region 424 in the package substrate 408 due to the presence of the KoZ region 424 in the package substrate 408.

[0026] An IC package, including a first die coupled to a first, outer surface of a package substrate, and a wire bond channel including a wire bond extending from a first metal pad coupled to the first die to a second metal pad outside of the package substrate and vertically above a signal routing KoZ within the package substrate to support a more direct signal routing path between the first die and the second metal pad, including, but not limited to, the IC packages 200, 400 in FIGS. 2A-2C and FIGS. 4A-4B, a manufacturing process for manufacturing the IC package may be used. In this regard, FIG. 5 is a flowchart showing an exemplary manufacturing process 500 for manufacturing an IC package, including a first die coupled to a first, outer surface of a package substrate, and a wire bond channel including a wire bond extending from a first metal pad coupled to the first die to a second metal pad outside of the package substrate and vertically above a signal routing KoZ within the package substrate to support a more direct signal routing path between the first die and the second metal pad, including, but not limited to, the IC packages in FIGS. 2A-2A and FIGS. 4A-4B. The manufacturing process 500 in FIG. 5 is described with respect to the IC packages 200, 400 in FIGS. 2A-2C and FIGS. 4A and 4B, but it should be noted that the manufacturing process 500 is not limited to manufacturing IC packages such as the IC packages 200, 400 in FIGS. 2A-2C and FIGS. 4A and 4B.

[0027] In this regard, as shown in FIG. 5, the first step of the manufacturing process 500 in this example can be to prepare package substrates 208, 408 including first surfaces 210, 410 extending in a first direction (X-axis and Y-axis directions) (block 502 in FIG. 5). The next step in the manufacturing process 500 can be to couple first dies 204, 404 to the first surfaces 210, 410 of the package substrates 208, 408 (block 504 in FIG. 5). The next step in the manufacturing process 500 can be to form wire bond channels 202, 402 (block 506 in FIG. 5). Forming the wire bond channels 202, 402 can include forming one or more first metal pads 226(1), 426(1) coupled to the first surfaces 210, 410 of the package substrates 208, 408 and coupled to the first dies 204, 404 (block 508 in FIG. 5). Forming the wire bond channels 202, 402 can also include forming one or more second metal pads 226(2), 426(2) coupled to the first surfaces 210, 410 of the package substrates 208, 408 (block 510 in FIG. 5). Forming the wire bond channels 202, 402 can also include coupling first ends 228(1), 428(1) of each of one or more wire bonds 206, 406 outside the package substrates 208, 408 to one or more first metal pads 226(1), 426(1) outside the package substrates 208, 408 (block 512 in FIG. 5). Forming the wire bond channels 202, 402 can also include coupling second ends 228(2), 428(2) of each of one or more wire bonds 206, 406 outside the package substrates 208, 408 to one or more second metal pads 226(2), 426(2) (block 514 in FIG. 5).

[0028] An IC package, including a first die coupled to a first, outer surface of a package substrate, and a wire bond extending from a first metal pad coupled to the first die to a second metal pad outside of the package substrate and vertically above a signal routing KoZ within the package substrate to support a more direct signal routing path between the first die and the second metal pad, and further including a wire bond channel including the wire bond, and other manufacturing processes for manufacturing the IC package may be used, including, but not limited to, the IC packages in FIGS. 2A-2C and FIGS. 4A-4B. In this regard, FIGS. 6A-6C are a flowchart showing another exemplary manufacturing process 600 for manufacturing an IC package, including a first die coupled to a first, outer surface of a package substrate, and a wire bond extending from a first metal pad coupled to the first die to a second metal pad outside of the package substrate and vertically above a signal routing KoZ within the package substrate to support a more direct signal routing path between the first die and the second metal pad, and further including a wire bond channel including the wire bond, and including, but not limited to, the IC packages in FIGS. 2A-2C and FIGS. 4A-4B. FIGS. 7A-7F are exemplary manufacturing stages 700A-700F during the manufacture of the IC package according to the manufacturing process 600 of FIGS. 6A-6C. The manufacturing process 600 in FIGS. 6A-6C is described with reference to the IC package 200 in FIGS. 2A and 2C as shown in FIGS. 7A-7F, but it should be noted that it is not limited thereto. It should be noted that the manufacturing process 600 may be for forming a plurality of IC packages 200 that are, after being manufactured, subsequently singulated, in the same process.

[0029] Regarding this point, as shown in manufacturing step 700A of FIG. 7A, the first step in manufacturing the IC package 200 is to prepare the package substrate 208 (block 602 in FIG. 6A). As shown in manufacturing step 700B in FIG. 7B, the next step in manufacturing the IC package 200 is to place and bond the first die 204 and the second die 220 on the first surface 210 of the package substrate (block 604 in FIG. 6A). To physically and electrically bond the first die 204 to the package substrate 208, the die interconnect 230 of the first die 204 is bonded to the package substrate 208. To physically and electrically bond the second die 220 to the package substrate 208, the die interconnect 232 of the second die 220 is bonded to the package substrate 208.

[0030] As shown in manufacturing step 700C in FIG. 7C, the next step in manufacturing the IC package 200 is to form first and second metal pads 226(1), 226(2) on the first surface 210 of the package substrate 208 (block 606 in FIG. 6B). The first metal pad 226(1) is bonded to the first die 204 through the package substrate 208. Next, the wire bond 206 is bonded between the first metal pad 226(1) and the second metal pad 226(2) to form the wire bond channel 202. The wire bond 206 is formed above the first surface 210 of the package substrate 208, outside the package substrate 208, and above the second die 220. Next, as shown in manufacturing step 700D in FIG. 7D, the next step in manufacturing the IC package 200 is to insulate and protect the first and second dies 204, 220 and form an overmolding 234 from an overmolding material above the first and second dies 204, 220 and on the first surface 210 of the package substrate 208 to form the IC package 200 (block 608 in FIG. 6B).

[0031] As shown in manufacturing stage 700E in FIG. 7, the next step in manufacturing the IC package 200 is to turn the IC package 200 over to provide an external interface to the IC package 200 and form external interconnects 236 (e.g., solder bumps, ball grid array (BGA) interconnects) on and / or coupled to the second outer metallization layer 212(4) of the package substrate 208 (block 610 in FIG. 6C). Next, as shown in manufacturing stage 700F in FIG. 7F, the next step in manufacturing the IC package 200 is to turn the IC package 200 over again after the external interconnects 236 have been formed on the package substrate 208. The IC package 200, and its external interconnects 236, can be mounted, for example, within a printed circuit board (PCB). If multiple other IC packages 200 are formed simultaneously on the package substrate 208 together with the IC package 200, the IC packages 200 can be singulated.

[0032] An IC package, including a first die coupled to a first, outer surface of a package substrate, and a wire bond extending from a first metal pad coupled to the first die to a second metal pad outside of the package substrate and vertically above a signal routing KoZ within the package substrate to support a more direct signal routing path between the first die and the second metal pad, further including a wire bond channel including the wire bond, including, but not limited to, the examples in FIGS. 2A-2C, FIGS. 4A-4B, and FIGS. 7A-7F, and, but not limited to, any of the exemplary manufacturing processes in FIGS. 5-6C, and including an IC package according to any aspect disclosed herein, the IC package may be provided within or integrated into any processor-based device. Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, cellular phones, smartphones, session initiation protocol (SIP) phones, tablets, phablets, servers, computers, portable computers, mobile computing devices, laptop computers, wearable computing devices (e.g., smartwatches, health or fitness trackers, eyewear, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multicopters.

[0033] In this regard, FIG. 8 shows an example of a processor-based system 800 that can include circuitry provided within one or more IC packages 802(1) - 802(7). The IC packages 802(1) - 802(7) can include a first die coupled to a first, outer surface of a package substrate, and wire bonds that extend from a first metal pad coupled to the first die to a second metal pad outside of the package substrate and vertically above a signal routing KoZ within the package substrate to support a more direct signal routing path between the first die and the second metal pad. The wire bonds include a wire bond channel that includes wire bonds, and can include, but is not limited to, IC packages according to any of the exemplary manufacturing processes in FIGS. 2A - 2C, FIGS. 4A - 4B, and FIGS. 7A - 7F, and, without limitation, FIGS. 5 - 6C. In this embodiment, the processor-based system 800 can be formed as an IC 804 within the IC package 802 and as a system-on-chip (SoC) 806. The processor-based system 800 includes a central processing unit (CPU) 808 that includes one or more processors 810, sometimes also referred to as CPU cores or processor cores. The CPU 808 can have a cache memory 812 coupled to the CPU 808 to provide rapid access to temporarily stored data. The CPU 808 is coupled to a system bus 814 and can interconnect master and slave devices included within the processor-based system 800. As is well known, the CPU 808 communicates with these other devices by exchanging address information, control information, and data information via the system bus 814. For example, the CPU 808 can communicate a burst transaction request to a memory controller 816 as an example of a slave device. Although not shown in FIG. 8, it is possible to provide multiple system buses 814, with each system bus 814 forming a different fabric.

[0034] Other master devices and slave devices can be connected to the system bus 814. As shown in FIG. 8, these devices may include, by way of example, a memory system 820 including a memory controller 816 and a memory array(s) 818, one or more input devices 822, one or more output devices 824, one or more network interface devices 826, and one or more display controllers 828. Each of the memory system(s) 820, one or more input devices 822, one or more output devices 824, one or more network interface devices 826, and one or more display controllers 828 may be provided within the same or different IC packages 802(2)-802(7). The input device(s) 822 may include any type of input device including, but not limited to, input keys, switches, voice processors, etc. The output device(s) 824 may include any type of output device including, but not limited to, audio indicators, video indicators, other visual indicators, etc. The network interface device(s) 826 can be any device configured to enable data exchange with a network 830. The network 830 can be any type of network including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH (trademark) network, and the Internet. The network interface device(s) 826 can be configured to support any desired type of communication protocol.

[0035] The CPU 808 may also be configured to access one or more display controllers 828 via the system bus 814 to control information sent to one or more displays 832. The display controller(s) 828 send the information to be displayed to the display(s) 832 via one or more video processors 834, and the one or more video processors 834 process the information to be displayed into a format suitable for the display(s) 832. The display controller(s) 828 and the video processor(s) 834 can be included as an IC, for example, in the same or different IC packages 802(2), 802(3), and in the same or different IC packages 802 that include the CPU 808. The display(s) 832 can include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc.

[0036] FIG. 9 shows one or more ICs 902, any of the ICs 902 being an IC package 903, the IC package 903 including a first die coupled to a first, outer surface of a package substrate, and a wire bond extending from a first metal pad coupled to the first die to a second metal pad outside the package substrate and vertically above a signal routing KoZ within the package substrate to support a more direct signal routing path between the first die and the second metal pad, the wire bond further including a wire bond channel. The IC package 903 may include an IC package according to any of the exemplary manufacturing processes in FIGS. 2A-2C, FIGS. 4A-4B, and FIGS. 7A-7F, and, without limitation, FIGS. 5-6C, and includes a radio frequency (RF) component formed from one or more of the ICs 902 that may be included within the IC package 903. The wireless communication device 900 is shown. The wireless communication device 900 may include, by way of example, any of the devices mentioned above, or may be provided within any of those devices. As shown in FIG. 9, the wireless communication device 900 includes a transceiver 904 and a data processor 906. The data processor 906 may include memory for storing data and program code. The transceiver 904 includes a transmitter 908 and a receiver 910 that support two-way communication. In general, the wireless communication device 900 may include any number of transmitters 908 and / or receivers 910 for any number of communication systems and frequency bands. All or part of the transceiver 904 may be implemented in one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, and the like.

[0037] The transmitter 908 or the receiver 910 can be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal is frequency-converted between RF and baseband in multiple stages. For example, in the case of the receiver 910, in one stage, it is frequency-converted from RF to an intermediate frequency (IF), and then in another stage, it is frequency-converted from IF to baseband. In a direct conversion architecture, the signal is frequency-converted between RF and baseband in one stage. The superheterodyne architecture and the direct conversion architecture may use different circuit blocks and / or have different requirements. In the wireless communication device 900 of FIG. 9, the transmitter 908 and the receiver 910 are implemented using a direct conversion architecture.

[0038] In the transmission path, the data processor 906 processes the data to be transmitted and provides an I analog output signal and a Q analog output signal to the transmitter 908. In the exemplary wireless communication device 900, the data processor 906 includes digital-to-analog converters (DACs) 912(1), 912(2) for converting the digital signal generated by the data processor 906 into an I analog output signal and a Q analog output signal (e.g., an I output current and a Q output current) for further processing.

[0039] Within the transmitter 908, low-pass filters 914(1) and 914(2) filter the I analog output signal and the Q analog output signal, respectively, to remove unwanted signals generated by previous digital-to-analog conversions. Amplifiers (AMPs) 916(1) and 916(2) amplify the signals from low-pass filters 914(1) and 914(2), respectively, to provide an I baseband signal and a Q baseband signal. An upconverter 918 uses the I TX LO signal and the Q TX LO signal from the transmit (TX) local oscillator (LO) signal generator 922, via mixers 920(1) and 920(2), to upconvert the I baseband signal and the Q baseband signal to provide an upconverted signal 924. A filter 926 filters the upconverted signal 924 to remove unwanted signals caused by frequency upconversion and noise in the received frequency band. A power amplifier (PA) 928 amplifies the upconverted signal 924 from the filter 926 to obtain a desired output power level and provide a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 930 and transmitted via an antenna 932.

[0040] In the receiving path, antenna 932 receives the signal transmitted by the base station and provides a received RF signal, which is routed through duplexer or switch 930 and provided to low noise amplifier (LNA) 934. Duplexer or switch 930 is designed to operate using a specific RX-to-TX duplexer frequency separation such that the receive (RX) signal is separated from the TX signal. To obtain the desired RF input signal, the received RF signal is amplified by LNA 934 and filtered by filter 936. Downconversion mixers 938(1), 938(2) mix the output of filter 936 with the I RX LO signal and Q RX LO signal (i.e., LO_I and LO_Q) from RX LO signal generator 940 to generate an I baseband signal and a Q baseband signal. The I baseband signal and the Q baseband signal are amplified by AMPs 942(1), 942(2) and further filtered by low pass filters 944(1), 944(2) to obtain an I analog input signal and a Q analog input signal, and those analog input signals are provided to data processor 906. In this embodiment, data processor 906 includes analog-to-digital converters (ADCs) 946(1), 946(2) for converting the analog input signals into digital signals that will be further processed by data processor 906.

[0041] In the wireless communication device 900 of FIG. 9, the TX LO signal generator 922 generates the I TX LO signal and the Q TX LO signal used for frequency upconversion, while the RX LO signal generator 940 generates the I RX LO signal and the Q RX LO signal used for frequency downconversion. Each LO signal is a periodic signal having a specific fundamental frequency. The TX phase-locked loop (PLL) circuit 948 receives timing information from the data processor 906 and generates a control signal used to adjust the frequency and / or phase of the TX LO signal from the TX LO signal generator 922. Similarly, the RX PLL circuit 950 receives timing information from the data processor 906 and generates a control signal used to adjust the frequency and / or phase of the RX LO signal from the RX LO signal generator 940.

[0042] Those skilled in the art will further understand that the various exemplary logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein can be implemented as electronic hardware, as instructions stored in memory or in another computer-readable storage medium and executed by a processor or other processing device, or as a combination of both. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, various exemplary components, blocks, modules, circuits, and steps have been generally described above in terms of their functionality. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in various ways for each particular application, but such implementation decisions should not be construed as causing a departure from the scope of the present disclosure.

[0043] Various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein can be implemented or performed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor can be a microprocessor, but in the alternative, the processor can be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0044] Aspects disclosed herein can be implemented in hardware and stored within hardware, for example, in a Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Erasable Programmable ROM (EPROM), Electrically Programmable ROM (EEPROM), registers, hard disk, removable disk, CD-ROM, or any other form of computer-readable storage medium known in the art, and can also be implemented in instructions. An exemplary storage medium is coupled to the processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium can be integrated with the processor. The processor and the storage medium can reside within an ASIC. The ASIC can be present within a remote station. Alternatively, the processor and the storage medium can be present within a remote station, base station, or server as separate components.

[0045] Also, note that the operation steps described in any of the exemplary embodiments of this specification are also noted in that they are described to provide examples and considerations. The described operations can also be implemented in many different sequences other than the illustrated sequence. Furthermore, the operations described in a single operation step can actually be implemented in several different steps. Furthermore, one or more operation steps discussed in the exemplary embodiments can also be combined. It should be understood that many different modifications can be made to the operation steps shown in the flowchart diagrams, as will be readily apparent to those skilled in the art. Those skilled in the art will also understand that information and signals can be represented using any of a variety of technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0046] The above description of the present disclosure is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be readily apparent to those skilled in the art, and the general principles defined herein can also be applied to other variations. Therefore, the present disclosure is not intended to be limited to the embodiments and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0047] In the following numbered clauses, implementation examples will be described. 1. An integrated circuit (IC) package, a package substrate including a first surface extending in a first direction, a first die coupled to the first surface of the package substrate, a wire bond channel, one or more first metal pads coupled to the first surface of the package substrate and coupled to the first die, One or more second metal pads coupled to a first surface of the package substrate, and One or more wire bonds disposed outside the package substrate, wherein each of the one or more wire bonds couples a respective first metal pad of the one or more first metal pads to a respective second metal pad of the one or more second metal pads, the one or more wire bonds, A wire bond channel including An integrated circuit (IC) package comprising 2. The IC package according to clause 1, wherein one or more wire bonds extend above a first surface of the package substrate in a second direction orthogonal to the first direction. 3. A second electronic device coupled to a first surface of the package substrate, the second electronic device being adjacent to the first die, further comprising the second electronic device, The IC package according to clause 1 or 2, wherein at least a portion of at least one of the one or more wire bonds intersects a first vertical plane that intersects the second electronic device. 4. The IC package according to clause 3, wherein at least a portion of each of the one or more wire bonds intersects a vertical plane that intersects the second electronic device. 5. The second electronic device includes a first side adjacent to the first die, One or more first metal pads are disposed adjacent to the first die and between the first die and the first side of the second electronic device in a first direction, The IC package according to clause 3 or 4, wherein one or more second metal pads are disposed adjacent to a second side of the second electronic device. 6. The package substrate further includes an outer metallization layer adjacent to the first surface of the package substrate, The second electronic device is coupled to the outer metallization layer, The outer metallization layer is a keep-out zone (KoZ) region including one or more first metal lines, the KoZ region extending in a first direction and at least partially intersecting a first plane orthogonal to the first direction, the IC package according to any one of clauses 3 to 5 including the keep-out zone (KoZ) region. 7. The IC package according to any one of clauses 3 to 6, wherein the second electronic device includes a second die. 8. The IC package according to any one of clauses 3 to 7, wherein the second electronic device includes a deep trench capacitor. 9. The package substrate further includes an outer metallization layer adjacent to a first surface of the package substrate, the outer metallization layer including a keep-out zone (KoZ) region including one or more first metal lines extending in a first direction, The IC package according to clause 1, wherein at least a portion of at least one wire bond among one or more wire bonds intersects a first vertical plane orthogonal to the first direction and intersects at least a portion of the KoZ region. 10. The IC package according to clause 9, wherein the IC package does not include a second electronic device coupled to a first surface of the package substrate that intersects the first vertical plane. 11. The outer metallization layer includes one or more second metal lines coupled to one or more first metal pads, The IC package according to clause 9 or 10, wherein the first die is coupled to one or more second metal lines. 12. One or more second metal lines extend in a third direction toward one or more first metal pads, The IC package according to clause 11, wherein one or more wire bonds extend in a fourth direction different from the third direction from one or more first metal pads toward one or more second metal pads. 13. One or more first metal pads are exposed from a first surface of the package substrate, The IC package according to any one of clauses 1 to 12, wherein one or more second metal pads are exposed from a first surface of the package substrate. 14. The package substrate includes a metallization layer containing a plurality of metal wires, wherein one or more first metal pads are coupled to the plurality of metal wires, and a first die is coupled to the plurality of metal wires, the IC package according to any one of clauses 1 to 13. 15. A set-top box, an entertainment unit, a navigation device, a communication device, a fixed-position data unit, a mobile-position data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smartphone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, vehicle components, an avionics system, a drone, and a multicopter integrated into a device selected from the group consisting of, the IC package according to any one of clauses 1 to 14. 16. A method of manufacturing an integrated circuit (IC) package, comprising preparing a package substrate including a first surface extending in a first direction, coupling a first die to the first surface of the package substrate, forming a wire bond channel, forming one or more first metal pads coupled to the first surface of the package substrate and coupled to the first die, forming one or more second metal pads coupled to the first surface of the package substrate, coupling a first end of each of one or more wire bonds outside the package substrate to one or more first metal pads outside the package substrate, and Coupling each second end of one or more wire bonds outside the package substrate to one or more second metal pads Including, forming Method including 17. The method according to clause 16, further comprising extending one or more wire bonds above a first surface of the package substrate in a second direction orthogonal to the first direction. 18. Further comprising coupling a second electronic device to the first surface of the package substrate and adjacent to the first die Extending one or more wire bonds further includes extending one or more wire bonds so as to at least partially intersect a first vertical plane intersecting the second electronic device. The method according to clause 16 or 17 19. Coupling the second electronic device to the first surface of the package substrate further includes coupling the first side of the second electronic device adjacent to the first die Forming one or more first metal pads further includes forming one or more first metal pads adjacent to the first die in the first direction and between the first die and the first side of the second electronic device 16. The method according to clause 18, wherein forming one or more second metal pads further includes forming one or more second metal pads adjacent to a second side of the second electronic device 20. The package substrate further includes an outer metallization layer adjacent to the first surface of the package substrate, the outer metallization layer being a keep-out zone (KoZ) region including one or more first metal lines, the KoZ region extending in the first direction, including a keep-out zone (KoZ) region 20. Coupling the second electronic device to the first surface of the package substrate further includes coupling the second electronic device to the outer metallization layer such that the second electronic device at least partially intersects the first vertical plane. The method according to clause 18 or 19 21. The package substrate further includes an outer metallization layer adjacent to a first surface of the package substrate, the outer metallization layer including a keep-out zone (KoZ) region including one or more first metal lines extending in a first direction, The method according to clause 16 or 17, further comprising extending one or more wire bonds such that the one or more wire bonds at least partially intersect a first vertical plane that is orthogonal to the first direction and intersects at least a portion of the KoZ region. The method according to clause 21, further comprising not coupling a second electronic device to a first surface of the package substrate that intersects the first vertical plane. 23. Forming one or more first metal pads further includes coupling the one or more first metal pads to one or more second metal lines within the outer metallization layer, The method according to clause 21 or 22, coupling a first die to a first surface of the package substrate further includes coupling the first die to one or more second metal lines. 24. The method according to any one of clauses 21 to 23, further comprising not coupling a second electronic device to a first surface of the package substrate that intersects the first vertical plane.

Claims

1. An integrated circuit (IC) package, A package substrate including a first surface extending in a first direction, A first die bonded to the first surface of the package substrate, A second electronic device bonded to the first surface of the package substrate, wherein the second electronic device is adjacent to the first die, It is a wire-bonded channel, One or more first metal pads bonded to the first surface of the package substrate and bonded to the first die, One or more second metal pads bonded to the first surface of the package substrate, and One or more wire bonds disposed on the outside of the package substrate, wherein each of the one or more wire bonds connects the first metal pad of each of the one or more first metal pads to the second metal pad of each of the one or more second metal pads, and at least one portion of the one or more wire bonds intersects with a first vertical plane that intersects with the second electronic device, Includes a wire bond channel, An integrated circuit (IC) package that includes [the specified features].

2. The IC package according to claim 1, wherein one or more wire bonds extend above the first surface of the package substrate in a second direction perpendicular to the first direction.

3. The IC package according to claim 1, wherein at least a portion of each of the one or more wire bonds intersects with a vertical plane that intersects with the second electronic device.

4. The second electronic device includes a first side adjacent to the first die, The one or more first metal pads are arranged in the first direction adjacent to the first die and between the first die and the first side of the second electronic device. The IC package according to claim 1, wherein the one or more second metal pads are disposed adjacent to the second side of the second electronic device.

5. The package substrate further includes an outer metallized layer adjacent to the first surface of the package substrate, The second electronic device is bonded to the outer metallized layer, The IC package according to claim 1, wherein the outer metallized layer includes a keep-out zone (KoZ) region comprising one or more first metal wires, wherein the KoZ region extends in a first direction and at least partially intersects a first plane perpendicular to the first direction.

6. The IC package according to claim 1, wherein the second electronic device includes a second die.

7. The IC package according to claim 1, wherein the second electronic device includes a deep trench capacitor.

8. The package substrate further includes an outer metallized layer adjacent to the first surface of the package substrate, The outer metallized layer includes a keep-out zone (KoZ) region comprising one or more first metal wires extending in the first direction, The IC package according to claim 1, wherein at least a portion of at least one of the one or more wire bonds intersects a first vertical plane that is perpendicular to the first direction and intersects at least a portion of the KoZ region.

9. The outer metallized layer includes one or more second metal wires bonded to the one or more first metal pads, The IC package according to claim 8, wherein the first die is coupled to the one or more second metal wires.

10. The one or more second metal wires extend in a third direction toward the one or more first metal pads, The IC package according to claim 9, wherein the one or more wire bonds extend from the one or more first metal pads toward the one or more second metal pads in a fourth direction different from the third direction.

11. The one or more first metal pads are exposed from the first surface of the package substrate, The IC package according to claim 1, wherein the one or more second metal pads are exposed from the first surface of the package substrate.

12. The package substrate includes a metallized layer containing a plurality of metal wires, The one or more first metal pads are connected to the plurality of metal wires, The IC package according to claim 1, wherein the first die is coupled to the plurality of metal wires.

13. Set-top boxes, entertainment units, navigation devices, communication devices, fixed-location data units, mobile-location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablets, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices, desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multicopters The IC package according to claim 1, which is integrated with a device selected from the group consisting of the following.

14. A method for manufacturing an integrated circuit (IC) package, To prepare a package substrate including a first surface extending in a first direction, Bonding the first die to the first surface of the package substrate, The second electronic device is bonded to the first surface of the package substrate and adjacent to the first die. This involves forming a wire bond channel, To form one or more first metal pads bonded to the first surface of the package substrate and bonded to the first die, To form one or more second metal pads bonded to the first surface of the package substrate, The first end of each of the one or more wire bonds on the outside of the package substrate is bonded to the one or more first metal pads on the outside of the package substrate. Further extending one or more of the wire bonds so as to intersect at least partially with the first vertical plane that intersects with the second electronic device, and The second end of each of the one or more wire bonds on the outside of the package substrate is bonded to the one or more second metal pads. Including forming, Methods that include...

15. The method according to claim 14, further comprising extending one or more wire bonds above the first surface of the package substrate in a second direction perpendicular to the first direction.

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