Custom stacked capacitor layout design for high capacitance

Abstract

The chip includes a first capacitor, the first capacitor including first electrodes formed from a metal layer M0, the first electrodes being coupled to each other, the first capacitor also including second electrodes formed from a metal layer M0, the second electrodes being coupled to each other.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to and the benefit of non-provisional application Ser. No. 17 / 888,369, filed with the United States Patent Office on Aug. 15, 2023, the entire contents of which are incorporated herein as if fully set forth below and for all applicable purposes.

[0002] Aspects of the present disclosure relate generally to capacitors, and more particularly to the layout of capacitors on a chip. [Background technology]

[0003] Capacitors may be integrated on a chip (i.e., a die). Integrated capacitors may be used, for example, as decoupling capacitors on supply rails. Integrated capacitors may also be used, for example, in filters, switched-capacitor circuits, analog-to-digital converters, digital-to-analog converters, etc. Because the cost of a silicon die is directly proportional to the die area, it is desirable to fabricate high-density capacitors on the die to reduce the die area required for the capacitors. Summary of the Invention

[0004] SUMMARY OF THE INVENTION The following presents a simplified summary of one or more implementations to provide a basic understanding of such implementations. This Summary is not an extensive overview of all contemplated implementations, and is not intended to identify key or critical elements of all implementations or to delineate the scope of all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the Detailed Description presented later.

[0005] A first aspect relates to a chip including a first capacitor, the first capacitor including first electrodes formed from a metal layer M0, the first electrodes being coupled to each other, the first capacitor also including second electrodes formed from the metal layer M0, the second electrodes being coupled to each other.

[0006] A second aspect relates to a chip including a capacitor. The capacitor includes first electrodes coupled to each other and each extending in a first direction, a first one of the first electrodes and a second one of the first electrodes separated in the first direction by a first gap, and a third one of the first electrodes and a fourth one of the first electrodes separated in the first direction by a second gap. The capacitor also includes second electrodes coupled to each other and each extending in the first direction. [Brief explanation of the drawings]

[0007] [Figure 1] 1 illustrates a side view of an example of a chip including metal layers and vias, according to some aspects of the present disclosure. [Figure 2A] 1 illustrates a side view of an example of a fin field-effect transistor (FinFET) according to some embodiments of the present disclosure. [Figure 2B] 1 illustrates a perspective view of a FinFET according to some embodiments of the present disclosure. [Figure 3A] 1 illustrates a top view of a transistor according to some aspects of the present disclosure. [Figure 3B] 1 illustrates an example of a finger capacitor formed above a transistor in accordance with some aspects of the present disclosure. [Figure 3C] 3C illustrates an example of a metal routing coupling electrode of the finger capacitor in FIG. 3B according to some embodiments of the present disclosure. [Figure 4A] 1 illustrates a top view of a transistor according to some aspects of the present disclosure. [Figure 4B] 1 illustrates an example of a finger capacitor formed above a transistor in accordance with some aspects of the present disclosure. [Figure 4C] 4C illustrates an example of metal routing coupling electrodes of the finger capacitor in FIG. 4B according to some embodiments of the present disclosure. [Figure 4D] 4D illustrates an example of metal routing that combines the metal routing in FIG. 4C, according to some embodiments of the present disclosure. [Figure 5] 4C illustrates an example of a second finger capacitor formed above the finger capacitor in FIG. 4B according to some embodiments of the present disclosure. [Figure 6] 1 illustrates an example of a third finger capacitor formed on top of a second finger capacitor according to some aspects of the present disclosure. [Figure 7] 1 illustrates an example of a decoupling capacitor according to some aspects of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0008] The Detailed Description set forth below in connection with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The Detailed Description includes specific details intended to provide a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0009] FIG. 1 illustrates a side view of an example chip 100 (i.e., die) according to some embodiments. Chip 100 may include many devices (e.g., transistors) integrated on chip 100. In this regard, FIG. 1 illustrates one example of a transistor 110 integrated on chip 100. For simplicity, one transistor 110 is shown in FIG. 1, but it will be understood that chip 100 may include many transistors. Chip 100 may also include a stacked capacitor, as described further below.

[0010] In the example shown in FIG. 1 , transistor 110 includes gate 115, a first source / drain 120-1, and a second source / drain 120-2. As used herein, the term “source / drain” means a source or a drain. Gate 115 is formed over a channel between first source / drain 120-1 and second source / drain 120-2. Transistor 110 may also include a thin gate oxide (not shown) between the gate and the channel. Gate 115 may be a polysilicon gate, a metal gate, or another type of gate. In the example shown in FIG. 1 , transistor 110 is shown as a planar transistor. However, it should be understood that transistor 110 may be implemented with a fin field effect transistor (FinFET), an example of which is described below with reference to FIGS. 2A and 2B . Transistor 110 may be part of the front end of line (FEOL) of chip 100.

[0011] The chip 100 may also include a first source / drain contact 130-1 formed on the first source / drain 120-1 and a second source / drain contact 130-2 formed on the second source / drain 120-2. The source / drain contacts 130-1 and 130-2 may be formed from a source / drain contact layer (labeled "MD" in FIG. 1 ) using, for example, lithography and etching processes. While the source / drain contact layer is labeled "MD" in the example in FIG. 1 , it should be understood that the source / drain contact layer may also be labeled "CA" or another label. The source / drain contact layer may include one or more metals and / or one or more other conductive materials.

[0012] Chip 100 may also include a gate contact 135 formed on gate 115. Gate contact 135 may be formed from a gate contact layer (labeled "MP" in FIG. 1 ) using, for example, lithography and etching processes. While the gate contact layer is labeled "MP" in the example in FIG. 1 , it should be understood that the gate contact layer may also be labeled with another label. The gate contact layer may include one or more metals and / or one or more other conductive materials.

[0013] Chip 100 may also include a stack of metal layers 150. Metal layers 150 are patterned (e.g., using lithography and etching) to provide metal routing for transistors 110 and other devices (not shown) on chip 100. Metal routing may be used, for example, to interconnect devices on chip 100, to couple devices to power supplies, to couple devices to one or more input / output (I / O) pins, etc. Metal layers 150 may also be used to form stacked capacitors, as described further below. Metal layers 150 may also be referred to as metallization layers or other terms.

[0014] 1, the bottom metal layer in stack of metal layers 150 may be designated as metal layer M1 (also called metal 1), the metal layer immediately above metal layer M1 may be designated as metal layer M2 (also called metal 2), the metal layer immediately above metal layer M2 may be designated as metal layer M3 (also called metal 3), and so on. While three metal layers are shown in FIG. 1 for ease of illustration, it should be understood that chip 100 may include additional metal layers (e.g., five or more metal layers, including metal layer M4, metal layer M5, etc.).

[0015] Chip 100 also includes vias 160 that provide electrical coupling between metal layers 150. In this example, via V1 provides electrical coupling between metal layer M1 and metal layer M2, and via V2 provides electrical coupling between metal layer M2 and metal layer M3.

[0016] As explained above, metal layer 150 may also be used to form a stacked capacitor (not shown in FIG. 1 ). For example, metal layer 150 may be used to form a stacked capacitor including multiple finger capacitors, with each finger capacitor formed from a respective one of metal layers 150. In this example, the finger capacitors may be stacked vertically to provide a high capacitance density within a given die area. Finger capacitors may also be referred to as interdigitated capacitors or by other terms.

[0017] In advanced process nodes, a new metal layer (referred to as metal layer M0) is introduced between metal layer M1 and device structures (e.g., first source / drain 120-1, second source / drain 120-2, and gate 115) on chip 100. Metal layer M0 is used as an intermediate metal layer used to couple device structures on chip 100 to metal layer M1. In other words, device structures are coupled to metal layer M1 through metal layer M0 in advanced process nodes, while in earlier process nodes, device structures are coupled to metal layer M1 without metal layer M0. In the example shown in FIG. 1 , source / drain contacts 130-1 and 130-2 are coupled to metal layer M0 by via VD, and gate contact 135 is coupled to metal layer M0 by via VG. Metal layer M0 is coupled to metal layer M1 by via V0. As used herein, “coupled” means electrically coupled unless otherwise specified.

[0018] FIG. 2A shows a side view of an example of a transistor 110 implemented as a FinFET, and FIG. 2B shows a perspective view. In this example, the transistor 110 includes fins 210-1 through 210-4 that extend perpendicular to the gate 115 and source / drain contacts 130-1 and 130-2 (shown in FIG. 2B). While four fins 210-1 through 210-4 are shown in the example in FIG. 2B, it should be understood that the transistor 110 may include a different number of fins. Also, while the fins 210-1 through 210-4 are shown as having rectangular cross-sections, it should be understood that the fins may have other cross-sectional shapes (e.g., tapered cross-sections). Note that the metal layer 150, via 160, and gate contact 135 are not explicitly shown in FIG. 2B.

[0019] In this example, gate 115 is formed on first portions 215 of fins 210-1 through 210-4. Gate 115 may surround three or more sides of each fin (e.g., the top surface and two opposing sidewalls of each fin). In this example, transistor 110 may also include a thin dielectric layer (not shown) interposed between fins 210-1 through 210-4 and gate 115. As shown in FIG. 2A , gate contact 135 may be formed on gate 115, and via VG may electrically couple gate contact 135 to metal layer M0.

[0020] The portions of the fins 210-1 to 210-4 extending from the first side 222-1 of the gate 115 form the first source / drain 120-1, and the portions of the fins 210-1 to 210-4 extending from the second side 222-2 of the gate 115 form the second source / drain 120-2, the first side 222-1 and the second side 222-2 being opposite sides of the gate 115. In this example, a first source / drain contact 130-1 is formed on the second portion 220-1 of the fin 210-1 to 210-4 on the first side 222-1 of the gate 115, and a second source / drain contact 130-2 is formed on the third portion 220-2 of the fin 210-1 to 210-4 on the second side 222-2 of the gate 115. Each of the source / drain contacts 130-1 to 130-2 may be made of a conductive material (e.g., one or more metals). As shown in Figure 2A, vias VD may electrically couple the source / drain contacts 130-1 to 130-2 to the metal layer M0.

[0021] As explained above, metal layer M0 is used as an intermediate metal layer to couple device structures (e.g., first source / drain 120-1, second source / drain 120-2, and gate 115) to metal layer M1. To increase capacitance density (i.e., capacitance for a given die area), aspects of the present disclosure provide finger capacitors formed from metal layer M0. In stacked capacitors, aspects of the present disclosure increase the number of finger capacitors in the stacked capacitor by using additional metal layers (e.g., metal layer M0) to form additional finger capacitors within the stacked capacitor. These and other features of the present disclosure are further described below according to various aspects.

[0022] FIG. 3A illustrates an exemplary top view of transistor 110, according to some embodiments. As described further below, a finger capacitor (shown in FIG. 3B) is formed on transistor 110 from metal layer M0. Transistor 110 may include an active region 310 that includes first source / drain 120-1 and second source / drain 120-2 of transistor 110 (shown in FIGS. 1, 2A, and 2B). In an example where transistor 110 is implemented with a FinFET, active region 310 includes fins 210-1 through 210-4 that extend in a lateral direction 322 (shown in FIGS. 2A and 2B). As used herein, "lateral direction" refers to a direction running parallel to the substrate of chip 100. Active region 310 may also be referred to as an active diffusion region, an oxide diffusion region, or another term.

[0023] The transistor 110 also includes a first source / drain contact 130-1, a second source / drain contact 130-2, and a gate 115. The gate 115 is located between the first source / drain contact 130-1 and the second source / drain contact 130-2. As described further below, a finger capacitor (shown in FIG. 3B ) can electrically couple the first source / drain 120-1 and the second source / drain 120-2 to configure the transistor 110 as a metal-oxide-semiconductor (MOS) capacitor. However, it should be understood that the present disclosure is not limited to this example. In the example of FIG. 3A , the first source / drain contact 130-1, the second source / drain contact 130-2, and the gate 115 run parallel to each other and extend in a lateral direction 324 perpendicular to the lateral direction 322.

[0024] 3A also shows first vias 320-1 and 320-2 coupled to gate 115. In examples where gate contact 135 (shown in FIGS. 1 and 2A) is formed on gate 115, first vias 320-1 and 320-2 may be coupled to gate 115 through gate contact 135. In this example, first vias 320-1 and 320-2 may be disposed on gate contact 135. As described further below, first vias 320-1 through 320-2 are used to couple gate 115 to metal layer M0.

[0025] 3A further illustrates second vias 325-1 and 325-2 coupled to the first source / drain contact 130-1 and third vias 330-1 and 330-2 coupled to the second source / drain contact 130-2. For example, the second vias 325-1 and 325-2 may be disposed on the first source / drain contact 130-1, and the third vias 330-1 and 330-2 may be disposed on the second source / drain contact 130-2. As described further below, the second vias 325-1 and 325-2 are used to couple the first source / drain contact 130-1 to the metal layer M0, and the third vias 330-1 and 330-2 are used to couple the second source / drain contact 130-2 to the metal layer M0.

[0026] 3B illustrates an example of a finger capacitor 335 formed from metal layer M0 according to some embodiments. In this example, metal layer M0 is patterned (e.g., using lithography and etching processes to pattern metal layer M0 into individual electrodes) to form first electrodes 340-1, 340-2, and 340-3 and second electrodes 345-1 and 345-2. Electrodes 340-1, 340-2, 340-3, 345-1, and 345-2 are elongated and extend in a lateral direction 322. In the example illustrated in FIG. 3B , electrodes 340-1, 340-2, 340-3, 345-1, and 345-2 are spaced apart from one another in a lateral direction 324, which is perpendicular to the lateral direction 322. However, it should be understood that the present disclosure is not limited to this example. As explained further below, first electrodes 340-1, 340-2, and 340-3 are coupled to a first terminal of capacitor 335, and second electrodes 345-1 and 345-2 are coupled to a second terminal of capacitor 335. Electrodes may also be referred to as plates, fingers, or other terms.

[0027] 3B, the first electrodes 340-1, 340-2, and 340-3 are interleaved with the second electrodes 345-1 and 345-2. In other words, the electrode arrangement in the finger capacitor 335 alternates between the first electrodes 340-1, 340-2, and 340-3 and the second electrodes 345-1 and 345-2. The chip 100 may include a dielectric material between the electrodes 340-1, 340-2, 340-3, 345-1, and 345-2.

[0028] The first electrodes 340-1 and 340-3 are coupled to the gate 115 by first vias 320-1 and 320-2. In the example shown in FIG. 3B, each of the first vias 320-1 and 320-2 is coupled between the gate 115 and a respective one of the first electrodes 340-1 and 340-3. Note that the first vias 320-1 and 320-2 are shown with dotted lines in FIG. 3B to indicate that the first vias 320-1 and 320-2 are located below the first electrodes 340-1 and 340-3, respectively. Also, note that the first electrode 340-2 is not coupled to the gate 115 by a via in this example. As explained further below, the first electrode 340-2 is coupled to the first electrodes 340-1 and 340-3 through metal layer M1.

[0029] The second electrodes 345-1 and 345-2 are coupled to the first source / drain contact 130-1 by second vias 325-1 and 325-2. In the example shown in Figure 3B, each of the second vias 325-1 and 325-2 is coupled between the first source / drain contact 130-1 and a respective one of the second electrodes 345-1 and 345-2. Note that the second vias 325-1 and 325-2 are shown with dotted lines in Figure 3A to indicate that the second vias 325-1 and 325-2 are located below the second electrodes 345-1 and 345-2, respectively.

[0030] The second electrodes 345-1 and 345-2 are also coupled to the second source / drain contacts 130-2 by third vias 330-1 and 330-2. In the example shown in Figure 3B, each of the third vias 330-1 and 330-2 is coupled between the second source / drain contact 130-2 and a respective one of the second electrodes 345-1 and 345-2. Note that the third vias 330-1 and 330-2 are shown with dotted lines in Figure 3A to indicate that the third vias 330-1 and 330-2 are located below the second electrodes 345-1 and 345-2, respectively.

[0031] Thus, in this example, the first source / drain contact 130-1 and the second source / drain contact 130-2 are coupled to each other through the second electrodes 345-1 and 345-2. This couples the first source / drain 120-1 and the second source / drain 120-2 to each other, causing the transistor 110 to function as a MOS capacitor coupled in parallel with the finger capacitor 335. However, it should be understood that the present disclosure is not limited to this example. For example, the finger capacitor 335 may be formed on another type of capacitor in other implementations. In some implementations, there may not be a device below the finger capacitor 335.

[0032] Figure 3B also shows fourth vias 350-1, 350-2, and 350-3 coupled to the first electrodes 340-1, 340-2, and 340-3, respectively. For example, each of the fourth vias 350-1, 350-2, and 350-3 may be disposed over a respective one of the first electrodes 340-1, 340-2, and 340-3. Figure 3B also shows fifth vias 355-1 and 355-2 coupled to the second electrodes 345-1 and 345-2. For example, each of the fifth vias 355-1 and 355-2 may be disposed over a respective one of the second electrodes 345-1 and 345-2.

[0033] 3C shows first and second metal routings 360 and 365 formed from metal layer M1 (e.g., by lithography and etching processes to pattern metal layer M1 into metal routings 360 and 365). In the example shown in FIG. 3C, each of first and second metal routings 360 and 365 extends in lateral direction 324.

[0034] In this example, each of the fourth vias 350-1, 350-2, and 350-3 is coupled between a respective one of the first electrodes 340-1, 340-2, and 340-3 and the first metal routing 360. Thus, in this example, the first electrodes 340-1, 340-2, and 340-3 are coupled to one another through the first metal routing 360. In this example, the first metal routing 360 may serve as a first terminal of the finger capacitor 335 described above. The first metal routing 360 may also be used as an electrode of another finger capacitor formed from the metal layer M1.

[0035] In this example, each of the fifth vias 355-1 and 355-2 is coupled between a respective one of the second electrodes 345-1 and 345-2 and the second metal routing 365. Thus, in this example, the second electrodes 345-1 and 345-2 are coupled to each other through the second metal routing 365. In this example, the second metal routing 365 may serve as a second terminal of the finger capacitor 335 described above. The second metal routing 365 may also be used as an electrode of another finger capacitor formed from the metal layer M1.

[0036] Finger capacitor 335 may be used in a stack capacitor including a stack of multiple finger capacitors formed from multiple metal layers. The use of metal layer M0 to form finger capacitor 335 provides a stack capacitor with increased capacitance density (i.e., capacitance for a given die area) by providing an additional metal layer (i.e., metal layer M0) to form additional finger capacitors (i.e., finger capacitor 335) within the stack capacitor. In some aspects, other finger capacitors (not shown) within the stack capacitor may be stacked above finger capacitor 335, and the other finger capacitors may be formed from metal layers M1 through Mx, where x is an integer greater than 1.

[0037] It should be understood that the present disclosure is not limited to the embodiments shown in Figures 3A-3C. For example, it should be understood that finger capacitor 335 can be formed over multiple devices. For example, in some implementations, electrodes 340-1, 340-2, 340-3, 345-1, and 345-2 can extend in lateral direction 322 across multiple devices (e.g., transistors). It should also be understood that finger capacitor 335 can include additional electrodes in lateral direction 324 in addition to electrodes 340-1, 340-2, 340-3, 345-1, and 345-2 shown in Figures 3A-3C.

[0038] 3B and 3C, each of electrodes 340-1, 340-2, 340-3, 345-1, and 345-2 is shown as a continuous metal line extending in lateral direction 322. However, it should be understood that electrodes 340-1, 340-2, 340-3, 345-1, and 345-2 are not limited to the exemplary shapes shown in Figures 3B and 3C, and electrodes 340-1, 340-2, 340-3, 345-1, and 345-2 may have other shapes.

[0039] It should be understood that any reference to elements herein using designations such as “first,” “second,” etc., generally does not limit the quantity or order of those elements. Rather, these designations are used herein as a convenient way to distinguish between two or more elements or instances of an element. For example, the fourth vias 350-1, 350-2, and 350-3 and the fifth vias 355-1 and 355-2 may also be referred to as the first via and the second via, respectively (e.g., in an implementation in which transistor 110 is omitted). Furthermore, the first vias 320-1 and 320-2, the second vias 325-1 and 325-2, and the third vias 330-1 and 330-2 may also be referred to as the third via, the fourth via, and the fifth via, respectively.

[0040] 4A illustrates an exemplary top view of transistor 110 and second transistor 410, according to some embodiments. In the following description, transistor 110 is referred to as first transistor 110, and gate 115 is referred to as first gate.

[0041] The first transistor 110 has been described above in accordance with various embodiments. Therefore, the description of the first transistor 110 will not be repeated here for the sake of brevity. In some embodiments, the second transistor 410 may be a separate instance (i.e., a copy) of the transistor 110. However, it should be understood that this is not necessarily the case. As described further below, according to some embodiments, finger capacitors may be formed on the first transistor 110 and the second transistor 410. It should be understood that in some implementations, the first transistor 110 and the second transistor 410 may be merged into a multi-gate transistor (also referred to as a multi-finger transistor).

[0042] In this example, the second transistor 410 includes an active region 412. In examples where the second transistor 410 is implemented with a FinFET, the active region 412 includes a fin (e.g., similar to fins 210-1 through 210-4 shown in FIGS. 2A and 2B ) extending in the lateral direction 322. In examples where the first transistor 110 and the second transistor 410 are merged into a multi-gate transistor, the active region 412 may be merged with the active region 310 into a single active region.

[0043] The second transistor 410 also includes a third source / drain contact 418-1, a fourth source / drain contact 418-2, and a second gate 415. The third source / drain contact 418-1 may be formed on a first source / drain of the second transistor 410, and the fourth source / drain contact 418-2 may be formed on a second source / drain of the second transistor 410. The second gate 415 is located between the third source / drain contact 418-1 and the fourth source / drain contact 418-2. In the example of FIG. 4A , the third source / drain contact 418-1, the fourth source / drain contact 418-2, and the second gate 415 run parallel to each other and extend in the lateral direction 324.

[0044] 4A also shows fourth vias 420-1 and 420-2 coupled to the second gate 415. In examples where a second gate contact is formed on the second gate 415, the fourth vias 420-1 and 420-2 may be coupled to the second gate 415 through the gate contact. FIG. 4A also shows fifth vias 425-1 and 425-2 coupled to the third source / drain contact 418-1 and sixth vias 430-1 and 430-2 coupled to the fourth source / drain contact 418-2. For example, the fifth vias 425-1 and 425-2 may be disposed on the third source / drain contact 418-1, and the sixth vias 430-1 and 430-2 may be disposed on the fourth source / drain contact 418-2.

[0045] 4B shows an example of a finger capacitor 435 formed from metal layer M0, according to some embodiments. In this example, metal layer M0 is patterned (e.g., using lithography and etching processes to pattern metal layer M0 into individual electrodes) to form first electrodes 440-1 through 440-6 and second electrodes 445-1 and 445-2. Electrodes 440-1 through 440-6, 445-1, and 445-2 are elongated and extend in lateral direction 322. As described further below, first electrodes 440-1 through 440-6 are coupled to first terminals of capacitor 435, and second electrodes 445-1 and 445-2 are coupled to second terminals of capacitor 435.

[0046] In this example, first electrodes 440-1 and 440-2 are aligned in the lateral direction 324 and separated by a first gap 456 (i.e., a space) in the lateral direction 322, first electrodes 440-3 and 440-4 are aligned in the lateral direction 324 and separated by a second gap 457 in the lateral direction 322, and first electrodes 440-5 and 440-6 are aligned in the lateral direction 324 and separated by a third gap 458 in the lateral direction 322. In other words, gaps 456, 457, and 458 separate first electrodes 440-1, 440-3, and 440-5 from first electrodes 440-2, 440-4, and 440-6 in the lateral direction 322. Gaps 456, 457, and 458 may have approximately the same length in the lateral direction 322. As will be further explained below, gaps 456, 457, and 458 can be used to increase capacitance density while complying with design rules for chip layout. It should be understood that the gaps between two electrodes can be filled with a dielectric material (e.g., oxide). In other words, a dielectric material may be disposed between first electrodes 440-1 and 440-2, between first electrodes 440-3 and 440-4, and between first electrodes 440-5 and 440-6.

[0047] In the example in FIG. 4B , the second electrode 445-1 extends in the lateral direction 322, a first portion of the second electrode 445-1 is between the first electrodes 440-1 and 440-3, a second portion of the second electrode 445-1 is between the first electrodes 440-2 and 440-4, and a third portion 447-1 of the second electrode 445-1 is between the first and second portions of the second electrode 445-1.

[0048] The second electrode 445-2 extends in the lateral direction 322, with a first portion of the second electrode 445-2 being between the first electrodes 440-3 and 440-5, a second portion of the second electrode 445-2 being between the first electrodes 440-4 and 440-6, and a third portion 447-2 of the second electrode 445-2 being between the first and second portions of the second electrode 445-2.

[0049] In the example of Figure 4B, the first electrodes 440-1 and 440-5 are coupled to the first gate 115 by first vias 320-1 and 320-2, each of which is coupled between the first gate 115 and a respective one of the first electrodes 440-1 and 440-5. Note that in Figure 4B, vias under the metal layer M0 are shown with dotted lines. The second electrodes 445-1 and 445-2 are coupled to the first source / drain contact 130-1 by second vias 325-1 and 325-2, each of which is coupled between the first source / drain contact 130-1 and a respective one of the second electrodes 445-1 and 445-2. The second electrodes 445-1 and 445-2 are coupled to the second source / drain contacts 130-2 by third vias 330-1 and 330-2, each of the third vias 330-1 and 330-2 being coupled between the second source / drain contact 130-2 and a respective one of the second electrodes 445-1 and 445-2.

[0050] 4B , the first electrodes 440-2 and 440-6 are coupled to the second gate 415 by fourth vias 420-1 and 420-2, each of which is coupled between the second gate 415 and a respective one of the first electrodes 440-2 and 440-6. The second electrodes 445-1 and 445-2 are coupled to the third source / drain contact 418-1 by fifth vias 425-1 and 425-2, each of which is coupled between the third source / drain contact 418-1 and a respective one of the second electrodes 445-1 and 445-2. The second electrodes 445-1 and 445-2 are coupled to the fourth source / drain contact 418-2 by sixth vias 430-1 and 430-2, each of the sixth vias 430-1 and 430-2 being coupled between the fourth source / drain contact 418-2 and a respective one of the second electrodes 445-1 and 445-2.

[0051] 4B also shows an example of seventh vias 450-1 through 450-6, each coupled to a respective one of first electrodes 440-1 through 440-6. For example, each of seventh vias 450-1 through 450-6 may be disposed over a respective one of first electrodes 440-1 through 440-6.

[0052] 4B , seventh vias 450-1, 450-3, and 450-5 are aligned in the lateral direction 322, and seventh vias 450-2, 450-4, and 450-6 are aligned in the lateral direction 322. Each of seventh vias 450-1, 450-3, and 450-5 is disposed over a portion of a respective first electrode 440-1, 450-3, and 450-5 that extends beyond the boundary of the active area 310 of the first transistor 110. Also, each of seventh vias 450-2, 450-4, and 450-6 is disposed over a portion of a respective first electrode 440-2, 440-4, and 440-6 that extends beyond the boundary of the active area 412 of the second transistor 410. However, it should be understood that the present disclosure is not limited to this example.

[0053] 4B also shows an example of eighth vias 455-1 and 455-2, where eighth vias 455-1 and 455-2 are coupled to second electrode 445-1 and eighth vias 455-3 and 455-4 are coupled to second electrode 445-2. In this example, eighth vias 455-1 and 455-2 are disposed on third portion 447-1 of second electrode 445-1. Also, eighth vias 455-3 and 455-4 are disposed on third portion 447-2 of second electrode 445-2.

[0054] As shown in FIG. 4B, the spacing between the first electrodes 440-1 through 440-6 and the second electrodes 445-1 and 445-2 is s1 in the lateral direction 324. However, because gaps 456, 457, and 458 separate the first electrodes 440-1, 440-3, and 440-5 from the first electrodes 440-2, 440-4, and 440-6, the spacing between the eighth vias 455-1 through 455-4 and the first electrodes 440-1 through 440-6 may be s2, where s2 is greater than s1 (i.e., s2 > s1). Thus, the gaps 456, 457, and 458 increase the spacing (i.e., distance) between the eighth vias 455-1 through 455-4 and the first electrodes 440-1 through 440-6. Without gaps 456, 457, and 458, the spacing between eighth vias 455-1 through 455-4 and first electrodes 440-1 through 440-6 would be s1. The increased spacing between eighth vias 455-1 through 455-4 and first electrodes 440-1 through 440-6 allows first electrodes 440-1 through 440-6 and second electrodes 445-1 and 445-2 to be spaced closer together for higher capacitance density while still complying with design rules, as described further below.

[0055] In some aspects, the layout of the chip may be governed by design rules provided by a foundry or another entity. The design rules may be specific to the manufacturing process used to produce the chip 100. For example, the design rules may define a minimum spacing between vias on the second electrodes 445-1 and 445-2 (e.g., the eighth vias 455-1 through 455-4) and the first electrodes 440-1 through 440-6. For example, the minimum spacing may be defined to prevent the vias from unintentionally shorting the second electrodes 445-1 and 445-2 and the first electrodes 440-1 through 440-6 due to process variations. In this example, the design rules may allow the spacing between the eighth vias 455-1 through 455-4 and the first electrodes 440-1 through 440-6 to be greater than or equal to the minimum spacing, but not less than the minimum spacing. During chip layout, the placement of the eighth vias 455-1 through 455-4 relative to the first electrodes 440-1 through 440-6 may be checked for compliance with design rules in a process called design rule checking (DRC), which helps ensure that the chip layout complies with the design rules.

[0056] In this example, the spacing s2 between the eighth vias 455-1 to 455-4 and the first electrodes 440-1 to 440-6 may be approximately equal to the minimum spacing specified by the design rules to comply with the design rules. Because the spacing s1 between the first electrodes 440-1 to 440-6 and the second electrodes 445-1 and 445-2 is smaller than the spacing s2, the spacing s1 between the first electrodes 440-1 to 440-6 and the second electrodes 445-1 and 445-2 can be smaller than the minimum spacing specified by the design rules while still complying with the design rules. The smaller (i.e., closer) spacing between the first electrodes 440-1 to 440-6 and the second electrodes 445-1 and 445-2 increases the capacitance density of the finger capacitors 435. Thus, gaps 456, 457, and 458 allow first electrodes 440-1 through 440-6 and second electrodes 445-1 and 445-2 to be spaced closer together for higher capacitance density.

[0057] 4C shows a first metal routing 460, a second metal routing 462, a third metal routing 464, and a fourth metal routing 466 formed from metal layer M1 (e.g., by lithography and etching processes to pattern metal layer M1 into metal routings). In the example shown in FIG. 3C, each of metal routings 460, 462, 464, and 466 is elongated and extends in lateral direction 324. It should be understood that metal routings 460, 462, 464, and 466 can also serve as electrodes for capacitors formed above finger capacitors 435.

[0058] In this example, each of the seventh vias 450-1, 450-3, and 450-5 is coupled between a respective one of the first electrodes 440-1, 440-3, and 440-5 and the first metal routing 460. Thus, in this example, the first electrodes 440-1, 440-3, and 440-5 are coupled to one another through the first metal routing 460. Each of the seventh vias 450-2, 450-4, and 450-6 is coupled between a respective one of the first electrodes 440-2, 440-4, and 440-6 and the second metal routing 462. Thus, in this example, the first electrodes 440-2, 440-4, and 440-6 are coupled to one another through the second metal routing 462.

[0059] Each of the eighth vias 455-1 and 455-3 is coupled between a respective one of the second electrodes 445-1 and 445-2 and the third metal routing 464, and each of the eighth vias 455-2 and 455-4 is coupled between a respective one of the second electrodes 445-1 and 445-2 and the fourth metal routing 466. Thus, the second electrodes 445-1 and 445-2 are coupled to each other through the third metal routing 464 and the fourth metal routing 466. In this example, the third metal routing 464 and the fourth metal routing 466 extend across the gaps 456, 457, and 458 in the lateral direction 324.

[0060] 4D shows fifth and sixth metal routings 480 and 485 formed from metal layer M2 (e.g., by lithography and etching processes to pattern metal layer M2 into metal routings). In the example shown in FIG. 3C, each of metal routings 480 and 485 is elongated and extends in lateral direction 322. It should be understood that metal routings 480 and 485 may also serve as electrodes for capacitors formed above finger capacitors 435.

[0061] In this example, fifth metal routing 480 extends from first metal routing 460 to second metal routing 462. Fifth metal routing 480 is coupled to first metal routing 460 by via 472 coupled between first metal routing 460 and fifth metal routing 480. Fifth metal routing 480 is also coupled to second metal routing 462 by via 474 coupled between second metal routing 462 and fifth metal routing 480. Thus, in this example, first metal routing 460 is coupled to second metal routing 462 through fifth metal routing 480. Thus, first electrodes 440-1 to 440-6 are coupled to each other through first metal routing 460, second metal routing 462, and fifth metal routing 480. In this regard, first metal routing 460, second metal routing 462, and / or fifth metal routing 480 may be considered first terminals of finger capacitor 435 in this example. However, it should be understood that the present disclosure is not limited to this example.

[0062] The sixth metal routing 485 is coupled to the third metal routing 464 by a via 476 coupled between the third metal routing 464 and the sixth metal routing 485. The sixth metal routing 485 is also coupled to the fourth metal routing 466 by a via 478 coupled between the fourth metal routing 466 and the sixth metal routing 485. Thus, in this example, the third metal routing 464 is coupled to the fourth metal routing 466 through the sixth metal routing 485. Thus, the second electrodes 445-1 and 445-2 are coupled to each other through the third metal routing 464, the fourth metal routing 466, and the sixth metal routing 485. In this regard, the third metal routing 464, the fourth metal routing 466, and / or the sixth metal routing 485 may be considered second terminals of the finger capacitor 435. However, it should be understood that the present disclosure is not limited to this example.

[0063] 5 illustrates an example of a finger capacitor 535 formed from metal layer M1, according to some embodiments. Finger capacitor 535 may be formed above finger capacitor 435 and may be coupled in parallel with finger capacitor 435. Note that finger capacitor 435 is not shown in FIG. 5 for ease of illustration.

[0064] In this example, finger capacitor 535 includes third electrodes 510-1 through 510-8 and fourth electrodes 530-1 through 530-10. Electrodes 510-1 through 510-8 and 530-1 through 530-10 may be formed, for example, using a lithography process to pattern metal layer M1 into individual electrodes and an etching process. In the example shown in FIG. 5, electrodes 510-1 through 510-8 and 530-1 through 530-10 are elongated and extend in lateral direction 324. Third electrodes 510-1 through 510-8 may be interleaved with fourth electrodes 530-1 through 530-10.

[0065] In some embodiments, the third electrodes 510-1 and 510-8 may correspond to the first metal routing 460 and the second metal routing 462, respectively, as shown in Figure 5. Also, the fourth electrodes 530-5 and 530-6 may correspond to the third metal routing 464 and the fourth metal routing 466, as shown in Figure 5. However, it should be understood that the present disclosure is not limited to this example.

[0066] 5 shows ninth vias 520-1 through 520-8, each coupled between a respective one of third electrodes 510-1 through 510-8 and fifth metal routing 480. Thus, in this example, third electrodes 510-1 through 510-8 are coupled to one another through fifth metal routing 480. In this regard, fifth metal routing 480 may be considered a first terminal of finger capacitor 535.

[0067] 5 also shows tenth vias 540-1 through 540-10, each coupled between a respective one of fourth electrodes 510-1 through 530-10 and sixth metal routing 485. Thus, in this example, fourth electrodes 530-1 through 530-10 are coupled to one another through sixth metal routing 485. In this regard, sixth metal routing 485 may be considered a second terminal of finger capacitor 535.

[0068] 6 illustrates an example of a finger capacitor 635 formed from metal layer M2, according to some embodiments. In this example, metal layer M2 is patterned (e.g., using lithography and etching processes to pattern metal layer M2 into individual electrodes) to form fifth electrodes 640-1 through 640-6 and sixth electrodes 645-1 and 645-2. Electrodes 640-1 through 640-6, 645-1, and 645-2 are elongated and extend in the lateral direction 322.

[0069] In this example, fifth electrodes 640-1 and 640-2 are aligned in the lateral direction 324 and separated by a first gap 656 (i.e., spacing) in the lateral direction 322, fifth electrodes 640-3 and 640-4 are aligned in the lateral direction 324 and separated by a second gap 657 in the lateral direction 322, and fifth electrodes 640-5 and 640-6 are aligned in the lateral direction 324 and separated by a third gap 658 in the lateral direction 322. Gaps 656, 657, and 658 may have approximately the same length in the lateral direction 322.

[0070] In the example of FIG. 6, the sixth electrode 645-1 extends in the horizontal direction 322, a first portion of the sixth electrode 645-1 is between the fifth electrodes 640-1 and 640-3, a second portion of the sixth electrode 645-1 is between the fifth electrodes 640-2 and 640-4, and a third portion of the sixth electrode 645-1 is between the first and second portions.

[0071] The sixth electrode 645-2 extends in the lateral direction 322, with a first portion of the sixth electrode 645-2 being between the fifth electrodes 640-3 and 640-5, a second portion of the sixth electrode 645-2 being between the fifth electrodes 640-4 and 640-6, and a third portion of the sixth electrode 645-2 being between the first and second portions.

[0072] 6 , the fifth electrodes 640-1, 640-3, and 640-5 are coupled to the first metal routing 460 by vias 650-1, 650-3, and 650-5, respectively, with each of the vias 650-1, 650-3, and 650-5 coupled between a respective one of the fifth electrodes 640-1, 640-3, and 640-5 and the first metal routing 460. The fifth electrodes 640-2, 640-4, and 640-6 are coupled to the second metal routing 462 by vias 650-2, 650-4, and 650-6, respectively, with each of the vias 650-2, 650-4, and 650-6 coupled between a respective one of the fifth electrodes 640-2, 640-4, and 640-6 and the second metal routing 462. In this example, the first metal routing 460 and the second metal routing 462 are coupled through the fifth metal routing 480. Therefore, in this example, the fifth electrodes 640-1 to 640-6 are coupled to each other through the first metal routing 460, the second metal routing 462, and the fifth metal routing 480.

[0073] The sixth electrode 645-1 is coupled to the third metal routing 464 and the fourth metal routing 466 by vias 655-1 and 655-2, respectively, with the via 655-1 coupled between the sixth electrode 645-1 and the third metal routing 464 and the via 655-2 coupled between the sixth electrode 645-1 and the fourth metal routing 466. The sixth electrode 645-2 is coupled to the third metal routing 464 and the fourth metal routing 466 by vias 655-3 and 655-4, respectively, with the via 655-3 coupled between the sixth electrode 645-2 and the third metal routing 464 and the via 655-4 coupled between the sixth electrode 645-2 and the fourth metal routing 466. The third metal routing 464 and the fourth metal routing 466 are coupled through the sixth metal routing 485. Thus, in this example, the sixth electrodes 645-1 and 645-2 are coupled to each other through the third metal routing 464, the fourth metal routing 466, and the sixth metal routing 485.

[0074] As described above, a capacitor may be used as a decoupling capacitor. In this regard, FIG. 7 shows a circuit diagram of a decoupling capacitor 735 that may be implemented with any one of capacitors 335, 435, 535, and / or 635. One terminal 740 of capacitor 735 is coupled to a voltage supply rail 720 (also referred to as a power rail) that provides a supply voltage Vdd, and the other terminal 745 of capacitor 735 is coupled to a low rail 730 that is at a lower potential than supply rail 720. For example, low rail 730 may be grounded. When capacitor 735 is implemented with any one of capacitors 335, 435, 535, and / or 635, the terminal 740 coupled to supply rail 720 may correspond to the first terminal described above, and the terminal 745 coupled to ground rail 730 may correspond to the second terminal described above, or vice versa. However, it should be understood that the present disclosure is not limited to this example and that the capacitors described above, according to various aspects, may be used in other applications.

[0075] Example implementations are described in the following numbered clauses. 1. first electrodes formed from a metal layer M0, the first electrodes being coupled to one another; a second electrode formed from the metal layer M0, the second electrodes being coupled to each other; a first capacitor; Tips. 2. The chip of clause 1, wherein the first electrode and the second electrode are interleaved. 3. The chip of clause 1 or 2, wherein the first capacitor is above one or more transistors. 4. the first electrode is coupled to one or more gates of the one or more transistors; the second electrode is coupled to one or more source / drain contacts of the one or more transistors; Tips as described in clause 3. 5. a first metal routing formed from a metal layer M1, wherein the first electrodes are coupled to each other through the first metal routing; a second metal routing formed from the metal layer M1, wherein the second electrodes are coupled to each other through the second metal routing; Chips as set out in any one of clauses 1 to 4. 6. The chip of any one of clauses 1 to 5, wherein each of the first electrodes and each of the second electrodes comprises a respective metal wire. 7. The chip of any one of clauses 1 to 6, further comprising a second capacitor formed from metal layer M1, the second capacitor being coupled in parallel with the first capacitor. 8. each of the first electrodes and each of the second electrodes extends in a first direction; a first one of the first electrodes and a second one of the first electrodes are separated in a first direction by a first gap; a third one of the first electrodes and a fourth one of the first electrodes are separated in the first direction by a second gap; Chips as set out in any one of clauses 1 to 7. 9. a first portion of one of the second electrodes is between a first one of the first electrodes and a third one of the first electrodes; a second portion of one of the second electrodes is between a second one of the first electrodes and a fourth one of the first electrodes; Tips as described in clause 8. 10. The chip of clause 9, wherein each of the first electrodes and each of the second electrodes comprises a respective metal wire. 11. The chip described in clause 9 or 10, further comprising one or more vias disposed on a third portion of one of the second electrodes, the third portion of one of the second electrodes being between a first portion of the one of the second electrodes and a second portion of the one of the second electrodes. 12. a first metal routing formed from a metal layer M1, the first metal routing coupled to a first one of the first electrodes and a third one of the first electrodes; a second metal routing formed from metal layer M1, the second metal routing coupled to a second one of the first electrodes and a fourth one of the first electrodes; a third metal routing formed from metal layer M1, wherein one or more vias are coupled between one of the second electrodes and the third metal routing. Tips as described in clause 11. 13. The chip of clause 12, wherein the first metal routing, the second metal routing, and the third metal routing each extend in a second direction, the second direction being perpendicular to the first direction. 14. The chip of clause 12 or 13, further comprising a fourth metal routing formed from metal layer M2, the fourth metal routing being coupled to the first metal routing and the second metal routing. 15. the first metal routing and the third metal routing are located on opposite sides of the first gate; the third metal routing and the second metal routing are disposed on opposite sides of the second gate; A tip as set out in any one of clauses 12 to 14. 16. The chip of clause 15, wherein each of the first metal routing, the second metal routing, the third metal routing, the first gate, and the second gate extends in a second direction, the second direction being perpendicular to the first direction. 17. first electrodes coupled to one another and each extending in a first direction, wherein a first one of the first electrodes and a second one of the first electrodes are separated in the first direction by a first gap, and a third one of the first electrodes and a fourth one of the first electrodes are separated in the first direction by a second gap; and second electrodes connected to each other and each extending in the first direction. Tips. 18. a first portion of one of the second electrodes is between a first one of the first electrodes and a third one of the first electrodes; a second portion of one of the second electrodes is between a second one of the first electrodes and a fourth one of the first electrodes; Tips as described in clause 17. 19. The chip of clause 18, wherein each of the first electrodes and each of the second electrodes comprises a respective metal wire. 20. The chip of clause 18 or 19, further comprising one or more vias disposed on a third portion of one of the second electrodes, the third portion of one of the second electrodes being between a first portion of the one of the second electrodes and a second portion of the one of the second electrodes. twenty one. a first metal routing coupled to a first one of the first electrodes and a third one of the first electrodes; a second metal routing coupled to a second one of the first electrodes and a fourth one of the first electrodes; a third metal, wherein one or more vias are coupled between one of the second electrodes and the third metal routing. Tips as described in clause 20. 22. The chip of clause 21, wherein the first metal routing, the second metal routing, and the third metal routing each extend in a second direction, the second direction being perpendicular to the first direction. 23. The chip of clause 21 or 22, further comprising a fourth metal routing, the fourth metal routing being coupled to the first metal routing and the second metal routing. twenty four. the first metal routing and the third metal routing are located on opposite sides of the first gate; the third metal routing and the second metal routing are disposed on opposite sides of the second gate; A tip as set out in any one of clauses 21 to 23. 25. The chip of clause 24, wherein each of the first metal routing, the second metal routing, the third metal routing, the first gate, and the second gate extends in a second direction, the second direction being perpendicular to the first direction.

[0076] Within the scope of this disclosure, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the described feature, advantage, or mode of operation. The term "coupled" is used herein to refer to a direct or indirect electrical coupling between two structures.

[0077] The above description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the embodiments described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. [Explanation of symbols]

[0078] 100 chips 110 first transistor 115 First Gate 120-1, 2 Drain 130-1, 2 drain contact 135 Gate Contact 150 metal layer 160 Beer 210-1~4 fins 215 First Part 220-1, 2 Second part 222-1, 2 First aspect 310 Active area 320-1, 2 First via 325-1, 2 Second via 330-1, 2 Third via 335 Finger Capacitor 340-1~3 First electrode 345-1, 2 Second electrode 350-1~3 4th via 355-1, 2 5th Via 360 First Metal Routing 365 Second Metal Routing 410 second transistor 412 Active region 415 Second Gate 418-1, 2 Drain contact 420-1, 2 Fourth Via 425-1, 2 5th Via 430-1, 2 6th Via 435 Finger Capacitor 440-1~6 First electrode 445-1, 2 Second electrode 447-1, 2 Third Part 450-1~6 7th via 455-1~4 8th Via 456 First Gap 457 Second Gap 458 The Third Gap 460 First Metal Routing 462 Second Metal Routing 464 Third Metal Routing 466 Fourth Metal Routing 472 Beer 474 Beer 476 Beer 478 Beer 480 Fifth Metal Routing 485 Sixth Metal Routing 510-1~8 Fourth electrode 520-1~8 9th Via 530-1~10 Fourth electrode 535 Finger Capacitor 540-1~10 10th via 635 Finger Capacitor 640-1~6 5th electrode 645-1, 2 6th electrode 650-1~6 via 655-1~4 via 656 First Gap 657 Second Gap 658 The Third Gap 720 voltage supply rail 730 Ground rail, low rail 735 Decoupling Capacitor

Claims

1. It's a tip, A metal routing for a device structure on the chip, wherein the bottom metal layer is metal layer M1, and metal layer M0 is used as an intermediate metal layer to connect the device structure on the chip to metal layer M1, and The first capacitor, A first electrode formed from a metal layer M0, the first electrode and a third electrode bonded to each other, A second electrode formed from the metal layer M0, the second electrode being bonded to each other, A first capacitor and It is equipped with, Each of the first electrodes and each of the second electrodes extends in the first direction, The first electrode of the first electrode and the second electrode of the first electrode are separated by a first gap in the first direction. The third electrode of the first electrode and the fourth electrode of the first electrode are separated in the first direction by a second gap, and the first gap and the second gap are filled with a dielectric material such that the dielectric material is between each of the first electrodes and each of the second electrodes. One first portion of the second electrode is located between the first electrode of the first electrode and the third electrode of the first electrode. One second portion of the second electrode is located between the second electrode of the first electrode and the fourth electrode of the first electrode. One third portion of the second electrode, comprising one or more vias disposed on the one third portion of the second electrode, which is located between the one first portion of the second electrode and the one second portion of the second electrode, A first metal routing formed from a metal layer M1, which is coupled to the first electrode of the first electrode and the third electrode of the first electrode, A second metal routing formed from the metal layer M1, which is coupled to the second electrode of the first electrode and the fourth electrode of the first electrode, The device further comprises a third metal routing formed from the metal layer M1, wherein one or more vias are coupled between one of the second electrodes and the third metal routing. The first metal routing and the third metal routing are located on opposite sides of the first gate. A chip in which the third metal routing and the second metal routing are located on opposite sides of the second gate.

2. The chip according to claim 1, wherein each of the first electrodes and each of the second electrodes includes a metal wire.

3. The chip according to claim 1, wherein each of the first metal routing, the second metal routing, and the third metal routing extends in a second direction, the second direction being perpendicular to the first direction.

4. The chip according to claim 1, further comprising a fourth metal routing formed from a metal layer M2, the fourth metal routing being coupled to the first metal routing and the second metal routing.

5. The chip according to claim 1, wherein each of the first metal routing, the second metal routing, the third metal routing, the first gate, and the second gate extends in a second direction, the second direction being perpendicular to the first direction.

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