Semiconductor equipment

Abstract

Miniaturized transistors require thinning of the gate insulating layer, but tunnel electricity If the gate insulating layer is a single layer of silicon oxide film, the gate leakage current will increase. Physical limitations are being reached in thinning the gate insulating layer. [Solution] By using a high-k film with a relative permittivity of 10 or more in the gate insulating layer, Reduces the gate leakage current of the modified transistor. The second insulating layer in contact with the oxide semiconductor layer By using a high-k film as the first insulating layer, which has a higher dielectric constant than the marginal layer, acid The gate insulating layer can be made thinner than when calculated using a silicon dioxide film.

Description

[Technical Field]

[0001] A semiconductor having a transistor made of an oxide semiconductor, and an integrated circuit composed of the transistor. The present invention relates to an electrical device and a method for manufacturing the same. For example, an electrical device that incorporates a semiconductor integrated circuit as a component. Regarding sub-devices.

[0002] In this specification, a semiconductor device refers to a device that can function by utilizing semiconductor properties. This refers to all things, including display devices, electro-optical devices, semiconductor circuits, electronic components, and electronic equipment. It is a conductive device. [Background technology]

[0003] In recent years, the development of semiconductor devices has progressed, and silicon wafers and glass substrates are used depending on the application. Various types of semiconductor devices are being manufactured.

[0004] For example, in liquid crystal displays, transistors and wiring are formed on a glass substrate. I, CPU, and memory are semiconductor integrated circuits (at least tra An assembly of semiconductor elements having a converter and memory, and having electrodes that serve as connection terminals. ru.

[0005] The above semiconductor device can use a transistor as part of its components. While silicon-based semiconductor materials are well known as applicable semiconductor thin films, oxide semiconductor materials are also... It's attracting attention.

[0006] As materials for oxide semiconductors, those containing zinc oxide are known. Transistors formed from zinc semiconductors have been disclosed (Patent Documents 1 to 3). [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2006-165527 [Patent Document 2] Japanese Patent Publication No. 2006-165528 [Patent Document 3] Japanese Patent Publication No. 2006-165529 [Overview of the project] [Problems that the invention aims to solve]

[0008] For semiconductor devices, not only is the power consumption during operation important, but the power consumption during standby is also a crucial factor. Portable semiconductor devices, in particular, rely on batteries for power, and therefore operate with limited power. The available time is limited. In addition, automotive semiconductor devices have a large leakage current when in standby mode. This could lead to a decrease in battery life. For example, in electric vehicles, The leakage current in the semiconductor device causes the driving distance per unit charge to be shortened.

[0009] To reduce power consumption, it is necessary to consider not only power consumption during operation but also leakage current during standby. Reducing it is effective. The leakage current of individual transistors is not large, however An LSI has millions of transistors, and when you add up their leakage currents, It will never be small. Such leakage currents contribute to the power consumption of semiconductor devices in standby mode. This is the cause of the increase. There are various factors that cause leakage current, but during standby, If the drive current can be reduced, the power consumed in the drive circuit and other components can be reduced. This allows for power saving in semiconductor devices. It reduces the leakage current of semiconductor devices during standby. One of the challenges is to reduce it.

[0010] In addition, since miniaturization of semiconductor devices is required, it is inevitable that miniaturization is also required for transistors, which are components of semiconductor devices. Miniaturized transistors require thinning of the gate insulating layer. However, when the thickness of the gate insulating layer becomes 1 nm or less, the tunnel current increases, and also the probability of pinholes occurring in the gate insulating layer increases rapidly. Due to these factors, the gate leakage current increases. Therefore, when the gate insulating layer is a single layer of silicon oxide film, a physical limit is arising in thinning the gate insulating layer. Making it a problem to attempt to thin the gate insulating layer. And making it a problem to attempt to miniaturize transistors and further miniaturize the entire semiconductor device.

Means for Solving the Problem

[0011]

[0012]

[0013]

[0012]

[0013]

[0013] m (m>0) A membrane can be used. Here, M is selected from Ga, Al, Mn, and Co. or indicates multiple metallic elements. For example, M could be Ga, Ga and Al, Ga and Mn, or Examples include Ga and Co.

[0014] By using a high-k film with a relative permittivity of 10 or higher in the gate insulating layer, miniaturized transistors can be used. This makes it possible to reduce the gate leakage current of the zista, thereby achieving power savings in semiconductor devices. Examples of high-k films with high dielectric constants include hafnium oxide (HfO2, etc.) and hafnium silicate. HfSi x O y ;However, x>0, y>0)), hafnium oxynitrite silicate Id (HfSiON), Hafnium Aluminate (HfAl x O y ;However, x>0, y> 0) and others can be used. In addition, zirconium oxide can be used as another high-k film. (ZrO2, etc.), tantalum oxide (Ta2O5, etc.), aluminum zirconium oxide (Zr Al x O y ;However, other examples such as x>0, y>0)) can also be given, and among these materials A layer consisting of one of the above-mentioned layers and an insulating film containing hafnium is used as the gate insulating layer. It is also possible that hafnium-containing insulating films can be used when wet etching is performed. Because it is hardly etched, it protects the electrodes and substrate located below it. It can also function as a stopper membrane.

[0015] Furthermore, by using a high-k film with a relative permittivity of 10 or more for the gate insulating layer, the silicon oxide film The same effect as a gate insulating layer with a thickness of 0.8 nm or less formed independently can be achieved with a thickness of 2 nm or more ( In terms of structure, it can be obtained with a gate insulating layer with a thickness of 2 nm to 10 nm. Alternatively, The insulating layer has a high-k film with a relative dielectric constant of 10 or more (specifically, a thickness of 2 nm to 10 nm). (Below) By using this method, the gate insulating film thickness is greater than that of the gate insulating layer when calculated using a silicon oxide film. It can be formed into a film. Furthermore, the gate insulating layer is free of pinholes and has a uniform dielectric strength. It is possible to implement Rangista.

[0016] One aspect of the present invention disclosed herein is a first insulating device provided in contact with a gate electrode. A layer, a second insulating layer made of a metal oxide provided in contact with the first insulating layer, and a second An oxide semiconductor layer provided in contact with the insulating layer, and a layer provided in contact with the oxide semiconductor layer The oxide semiconductor layer has a third insulating layer, and between the second insulating layer and the third insulating layer A semiconductor device characterized by the arrangement of the first insulating layer and the higher relative permittivity of the second insulating layer. That is the case.

[0017] The above configuration solves at least one of the above problems.

[0018] For example, as a first insulating layer having a higher dielectric constant than the second insulating layer in contact with the oxide semiconductor layer, By using an insulating film containing hafnium (specifically, with a thickness of 2 nm to 10 nm), acid The gate insulating film can be made thinner than the gate insulating layer when calculated using a silicon dioxide film, and the transient This enables miniaturization of the device.

[0019] In the above configuration, the second insulating layer, the third insulating layer, and the oxide semiconductor layer are made by sputtering. It is preferable to manufacture it as follows. The second insulating layer and the third insulating layer are made of an oxide semiconductor layer with hydrogen and hydroxyl To minimize the inclusion of substrates and moisture, residual moisture in the deposition chamber is removed while water It is preferable to perform film deposition by introducing sputtering gas from which elements and moisture have been removed.

[0020] One of the present inventions is a method for fabricating bottom-gate transistors, and the invention relates to this fabrication method. The configuration involves forming a gate electrode on a substrate having an insulating surface, and a first insulating layer covering the gate electrode. The edge layer is formed by sputtering, and the second insulating layer is formed on the first insulating layer by sputtering. Then, an oxide semiconductor layer is formed on the second insulating layer, and an atmosphere containing nitrogen, oxygen, or a noble gas is used. The following heating treatment is performed at temperatures above 400°C, below the strain point of the substrate, to remove the water contained in the oxide semiconductor layer. The amount of material used is reduced, and a third insulating layer is formed on the oxide semiconductor layer by sputtering, and the first insulating layer This is a method for fabricating a semiconductor device in which the marginal layer has a relative permittivity higher than that of the second insulating layer.

[0021] Furthermore, since the second and third insulating layers are layers that are in contact with the oxide semiconductor layer, silicon oxide It is preferable to use an oxide insulating layer such as a crystalline oxide. In particular, the layer formed after the formation of the oxide semiconductor layer The insulating layer 3 is subjected to a heat treatment above 400°C but below the strain point of the substrate, thereby removing impurities in the oxide semiconductor layer. The oxide semiconductor, which is composed of elements that were simultaneously reduced by the process of removing pure substances (such as water), It can also supply oxygen, one of the materials that make up oxide semiconductors. By supplying a certain amount of oxygen, the oxide semiconductor layer is purified and electrically converted to type I (intrinsic). It can be transformed.

[0022] Furthermore, the first insulating layer uses a high-k film with a relative permittivity of 10 or higher, such as hafnium. Using an insulating film containing [the specified element] allows for wet etching during patterning of the oxide semiconductor layer. Furthermore, even if the thickness of the second insulating layer is thinly removed, it is hardly etched, It functions as an etching stopper film that protects the gate electrode and substrate located below. It is also possible.

[0023] Furthermore, it has two gate electrodes positioned above and below the channel region, separated by gate insulating layers. The dual-gate transistor structure is also one of the present inventions, and its configuration is a first gate A first insulating layer provided so as to be in contact with the electrode, and a second insulating layer provided so as to be in contact with the first insulating layer A second insulating layer, an oxide semiconductor layer provided in contact with the second insulating layer, and an oxide A third insulating layer provided in contact with the semiconductor layer, and a third insulating layer in contact with the third insulating layer A fourth insulating layer with a higher dielectric constant and a second gate electrode that overlaps with the first gate electrode are connected as the fourth insulating layer. The oxide semiconductor layer is in contact with the insulating layer, and the oxide semiconductor layer is between the second insulating layer and the third insulating layer. A semiconductor is arranged such that the first insulating layer has a higher dielectric constant than the second insulating layer. It is a body device.

[0024] The above configuration solves at least one of the above problems.

[0025] For example, an insulating film containing hafnium is used as the first insulating layer, which has a higher dielectric constant than the second insulating layer. In addition, a hafnium-containing insulating film is used as the fourth insulating layer, which has a higher dielectric constant than the third insulating layer. By doing so, the thickness of the gate insulating layer of a dual-gate transistor can be reduced. This enables miniaturization of dual-gate transistors.

[0026] In the above configuration, the oxide semiconductor layer is a semiconductor layer including the channel formation region of the transistor. When used, depending on the semiconductor manufacturing process, the transistor threshold voltage may become negative. The shift may occur on the negative or positive side. Therefore, the semiconductor containing the channel formation region may shift. In transistors using oxide semiconductors in the layers, a mechanism is available that allows for control of the threshold voltage. The configuration is preferable, and by controlling the potential of the first gate electrode or the second gate electrode It is also possible to control the threshold voltage to a desired value. [Effects of the Invention]

[0027] Transistors that use an oxide semiconductor layer with sufficiently reduced hydrogen concentration and high purity are, This enables the creation of semiconductor devices with low power consumption due to low current consumption.

[0028] Furthermore, the gate insulating layer has a high-k film with excellent low gate leakage current. It can realize the 'njista'.

[0029] Furthermore, transistors using oxide semiconductor layers with sufficiently reduced hydrogen concentration and high purity. These can be formed on a glass substrate, and displays, LSIs, and CPUs can be formed on the glass substrate. It can be used to form memory. By using a large-area glass substrate, the manufacturing cost can be reduced. This can be reduced. [Brief explanation of the drawing]

[0030] [Figure 1] This is a cross-sectional view showing one aspect of the present invention. [Figure 2] This is a cross-sectional process diagram showing one aspect of the present invention. [Figure 3] This is a cross-sectional process diagram showing one aspect of the present invention. [Figure 4] These are a top view and a cross-sectional view showing one aspect of the present invention. [Figure 5] These are a cross-sectional view and a top view illustrating one aspect of the present invention. [Figure 6] This is a cross-sectional view showing one aspect of the present invention. [Figure 7] These are a cross-sectional view and a top view illustrating one aspect of the present invention. [Figure 8] A diagram showing an example of an electronic device. [Modes for carrying out the invention]

[0031] The embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is... Not limited to the following description, the form and details can be modified in various ways, as any person skilled in the art would know. This is easily understood. Furthermore, the present invention shall be interpreted as being limited to the contents of the embodiments described below. It's not something that can be done.

[0032] (Embodiment 1) This embodiment provides an example of a transistor applicable to the semiconductor device disclosed herein. The transistor structures applicable to the semiconductor devices disclosed herein are not particularly limited, for example. For example, the gate electrode is positioned on the upper side of the oxide semiconductor layer via the gate insulating layer. A gate structure, or gate electrode, is located beneath the oxide semiconductor layer via a gate insulating layer. Staggered and planar bottom gate structures can be used. The zista is a single-gate structure in which one channel-forming region is formed, or a double gate structure in which two channels are formed. It may be a double gate structure or a triple gate structure with three gates formed. A dual gate electrode having two gate electrodes positioned above and below the Nell region with gate insulating layers in between. A gate-type design is also acceptable.

[0033] Figures 1(A) through (D) show examples of the cross-sectional structure of a transistor. Figure 1(A) The transistors shown in (D) to (Oxide) use oxide semiconductors as semiconductors. The advantages of using an oxide semiconductor are that the maximum value of the field-effect mobility in the on-state of the transistor is 5 cm 2 / Vsec or more, preferably 10 cm 2 / Vsec or more and 150 cm 2 / Vsec or less), which is relatively excellent, and a low off-current (less than 1 aA / μm, more preferably less than 10 zA / μm, and less than 100 zA / μm at 85°C) can be obtained.

[0034] The transistor 410 shown in FIG. 1(A) is one of the transistors with a bottom gate structure and is also called an inverse staggered transistor.

[0035] The transistor 410 includes a gate electrode 401, a first gate insulating layer 402a, a second gate insulating layer 402b, an oxide semiconductor layer 403, a source electrode 405a, and a drain electrode 405b on a substrate 400 having an insulating surface. Further, an insulating film 407 that covers the transistor 410 and is laminated on the oxide semiconductor layer 403 is provided. A protective insulating layer 409 is further formed on the insulating film 407.

[0036] The transistor 420 shown in FIG. 1(B) is one of the bottom gate structures called a channel protection type (also called a channel stop type) and is also called an inverse staggered transistor.

[0037] The transistor 420 includes a gate electrode 401, a first gate insulating layer 402a, a second gate insulating layer 402b, an oxide semiconductor layer 403, and an insulating layer 427 that functions as a channel protection layer covering the channel formation region of the oxide semiconductor layer 403, a source on a substrate 400 having an insulating surface. It includes a drain electrode 405a and a drain electrode 405b. It also covers the transistor 420. A protective insulating layer 409 is formed.

[0038] The transistor 430 shown in Figure 1(C) is a bottom-gate type transistor, and its insulating surface is A gate electrode 401, a first gate insulating layer 402a, and a first gate insulating layer 402a are provided on the substrate 400 which is a substrate having The gate insulating layer 402b, source electrode 405a, drain electrode 405b, and oxide semiconductor are 2. It includes a conductive layer 403. It also covers the transistor 430 and is in contact with the oxide semiconductor layer 403. An insulating film 407 is provided. A protective insulating layer 409 is further formed on the insulating film 407. It is.

[0039] In transistor 430, the first gate insulating layer 402a is connected to the substrate 400 and the gate The source electrode 405a and drain electrode 405b are provided in contact with the electrode 401, and the second gate It is provided in contact with the gate insulating layer 402b. And the second gate insulating layer 402b, Furthermore, an oxide semiconductor layer 403 is provided on the source electrode 405a and the drain electrode 405b. Yes, they are.

[0040] The transistor 440 shown in Figure 1(D) is a top-gate transistor. The transistor 440 is mounted on a substrate 400 having an insulating surface, with an insulating layer 437 and an oxide semiconductor layer. Body layer 403, source electrode 405a, drain electrode 405b, second gate insulating layer 40 2b includes a first gate insulating layer 402a, a gate electrode 401, a source electrode 405a, and a dot electrode. Wiring layers 436a and 436b are provided in contact with the rain electrode 405b, respectively, and electrical It is connected.

[0041] In this embodiment, as described above, an oxide semiconductor layer 403 is used as the semiconductor layer. As the oxide semiconductor used in the material semiconductor layer 403, the quaternary metal oxide In-Sn- Ga-Zn-O-based oxide semiconductors and ternary metal oxides such as In-Ga-Zn-O-based oxides. Monocrystalline semiconductors, In-Sn-Zn-O oxide semiconductors, In-Al-Zn-O oxide semiconductors Sn-Ga-Zn-O oxide semiconductors, Al-Ga-Zn-O oxide semiconductors, Sn- Al-Zn-O oxide semiconductors and binary metal oxides such as In-Zn-O oxide semiconductors Body, Sn-Zn-O oxide semiconductor, Al-Zn-O oxide semiconductor, Zn-Mg-O system Oxide semiconductors, Sn-Mg-O based oxide semiconductors, In-Mg-O based oxide semiconductors, and unified In-O-based oxide semiconductors, Sn-O-based oxide semiconductors, and Zn-O-based oxide semiconductors are examples of metal oxide systems. A monocrystalline semiconductor can be used. Furthermore, the oxide semiconductor may contain SiO2. Here, for example, an In-Ga-Zn-O oxide semiconductor is made of indium (In), galangal. This means an oxide film containing lium (Ga) and zinc (Zn), and its stoichiometric ratio is There are no specific restrictions. Furthermore, elements other than In, Ga, and Zn may be included.

[0042] Transistors 410, 420, 430, and 440 using the oxide semiconductor layer 403 are in the off state. The current value in the off-state (off-current value) can be reduced.

[0043] Furthermore, transistors 410, 420, 430, and 440 using the oxide semiconductor layer 403 are, Because a relatively high field-effect mobility can be obtained, high-speed operation is possible.

[0044] The first gate insulating layer 402a is obtained using a plasma CVD method or a sputtering method, etc. High-k films containing hafnium, such as hafnium oxide films, hafnium silicate films, and silica Hafnium oxynitride film and hafnium aluminate film are formed as a single layer or in a laminated form. It is possible.

[0045] Furthermore, the second gate insulating layer 402b is a silicon oxide layer (SiO x (x>2), nitride Forming a silicon oxide layer, a silicon oxide nitride layer, and a silicon nitride oxide layer, either as a single layer or in a laminated configuration. This is possible. For example, the first gate insulating layer 402a can be made with a film thickness of 5 nm or more by sputtering. A hafnium oxide layer of 100 nm or less is formed, and a second gate insulating layer is formed on the first gate insulating layer. Layer 402b is a silicon oxide layer (S) with a thickness of 5 nm to 100 nm, formed by sputtering. iO x (x>2)) is stacked to form a gate insulating layer with a total film thickness of 100 nm or less. The thickness of the first gate insulating layer 402a is greater than that of the second gate insulating layer 402b. It is preferable to set it.

[0046] In the top-gate structure transistor 440, the oxide semiconductor layer 403 is in contact with the first The sequence of forming the first gate insulating layer 402a after forming the second gate insulating layer 402b. Let's assume that.

[0047] In bottom-gate transistors 410, 420, and 430, the insulating film that forms the base layer is used. A protective layer may be placed between the substrate and the gate electrode. The protective layer prevents the diffusion of impurity elements from the substrate. It has the function of forming silicon nitride film, silicon oxide film, silicon nitride oxide film, or silicon oxide nitride film. It can be formed by a laminated structure consisting of one or more films selected from silicon films.

[0048] There are no major restrictions on the substrates that can be used for the substrate 400 having an insulating surface, however Glass substrates such as borosilicate glass or aluminobrosilicate glass are used.

[0049] The material of gate electrode 401 is Mo, Ti, Cr, Ta, W, Al, Cu, Nd, Sc, etc. Formed using metallic materials or alloy materials mainly composed of these materials, either as a single layer or in layers. It is possible.

[0050] Examples of conductive films used for the source electrode 405a and drain electrode 405b include Al and C. A metal film containing an element selected from r, Cu, Ta, Ti, Mo, W, or the above elements Metal nitride films containing elemental metals (titanium nitride film, molybdenum nitride film, tungsten nitride film) The following can be used. Also, one or both the underside or upperside of a metal film such as Al or Cu can be used. In the case of high-melting-point metal films such as Ti, Mo, and W, or metal nitride films of these metals (titanium nitride film, nitrogen A configuration in which molybdenum oxide film and tungsten nitride film are stacked is also possible.

[0051] Furthermore, source electrode 405a, drain electrode 405b (the wiring layer formed from the same layer) A conductive metal oxide may be used as the conductive film (including). Examples include indium oxide (In2O3, etc.), tin oxide (SnO2, etc.), and zinc oxide (ZnO, etc.). ), indium tin oxide alloy (In2O3-SnO2, abbreviated as ITO), oxide Indium zinc oxide alloy (In2O3-ZnO, etc.) or these metal oxide materials are oxidized. A silicone-containing material can be used.

[0052] The insulating films 407 and 427, which are placed above the oxide semiconductor layer, are typically silicon oxide films. inorganic materials such as silicon oxide nitride film, aluminum oxide film, or aluminum oxide nitride film. An insulating film can be used. In addition, the insulating layer 437 provided below the oxide semiconductor layer is Typical examples include silicon oxide films, silicon oxide nitride films, aluminum oxide films, or nitrile oxide films. Inorganic insulating films, such as aluminum oxide films, can be used.

[0053] Furthermore, the protective insulating layer 409 provided above the oxide semiconductor layer is made of silicon nitride film, a silicon nitride film, and High-k films containing luminium film, aluminum oxide nitride film, hafnium, etc. are used. This is possible. Examples of high-k films containing hafnium include hafnium oxide films and silica Hafnium acid film, hafnium silicate oxynitride film, hafnium aluminate film, etc. You can use it.

[0054] Thus, in this embodiment, an oxide semiconductor with high field-effect mobility and low off-current value is obtained. A transistor containing a conductive layer is used, and the first gate insulating layer 402a contains hafnium. By using a high-k film, we can provide semiconductor devices that consume less power due to leakage current. It can be provided.

[0055] (Embodiment 2) This embodiment uses Figure 2 to illustrate an example of a transistor including an oxide semiconductor layer and a method for fabricating it. This will be explained in detail. The same parts as or having similar functions as those in the above embodiment, and the process are This can be done in the same manner as the above embodiment, and repeated explanations will be omitted. Also, the same part Detailed explanations will be omitted.

[0056] Figures 2(A) to (E) show examples of the cross-sectional structure of a transistor. The transistor 510 shown is a bottom gate transistor similar to the transistor 410 shown in Figure 1(A). It is a transistor with an inverse staggered structure.

[0057] The following describes the process of fabricating the transistor 510 on the substrate 505, using Figures 2(A) to (E). Explain.

[0058] First, a conductive film is formed on a substrate 505 having an insulating surface, and then a first photolithography is performed. The gate electrode 511 is formed by the process. The resist mask is shaped by the inkjet method. It may be done. If the resist mask is formed by the inkjet method, a photomask is not used. Therefore, manufacturing costs can be reduced.

[0059] The substrate 505 having an insulating surface is a substrate similar to the substrate 400 shown in Embodiment 1. This is possible. In this embodiment, a glass substrate is used as the substrate 505.

[0060] An insulating film, which serves as the base layer, may be provided between the substrate 505 and the gate electrode 511. The base layer is It has the function of preventing the diffusion of impurity elements from the substrate 505, silicon nitride film, silicon oxide By using one or more films selected from silicon film, silicon nitride film, or silicon oxide film. It can be formed by a layered structure.

[0061] Furthermore, the materials of gate electrode 511 are Mo, Ti, Cr, Ta, W, Al, Cu, Nd, S Using metal materials such as c or alloy materials mainly composed of these, it is formed in a single layer or in layers. It is possible.

[0062] Next, a first gate insulating layer 507a is formed on the gate electrode 511. The edge layer 507a is formed by a high-k film using plasma CVD or sputtering. To form.

[0063] In this embodiment, a metal oxide target made of hafnium oxide is used, and RF power supply 1kW, pressure 3mTorr, distance between substrate and target (TS distance) 150m m, assuming a film deposition temperature of room temperature, an argon flow rate of 5 sccm, and an oxygen flow rate of 5 sccm, 50 A hafnium oxide film of nm thickness is formed. Note that the 100 nm hafnium oxide film obtained under the above deposition conditions is also formed. The relative permittivity of the humium film was 15. The permittivity of vacuum ε0 is given by 8.84 × 10⁻⁶. -1 2 Assuming F / m, the electrode pad area is 0.7854 mm². 2 The relative permittivity was calculated using the following method. Also, the oxide was used. After depositing the funium film, the following measurements were taken after heat treatment at 550°C for 1 hour in a nitrogen atmosphere: The relative permittivity of the hafnium oxide film was 15.2, which was almost the same value as immediately after deposition. Hafnium oxide films are almost impossible to etch using wet etching solutions. When etching, use BCl3 gas, Cl2 gas, CHF3 gas, or a mixture of these gases. Use the dry etching method.

[0064] In a later process, the hafnium oxide film is selectively etched to reach the contact point 511. When forming a cleft hole, if a mixed gas of BCl3 and Cl2 is used, If the electrode 511 is a Ti film or Al film, it will be etched together, It is preferable that the uppermost layer of 511 be a W film.

[0065] Next, a second gate insulating layer 507b is formed on the first gate insulating layer 507a. The gate insulating layer 507b is formed using plasma CVD or sputtering, etc. A silicon nitride layer, silicon nitride layer, silicon oxide nitride layer, and silicon oxide nitride layer can be used as a single layer or in a laminated configuration. It can be formed in this way. In this embodiment, the second is formed on the first gate insulating layer 507a As the gate insulating layer 507b, a silicon oxide layer with a thickness of 5 nm to 100 nm is applied by sputtering. Con layer (SiO x (x>2)) are stacked to form a gate insulating layer with a total film thickness of 100 nm or less. ru.

[0066] The oxide semiconductor of this embodiment is an acid that has had impurities removed and is type I or substantially type I. An oxide semiconductor is used. In the technical concept of this invention, an oxide is type I or substantially type I. A semiconductor is a device with a carrier density of 1 × 10⁻⁶. 12 cm -3 Less than, more preferably below the detection limit. 1.45 × 10 10 cm -3 This refers to oxide semiconductors that are less than [a certain level] of purity. Because oxide semiconductors are extremely sensitive to interface state density and interface charge, The interface between the semiconductor layer and the gate insulating layer is important. Therefore, highly purified oxide semiconductors are used. The second gate insulating layer 507b, which is in contact with the first layer, requires high quality.

[0067] For example, high-density plasma CVD using μ-waves (e.g., frequency 2.45 GHz) is dense and It is preferable because it can form a high-quality insulating layer with high dielectric strength. The close contact between the high-quality second gate insulating layer 507b and the interface state density reduces the interface state density. This is because it allows for good interfacial properties.

[0068] Of course, if it can form a good quality insulating layer as the second gate insulating layer 507b, Other film deposition methods such as sputtering can be applied. Furthermore, heat treatment after film deposition can be performed. This modifies the film quality of the second gate insulating layer 507b and the interface characteristics with the oxide semiconductor, thus improving insulation. It may also be a layer. In any case, the film quality of the second gate insulating layer 507b is good. In addition to being able to reduce the interface state density with oxide semiconductors, it is possible to form a good interface. Anything that works is fine.

[0069] Furthermore, the first gate insulating layer 507a, the second gate insulating layer 507b, and the oxide semiconductor film In order to minimize the presence of hydrogen, hydroxyl groups, and water in 530, an oxide semiconductor film As a pretreatment for film deposition of 530, the gate electrode 511 is formed in the preheating chamber of the sputtering apparatus. The formed substrate 505, the first gate insulating layer 507a, or the second gate insulating layer 507b The substrate 505, which has been formed, is preheated to remove impurities such as hydrogen and moisture adsorbed on the substrate 505. It is preferable to detach and exhaust the fluid. The exhaust means provided in the preheating chamber is a cryopump. This is preferable. However, this preheating process can be omitted. Also, this preheating is Before the formation of the insulating layer 516, the source electrode 515a and drain electrode 515b are formed. The same procedure may be performed on substrate 505.

[0070] Next, a second gate insulating layer 507b is applied to a thickness of 2 nm to 200 nm, preferably. An oxide semiconductor film 530 with a wavelength of 5 nm to 30 nm is formed (see Figure 2(A)).

[0071] Furthermore, before depositing the oxide semiconductor film 530 by sputtering, an argon gas is introduced. Inverted sputtering is performed to generate plasma by introducing material into the surface of the second gate insulating layer 507b. It is preferable to remove any attached powdery material (also called particles or debris). A TT is a method that uses an RF power supply on the substrate side under an argon atmosphere without applying voltage to the target side. This method involves applying a voltage to form plasma near the substrate and modify the surface. Nitrogen, helium, oxygen, etc., may be used instead of a argone atmosphere.

[0072] The oxide semiconductor used in the oxide semiconductor film 530 is the oxide semiconductor shown in Embodiment 1. It is possible to include SiO2 in the oxide semiconductor. This uses an In-Ga-Zn-O-based metal oxide target as the oxide semiconductor film 530. The film is deposited by sputtering. The cross-sectional view at this stage corresponds to Figure 2(A). The oxide semiconductor film 530 is subjected to a rare gas (typically argon) atmosphere, an oxygen atmosphere, or It can be formed by sputtering in a mixed atmosphere of noble gas and oxygen.

[0073] For example, a target for fabricating oxide semiconductor film 530 by sputtering is The composition ratio of the metal acid is In2O3:Ga2O3:ZnO = 1:1:1 [molar ratio]. An In-Ga-Zn-O film is deposited using a crystalline target. Not limited to materials and composition, for example, In2O3:Ga2O3:ZnO=1:1:2[mo A metal oxide target with a specific ratio of l may also be used.

[0074] Furthermore, the relative density of the metal oxide target is 90% or more and 100% or less, preferably 95% or less. The percentage is 99.9% or less. By using a metal oxide target with a high relative density, The oxide semiconductor film that is formed can be made into a dense film.

[0075] The sputtering gas used when depositing the oxide semiconductor film 530 is hydrogen, water, hydroxyl group or hydrogen It is preferable to use a high-purity gas from which impurities such as monoxides have been removed.

[0076] The substrate is held in a film deposition chamber under reduced pressure, and the substrate temperature is kept between 100°C and 600°C. The temperature should be between 200°C and 400°C. By depositing the film while heating the substrate, The concentration of impurities in the deposited oxide semiconductor film can be reduced. Damage caused by rinsing is reduced. And, while removing residual moisture in the deposition chamber, hydrogen and moisture are removed. The removed sputtering gas is introduced, and the oxide semiconductor is placed on the substrate 505 using the target described above. A film 530 is deposited. To remove residual moisture in the deposition chamber, an adsorption-type vacuum pump is used, for example. For example, cryopumps, ion pumps, and titanium sublimation pumps are preferred. It seems so. Also, as an exhaust method, it was a turbo pump with a cold trap added. It is also possible. The deposition chamber, which is evacuated using a cryopump, contains, for example, hydrogen atoms and water (H2O). Compounds containing hydrogen atoms (more preferably compounds containing carbon atoms) are exhausted. Therefore, the concentration of impurities in the oxide semiconductor film deposited in the deposition chamber can be reduced.

[0077] An example of film deposition conditions is a distance of 100 mm between the substrate and the target, and a pressure of 0.6 Pa. The conditions applied are a DC power supply of 0.5kW and an oxygen atmosphere (oxygen flow rate ratio of 100%). It can be done. Furthermore, when using a pulsed DC power supply, powdery substances (particles) generated during film formation can be produced. This method is preferable because it reduces (also known as) the film thickness distribution and becomes more uniform.

[0078] Next, the oxide semiconductor film 530 is transformed into island-shaped oxide semiconductors by a second photolithography process. The material is processed into layers. Additionally, a resist mask is used to form island-shaped oxide semiconductor layers. It may also be formed by the jet method. If the resist mask is formed by the inkjet method, photomask Because no screws are used, manufacturing costs can be reduced.

[0079] Furthermore, the first gate insulating layer 507a and the second gate insulating layer 507b have contact holes When forming the oxide semiconductor film 530, the process can be carried out simultaneously with the processing of the oxide semiconductor film 530.

[0080] Note that the etching of the oxide semiconductor film 530 here can be done by dry etching or wet etching. Wetting is also acceptable, and both can be used. For example, wet etching of oxide semiconductor film 530 Etching solutions used for chipping include a solution of phosphoric acid, acetic acid, and nitric acid, and ITO07N (Manufactured by Kanto Chemical Co., Ltd.) may also be used.

[0081] Next, the oxide semiconductor layer is subjected to a first heat treatment. This first heat treatment causes the oxide semiconductor layer The conductive layer can be dehydrated or dehydrogenated. The temperature of the first heat treatment is 400°C. The temperature shall be 750°C or higher, or 400°C or higher, below the substrate's strain point. Here, the heat treatment equipment The substrate is introduced into an electric furnace, one of the furnaces, and the oxide semiconductor layer is subjected to a nitrogen atmosphere at 450°C. After a 1-hour heat treatment, water and water are removed from the oxide semiconductor layer without exposure to the atmosphere. This prevents the re-incorporation of the element and obtains the oxide semiconductor layer 531 (see Figure 2(B)).

[0082] Furthermore, the heat treatment device is not limited to electric furnaces, but also includes heat conduction or heat from heat-generating elements such as resistance heating elements. A device that heats the object to be processed by radiation may also be used. For example, GRTA(Gas R apid Thermal Anneal) equipment, LRTA (Lamp Rapid T RTA (Rapid Thermal Annealing) devices such as hermal annealing equipment al) equipment can be used. LRTA equipment uses halogen lamps, metal halide lamps. Lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps This is a device that heats an object to be processed by radiating light (electromagnetic waves) from a lamp or similar light source. The GRTA device is a device that performs heat treatment using high-temperature gas. Noble gases such as argon, or nitrogen, which do not react with the material being treated by heat treatment. An active gas is used.

[0083] For example, as a first heat treatment, the base is placed in an inert gas heated to a high temperature of 650°C to 700°C. The board is moved and placed inside, heated for several minutes, then the substrate is moved and placed in a hot inert gas chamber. You may perform a GRTA (Great Value Analysis) from this source.

[0084] In the first heat treatment, nitrogen or a noble gas such as helium, neon, or argon is used. It is preferable that it does not contain water, hydrogen, etc. Alternatively, nitrogen introduced into the heat treatment device, Alternatively, the purity of noble gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably 7N (99.99999%) or higher (i.e., impurity concentration of 1 ppm or less, preferably) It is preferable that the concentration be 0.1 ppm or less.

[0085] Furthermore, after heating the oxide semiconductor layer in the first heat treatment, high-purity oxygen gas is added to the same furnace. A 10°C N2O gas or ultra-dry air (with a dew point of -40°C or lower, preferably -60°C or lower) is introduced. It may be added. It is preferable that the oxygen gas or N2O gas does not contain water, hydrogen, etc. Alternatively, the purity of the oxygen gas or N2O gas introduced into the heat treatment device is preferably 6N or higher. Preferably, the impurity concentration in oxygen gas or N2O gas is 7N or higher (i.e., 1 ppm or less). It is preferable to keep the concentration below 0.1 ppm. Due to the action of oxygen gas or N2O gas, The process of removing impurities through dehydration or dehydrogenation treatment simultaneously reduces the amount of impurities. By supplying oxygen, one of the materials that make up oxide semiconductors, The layer is purified and electrically converted to type I (intrinsic).

[0086] Furthermore, the first heat treatment of the oxide semiconductor layer is performed on the oxide before it is processed into an island-shaped oxide semiconductor layer. This can also be done on the semiconductor film 530. In that case, after the first heat treatment, the heating device or Then the substrate is removed and the photolithography process is performed.

[0087] Furthermore, the first heat treatment can also be performed after oxide semiconductor layer deposition, in addition to the above. After stacking the source electrode and drain electrode on a layer, or the source electrode and drain Either method is acceptable: after forming an insulating layer on the electrode, or afterwards.

[0088] Furthermore, the first gate insulating layer 507a and the second gate insulating layer 507b have contact holes When forming the oxide semiconductor film 530, the process can be carried out even before the first heat treatment is performed on the oxide semiconductor film 530. It's okay to do it later.

[0089] Furthermore, by depositing the oxide semiconductor layer in two stages and performing heat treatment in two stages, the substrate Regardless of the material of the component, such as oxides, nitrides, or metals, the crystalline region with a thick film thickness, i.e., the film An oxide semiconductor layer having a crystalline region oriented along the c axis perpendicular to the surface may be formed. For example, A first oxide semiconductor film with a thickness of 3 nm to 15 nm is deposited, and nitrogen, oxygen, noble gas, or In a dry air atmosphere, 450°C to 850°C, preferably 550°C to 750°C. A first heat treatment is performed, and a first heat treatment is performed, which has a crystalline region (including plate-like crystals) in the region including the surface. An oxide semiconductor film is formed. Then, a second oxide semiconductor film thicker than the first oxide semiconductor film is formed. A second membrane is formed, and the temperature is between 450°C and 850°C, preferably between 600°C and 700°C. The first oxide semiconductor film is subjected to heat treatment, and crystals are grown upward using the first oxide semiconductor film as a seed for crystal growth. A second oxide semiconductor film is crystallized, resulting in an oxide semiconductor having a thick crystalline region. It may form layers.

[0090] Next, a source electrode and an oxide semiconductor layer are placed on the second gate insulating layer 507b and the oxide semiconductor layer 531. A conductive film is formed that will serve as the drain electrode (including wiring formed from the same layer). The conductive film used for the electrode and drain electrode is the source electrode 40 shown in Embodiment 1. 5a, the same material used for the drain electrode 405b can be used.

[0091] A third photolithography step forms a resist mask on the conductive film, and selectively extracts the residue. After forming the source electrode 515a and drain electrode 515b by ching, the resist mass Remove the "ku" (see Figure 2(C)).

[0092] For exposure during resist mask formation in the third photolithography process, ultraviolet light and KrF light are used. It is preferable to use a laser or ArF laser. Adjacent source electrodes on the oxide semiconductor layer 531 The gap between the lower end and the lower end of the drain electrode determines the channel of the transistor that is later formed. The channel length L is determined. Note that when performing exposure with a channel length L = less than 25 nm, the third process The exposure during resist mask formation in the photolithography process is extremely low, ranging from a few nanometers to tens of nanometers. It is best to use extremely short wavelength ultraviolet light. Exposure with ultraviolet light yields high resolution and a large depth of field. Therefore, the transients that are formed later... The channel length L of the TA can also be set to 10 nm or more and 1000 nm or less, and the circuit operation It can increase speed.

[0093] Furthermore, in order to reduce the number of photomasks and processes used in the photolithography process, The resist mask formed by a multi-tone mask, which is an exposure mask where the light has multiple intensities, is formed by the light. The etching process may be performed using a mask. A resist mask formed using a multi-gradation mask. The ske has a shape with multiple film thicknesses, and can be further deformed by etching. Therefore, it can be used in multiple etching processes to process different patterns. And, a single multi-tone mask can correspond to at least two different patterns. A dystomask can be formed. Therefore, the number of exposure masks can be reduced. This also reduces the number of photolithography steps, thus simplifying the process.

[0094] Furthermore, during the etching of the conductive film, the oxide semiconductor layer 531 is etched and fragmented. To avoid this, it is desirable to optimize the etching conditions. However, for oxide semiconductors... It is difficult to obtain conditions that allow etching only the conductive film without etching layer 531 at all. During etching of the conductive film, a portion of the oxide semiconductor layer 531 is etched, forming grooves (recesses). It can also become an oxide semiconductor layer having [a specific characteristic].

[0095] In this embodiment, a Ti film is used as the conductive film, and the oxide semiconductor layer 531 is made of In-Ga- Since a Zn-O-based oxide semiconductor was used, ammonia hydrogen peroxide (3) was used as the etchant for the Ti film. Use 1 wt% hydrogen peroxide solution, 28 wt% ammonia solution, and water (5:2:2).

[0096] Next, plasma treatment is performed using a gas such as N2O, N2, or Ar, and the exposed material is then... Adsorbed water and other substances attached to the surface of the oxide semiconductor layer may be removed. In this case, after plasma treatment, a protective insulation is applied to a portion of the oxide semiconductor layer without contact with the atmosphere. An insulating layer 516, which will form the edge film, is created.

[0097] The insulating layer 516 has a thickness of at least 1 nm, and water is applied to the insulating layer 516 by sputtering or other methods. The insulating layer 516 can be formed using appropriate methods that prevent the inclusion of impurities such as hydrogen. When hydrogen is present, the hydrogen penetrates the oxide semiconductor layer, or the hydrogen affects the oxide semiconductor layer. Oxygen is extracted from the layer, and the back channel of the oxide semiconductor layer becomes less resistive (N-type). This may lead to the formation of parasitic channels. Therefore, the insulating layer 516 should be as thin as possible. To ensure that the resulting film is hydrogen-free, it is important to avoid using hydrogen in the film deposition method.

[0098] In this embodiment, a silicon oxide film with a thickness of 200 nm is sputtered as the insulating layer 516. The film is deposited using the 3D method. The substrate temperature during film deposition should be between room temperature and 300°C. The application temperature is set to 100°C. For silicon oxide film deposition by sputtering, a rare gas (representative) is used. In particular, under an argon atmosphere, an oxygen atmosphere, or a mixed atmosphere of a noble gas and oxygen. It is possible to use silicon oxide targets or silicon tar as targets. A GET can be used. For example, using a silicon target in an oxygen-containing atmosphere. Below, silicon oxide can be formed by sputtering. In contact with the oxide semiconductor layer, The insulating layer 516 that forms the structure is resistant to moisture, hydrogen ions, and OH - It does not contain impurities such as these, and these Inorganic insulating films are used to block external intrusion, typically silicon oxide films, acid A silicon nitride film, an aluminum oxide film, or an aluminum oxide nitride film is used.

[0099] Similar to the deposition of the oxide semiconductor film 530, residual moisture in the deposition chamber of the insulating layer 516 is removed. For this purpose, it is preferable to use an adsorption-type vacuum pump (such as a cryopump). The concentration of impurities in the insulating layer 516 deposited in the deposition chamber, which is evacuated using an op-pump, is reduced. Yes, it is possible. Furthermore, as an exhaust means for removing residual moisture in the film deposition chamber of the insulating layer 516, A turbopump with a cold trap added may also be used.

[0100] The sputtering gas used when forming the insulating layer 516 is hydrogen, water, hydroxyl groups, or hydrides. It is preferable to use a high-purity gas from which impurities have been removed.

[0101] Next, a second heat treatment (preferably 2) is performed under an inert gas atmosphere or an oxygen gas atmosphere. Perform the procedure at temperatures between 0°C and 400°C (for example, between 250°C and 350°C). For example, under a nitrogen atmosphere. A second heat treatment is performed at 250°C for 1 hour under gas pressure. After the second heat treatment, the oxide semiconductor A portion of the body layer (channel-forming region) is heated while in contact with the insulating layer 516.

[0102] A first heat treatment performed on an oxide semiconductor film (hydrogen, water, hydroxyl group or hydride (water) This process involves intentionally removing impurities such as elementary compounds from the oxide semiconductor layer. At the same time, oxygen, one of the materials that make up oxide semiconductors, decreases through the above process. By going through this process, it can be supplied to the oxide semiconductor layer. Therefore, the oxide semiconductor layer To increase purity and electrically convert to Type I (intrinsic).

[0103] The transistor 510 is formed through the above process (see Figure 2(D)).

[0104] Furthermore, if a silicon oxide layer containing many defects is used for the insulating layer 516, after the silicon oxide layer is formed... By heat treatment, hydrogen, water, hydroxyl groups or hydrides contained in the oxide semiconductor layer are removed. This has the effect of diffusing impurities into the insulating layer and further reducing the amount of impurities contained in the oxide semiconductor layer. To play.

[0105] A protective insulating layer 506 may be formed on the insulating layer 516. For example, the RF sputtering method A silicon nitride film is formed using this method. RF sputtering is suitable for mass production, and the protective insulating layer This is a preferred method for forming a film. The protective insulating layer does not contain impurities such as moisture, and these are protected from the outside. Using an inorganic insulating film that blocks penetration, silicon nitride film, aluminum nitride film, etc. In this embodiment, the protective insulating layer 506 is formed using a silicon nitride film. (See Figure 2(E)).

[0106] In this embodiment, the protective insulating layer 506 is made of the substrate 505 formed up to the insulating layer 516. Spam containing high-purity nitrogen, which has been heated to a temperature of 100°C to 400°C and from which hydrogen and moisture have been removed. Tagus is introduced, and a silicon nitride film is deposited using a silicon semiconductor target. Even in this case, similar to the insulating layer 516, the protective insulating layer 5 removes residual moisture in the processing chamber. It is preferable to form a film of 06.

[0107] After forming the protective insulating layer, further immerse in air at a temperature between 100°C and 200°C for 1 to 30 hours. The following heat treatment may be performed. This heat treatment may be carried out while maintaining a constant heating temperature. Furthermore, the temperature is raised from room temperature to a heating temperature of 100°C to 200°C, and from the heating temperature back to room temperature. The cooling process can be repeated multiple times.

[0108] Thus, a trace containing a highly purified oxide semiconductor layer fabricated using this embodiment The inverter can achieve high speed operation because it provides high field-effect mobility. First gate By using a hafnium oxide film as an insulating layer, the gate leakage current of the transistor can be reduced. This makes it possible to reduce power consumption, thereby achieving power savings in semiconductor devices.

[0109] Furthermore, by using a hafnium oxide film as the first gate insulating layer, the silicon oxide film alone can form The same effect as the gate insulating layer with a thickness of 0.8 nm or less can be achieved with a thickness of 2 nm or more (specifically, It can be obtained with a gate insulating layer with a thickness of 2 nm to 10 nm.

[0110] Furthermore, this embodiment can be freely combined with Embodiment 1.

[0111] (Embodiment 3) In this embodiment, two gates are arranged above and below the channel region with a gate insulating layer in between. An example of fabricating a dual-gate transistor with electrodes is shown below.

[0112] Since the intermediate steps are the same as in Embodiment 2, the same reference numerals are used to indicate the same parts. I will reveal it.

[0113] Figures 3(A) to 3(C) show examples of the cross-sectional structure of a transistor. Figure 3(A) is the same as Figure 2(C). This is identical to the previous example. First, according to Embodiment 2, we obtain the state shown in Figure 3(A).

[0114] Next, similar to Embodiment 2, an insulating layer 5, which serves as a protective insulating film in contact with a portion of the oxide semiconductor layer. Form 16. In this embodiment, a second gate electrode is formed in a later step. This forms an insulating film of the same material and thickness as the second gate insulating layer 507b.

[0115] Next, as shown in Figure 3(B), a material with a higher dielectric constant than the insulating layer 516 is placed on the insulating layer 516. An insulating layer 526 is formed. The insulating layer 526 is made of the same material as the first gate insulating layer 507a. A hafnium oxide film forms an insulating film with the same thickness of 20 nm.

[0116] Next, a second gate electrode 508 is formed on the insulating layer 526. The materials are metallic materials such as Mo, Ti, Cr, Ta, W, Al, Cu, Nd, Sc, etc. These can be formed using alloy materials that are the main components, either as a single layer or in layers.

[0117] By following the above steps, the transistor 520 shown in Figure 3(C) can be manufactured.

[0118] Furthermore, the insulating layer 526, which is hafnium oxide, is almost completely etched by wet etching. To prevent this from happening, wet etching is used when patterning the second gate electrode 508. When present, it functions as an etching stopper film, and the thickness of the insulating layer 526 is 2 nm or more and 10 nm Even if the thickness is less than m, the insulating layer 526 is free of pinholes and has a uniform dielectric strength. This makes the ZISTA 520 possible.

[0119] An insulating film containing hafnium is used as the first insulating layer, which has a higher dielectric constant than the second insulating layer. An insulating film containing hafnium is used as the fourth insulating layer, which has a higher dielectric constant than the third insulating layer. Therefore, the gate insulating layer of this embodiment is better than the gate insulating layer when calculated using a silicon oxide film. Thin films can be made.

[0120] When an oxide semiconductor layer is used in a semiconductor layer that includes the channel formation region of a transistor, Depending on the manufacturing process of the device, the transistor threshold voltage may be on the negative or positive side. This can shift to a certain state. Therefore, an oxide semiconductor is used in the semiconductor layer containing the channel formation region. The transistor used had a dual-gate structure, like transistor 520. A configuration that allows control of the threshold voltage is preferred, and the first gate electrode 511 and This controls the threshold voltage to a desired value by controlling the potential of the second gate electrode 508. It is also possible to do so.

[0121] This embodiment can be freely combined with Embodiment 1 or Embodiment 2.

[0122] (Embodiment 4) Oxide semiconductor layers are susceptible to the effects of electric fields generated during the manufacturing process. Therefore, in practice... When fabricating a top-gate type transistor as shown in Figure 1(D) of state 1, oxidation To reduce the effects of electric fields and other factors that occur when forming a gate insulating layer on a semiconductor layer using the sputtering method. Figure 4 shows the film deposition apparatus used for this purpose.

[0123] In this embodiment, the hafnium oxide film is deposited using the film deposition apparatus shown in Figures 4(A) and 4(B). Here is an example.

[0124] The chamber 301 is kept under vacuum, and a mixture of O2 gas and Ar gas is used as the raw material gas. Alternatively, Ar gas is flowed, and electrode 302, which is connected to RF power supply 304, and electrode 303 face each other. It is provided as follows. Electrodes 302 and 303 have hafnium oxide targets 308 and 30 Each of the 9s is fixed.

[0125] Figure 4(A) is a schematic top view of the chamber 301 as seen from above, and Figure 4(B) is a schematic top view of the chamber 301. This is a schematic cross-sectional view of chamber 301.

[0126] To accommodate large-area substrates, the substrate 305 is positioned vertically for sputter deposition. The hafnium targets 308 and 309 are opposite each other, with the substrate 305 placed between them. By preventing this, the substrate 305 is hardly exposed to the plasma. 05 is provided with an oxide semiconductor layer covered with an insulating film, as shown in Figures 4(A) and 4(B). By using the apparatus shown, the oxide semiconductor layer can be damaged without causing any practical problems (plasma damage). Hafnium oxide films can be deposited without causing any damage (such as image). Thus, A hafnium oxide film is deposited on the surface of the substrate 305, which is fixed by the holder 307. The shutter 306 stops the formation of the coating on the substrate until the speed stabilizes, and the shutter 3 Open 06 and start the film deposition. In Figures 4(A) and 4(B), shutter 306 A sliding shutter is shown in the illustration, but it is not particularly limited to this type of shutter.

[0127] In FIG. 4(A), the substrate surface is shown perpendicular to the bottom surface of the chamber, but it is not particularly limited, and the substrate surface may be arranged obliquely with respect to the bottom surface of the chamber by the holder 307. The holder 307 is provided with a heater, and film formation can be performed while heating the substrate 305. It can be done.

[0128] Using the heater of the holder 307, the substrate 30 5 is held in the chamber 301 maintained in a reduced pressure state, and the temperature of the substrate 305 is 100° C. or higher and lower than 550° C., preferably 200° C. or higher and 4 00° C. or lower, and the oxide semiconductor layer on the substrate 305 can also be heated. Then, while removing moisture in the chamber 301, a sputtering gas (oxygen or argon) from which hydrogen and water have been removed is introduced, and a hafnium oxide film is formed using the above target. The oxide hafnium film can also be formed while heating the substrate 305 using the heater of the holder 307. By doing so, damage due to sputtering can also be reduced.

[0129] In order to remove moisture in the chamber 301, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, a titanium sublimation pump, etc. can be used. Alternatively, a turbo pump with a cold trap added may be used. By evacuating using a cryopump or the like, hydrogen, water, etc. can be removed from the processing chamber. It can be done.

[0130] In addition, in this embodiment, a hafnium oxide film has been described as an example, but it is not particularly limited, and an insulating film that can be used for a gate insulating layer or a film forming apparatus shown in FIG. 4 can be used for forming other high-k films. In addition, the film forming apparatus shown in FIG. 4 can be used for forming an insulating film in contact with an oxide semiconductor layer. Also, the film forming apparatus shown in FIG. 4 is for forming an insulating film in contact with an oxide semiconductor layer. It can also be used in membranes.

[0131] (Embodiment 5) In this embodiment, the external appearance and cross-section of a liquid crystal display panel, which corresponds to one form of semiconductor device, are described below. Next, we will explain using Figure 5. Figures 5(A) and 5(C) show transistors 4010 and 40 11, and the liquid crystal element 4013 is placed between the first substrate 4001 and the second substrate 4006. This is a plan view of the panel sealed with material 4005, and Figure 5(B) is also a plan view of Figure 5(A). This corresponds to the cross-sectional view at MN in Figure 5(C).

[0132] The pixel section 4002 and the scanning line driving circuit 4004 are surrounded on the first substrate 4001. A sealing material 4005 is provided in this manner. Also, the pixel section 4002 and the scan line drive rotation A second substrate 4006 is provided on the path 4004. Therefore, the pixel section 4002 and the scanning The line drive circuit 4004 consists of the first substrate 4001, the sealing material 4005, and the second substrate 4006. It is sealed together with the liquid crystal layer 4008. Also, the seal on the first substrate 4001 A single crystal is placed on a separately prepared substrate in a region different from the area enclosed by material 4005. A signal line driving circuit 4003, formed from a semiconductor film or a polycrystalline semiconductor film, is mounted.

[0133] Furthermore, the method of connecting the separately formed drive circuit is not particularly limited, and COG method, Wire bonding methods or TAB methods can be used. Figure 5(A) shows This is an example of implementing the signal line drive circuit 4003 using the COG method, and Figure 5(C) shows the TAB method. This is an example of implementing the signal line drive circuit 4003 according to the law.

[0134] Also, the pixel portion 4002 provided on the first substrate 4001 and the scanning line driving circuit 4004 each have a plurality of transistors. In FIG. 5(B), the transistor 4010 included in the pixel portion 4002 and the transistor 4011 included in the scanning line driving circuit 4004 are illustrated. The transistor 4011 has a first gate insulating layer 4020a and a second gate insulating layer 40 20b, and the first gate insulating layer 402a and the second gate insulating layer 40 2b shown in Embodiment 2 can be used. By using a high-k film as the first gate insulating layer 402a , a transistor with less gate leakage current can be obtained. Insulating layers 4041, 4042, and 4021 are provided on the transistors 4010 and 4011.

[0135] The transistors 4010 and 4011 can be the transistors with less gate leakage current shown in Embodiment 1. As the transistor 4011 for the driving circuit and the transistor 4010 for the pixel, the transistors 410, 420, 43 0, and 440 shown in Embodiment 1 can be used. In the present embodiment, the transistors 4010 and 40 11 are n-channel transistors.

[0136] On the insulating layer 4021, a conductive layer 4040 is provided at a position overlapping with the channel formation region of the oxide semiconductor layer of the transistor 4011 for the driving circuit. By providing the conductive layer 4040 at a position overlapping with the channel formation region of the oxide semiconductor layer, the change amount of the threshold voltage of the transistor 4011 before and after the BT test can be reduced. Also, the potential of the conductive layer 4 040 may be the same as or different from the potential of the gate electrode of the transistor 4011. It may also be used as a second gate electrode. The position may be GND, 0V, or in a floating state.

[0137] Furthermore, the pixel electrode layer 4030 of the liquid crystal element 4013 is electrically connected to the transistor 4010. It is connected to the second substrate 4006. The counter electrode layer 4031 of the liquid crystal element 4013 is connected to the second substrate 4006. The pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 are formed on top of each other. The part that is made up corresponds to the liquid crystal element 4013. Note that the pixel electrode layer 4030 and the counter electrode Layer 4031 is provided with insulating layers 4032 and 4033, which function as alignment films, and is insulating The liquid crystal layer 4008 is sandwiched between layers 4032 and 4033.

[0138] Furthermore, translucent substrates can be used as the first substrate 4001 and the second substrate 4006. Plastics such as polyester film or acrylic resin film, or glass. Ceramics and other materials can be used.

[0139] Furthermore, 4035 is a columnar spacer obtained by selectively etching an insulating film. To control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 It is provided in [location]. A spherical spacer may also be used. Also, the counter electrode layer 4031 It is electrically connected to a common potential line provided on the same substrate as transistor 4010. Using a common connection, the opposing electrode layer 4031 is connected via conductive particles placed between the pair of substrates. It can be electrically connected to a common potential line. Note that the conductive particles are sealing material 4005 It is to be included in it.

[0140] Furthermore, a liquid crystal exhibiting a blue phase without an alignment layer may be used, in which case the transverse electric field method and Therefore, a different electrode arrangement will be used from the one shown in Figure 5. For example, the pixel electrode layer will be placed on the same insulating layer. The common electrode layer is placed side by side, and a transverse electric field is applied to the liquid crystal layer. The blue phase is one of the liquid crystal phases. Yes, as the temperature of a cholesteric liquid crystal is increased, it transitions from the cholesteric phase to the isotropic phase. This is the phase that appears earlier. The blue phase only appears within a narrow temperature range, so improving the temperature range is necessary. To achieve this, a liquid crystal composition containing 5% or more by weight of a chiral agent is used in the liquid crystal layer 4008. The liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 1 msec. It is short, optically isotropic, and therefore requires no orientation processing, and has low dependence on viewing angle.

[0141] In addition to transmissive liquid crystal displays, this method can also be applied to semi-transmissive liquid crystal displays.

[0142] Furthermore, in liquid crystal display devices, a polarizing plate is provided on the outside (viewing side) of the substrate, and a colored layer and display element are provided on the inside. The example shows the electrode layers being arranged in the order of the child, but the polarizing plate may be placed on the inside of the substrate. Furthermore, the laminated structure of the polarizing plate and the colored layer is not limited to this embodiment, and the materials of the polarizing plate and the colored layer may also vary. The settings should be adjusted as appropriate depending on the manufacturing process conditions. In addition, a black matrix can be used in addition to the display area. A light-shielding film that functions in this way may be provided.

[0143] An insulating layer 4041 is formed on transistors 4011 and 4010 in contact with the oxide semiconductor layer. The insulating layer 4041 is made of the same material and method as the insulating film 407 shown in Embodiment 1. It is sufficient to form it. Here, as the insulating layer 4041, the film deposition apparatus of Embodiment 4 is used. A silicon oxide film is formed by the putter method. A protective insulating layer 40 is also placed in contact with the insulating layer 40 41. 42 is formed. Also, the insulating layer 4042 is the same as the protective insulating layer 409 shown in Embodiment 1. It can be formed using any material and method. In addition, in order to reduce surface irregularities of the transistor, The configuration involves covering the edge layer 4042 with an insulating layer 4021 that functions as a planar insulating film.

[0144] Furthermore, an insulating layer 4021 is formed as a planar insulating film. The insulating layer 4021 is made of poly Heat-resistant organic materials such as mids, acrylics, benzocyclobutenes, polyamides, and epoxys. Materials can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials) can also be used. Using siloxane-based resins, PSG (phosphorus glass), BPSG (phosphorus boron glass), etc. This can be achieved by stacking multiple insulating films made of these materials. 4021 may be formed.

[0145] The method for forming the insulating layer 4021 is not particularly limited and can be sputtered or SOG depending on the material. Spin coating, dip coating, spray coating, droplet ejection (inkjet method, screen coating) Printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife A f-coater or the like can be used. The firing process of the insulating layer 4021 and the annealing of the semiconductor layer are performed. By combining these processes, it becomes possible to efficiently manufacture semiconductor devices.

[0146] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Titanium oxide-containing indium tin oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide with added silicon dioxide. Conductive materials can be used.

[0147] In addition, a separately formed signal line drive circuit 4003 and a scan line drive circuit 4004 or pixel unit 4 The various signals and potentials supplied to 002 are provided by the FPC4018.

[0148] Is the connection terminal electrode 4015 made of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013? Formed from there, the terminal electrode 4016 is the source electrode and of transistors 4010 and 4011. It is formed from the same conductive film as the rain electrode.

[0149] The connecting terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. They are electrically connected.

[0150] Furthermore, in Figure 5, a signal line drive circuit 4003 is formed separately and mounted on the first substrate 4001. The example shown is not limited to this configuration. A separate scan line drive circuit can be formed and implemented. Alternatively, you can separately form only a part of the signal line drive circuit or a part of the scan line drive circuit. You may wear it.

[0151] (Embodiment 6) In this embodiment, an example of electronic paper is shown as one form of semiconductor device.

[0152] A transistor including a stacked gate insulating layer obtained by the method shown in Embodiment 2 is a Swiss transistor. Electronic paper uses a switching element and an electrically connected element to drive the electronic ink. It may be used. Electronic paper is also called an electrophoretic display device (electrophoretic display). It offers the same readability as paper, lower power consumption compared to other display devices, and a thin and lightweight form factor. It has the advantage of making this possible.

[0153] Electrophoretic displays can take various forms, but one involves a first particle with a positive charge. A microcapsule containing a child and a second particle having a negative charge is placed in a solvent or solute. It is a multiple dispersed material, and by applying an electric field to the microcapsules, micro Move the particles inside the capsule in opposite directions and display only the color of the particles that have gathered on one side. It is such that the first or second particle contains dye and, in the absence of an electric field, It does not move. Also, the color of the first particle and the color of the second particle are different (colorless). (Includes)

[0154] Thus, in electrophoretic displays, substances with high dielectric constants move to regions with high electric fields. This is a display that utilizes the so-called dielectrophoretic effect.

[0155] When the above microcapsules are dispersed in a solvent, it is called an electronic ink. This electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. Color display is also possible by using color filters or particles containing pigments.

[0156] Furthermore, the microphone is placed on the active matrix substrate, appropriately sandwiched between the two electrodes. By arranging multiple microcapsules, an active-matrix type display device can be completed. By applying an electric field to the cell, a display can be created. For example, the transistor of Embodiment 2 An active matrix substrate obtained by this method can be used.

[0157] Furthermore, the first and second particles in the microcapsules are made of conductive material, insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, electro A type of material selected from trochromic materials, magnetophoretic materials, or a composite material thereof Use it.

[0158] Figure 6 shows an active-matrix electronic paper as an example of a semiconductor device. The transistor 581 used in this configuration is the same as the transistor shown in Embodiment 2. It is a transistor that can be manufactured and has low gate leakage current.

[0159] The electronic paper in Figure 6 is an example of a display device using a twist ball display method. The ball display method is an electrode layer that uses spherical particles painted in white and black as display elements. It is placed between the first electrode layer and the second electrode layer, and a potential difference is created between the first electrode layer and the second electrode layer. This method of display is achieved by controlling the orientation of spherical particles that are generated.

[0160] Transistor 581 is a bottom-gate transistor, and the first gate insulating layer 58 2a, having an oxide semiconductor layer in contact with the stack of second gate insulating layers 582b, It is covered by an insulating layer 583 that is in contact with the conductor layer. The first gate insulating layer 582a is Huff An insulating film containing nium is used, and a film with a higher dielectric constant than the second gate insulating layer 582b is used. It is.

[0161] The source electrode or drain electrode of transistor 581 consists of a first electrode layer 587 and an insulating layer 5 The first electrode is electrically connected to the openings formed at 83, 584, and 585. Between layer 587 and the second electrode layer 588, there is a black region 590a and a white region 590b. A spherical particle 589, surrounded by liquid, is placed between a pair of substrates 580 and 596. The spherical particles 589 are surrounded by a filler material 595 such as resin (see Figure 6). .

[0162] Furthermore, the first electrode layer 587 corresponds to the pixel electrode, and the second electrode layer 588 corresponds to the common electrode. The second electrode layer 588 is provided on the same substrate as the transistor 581 and has a common potential line. Electrically connected. A common connection is used to place a guide between a pair of substrates 580 and 596. The second electrode layer 588 and the common potential line can be electrically connected via the electrolytic particles.

[0163] Alternatively, an electrophoretic element can be used instead of a twist ball. (Transparent liquid) And, positively charged white particles and negatively charged black particles are enclosed in a diameter of 10 μm to 20 Microcapsules of approximately 0 μm are used. They are placed between the first electrode layer and the second electrode layer. The microcapsules, when an electric field is applied, are formed by the first electrode layer and the second electrode layer, and white The white and black particles move in opposite directions, allowing for the display of either white or black. An electrophoretic display element, commonly known as electronic paper, is a display element that applies this principle. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary lights are not required. Furthermore, it consumes little power and the display can be seen even in dimly lit places. Even if power is not supplied to the display unit, it is possible to retain the image that has been displayed. Therefore, a semiconductor device with a display function (simply a display device, or equipped with a display device) is transmitted from a radio wave source. Even when the semiconductor device (also called a semiconductor device) is moved away, the displayed image is saved. This becomes possible.

[0164] Through the above process, a transistor with low gate leakage current and low power consumption is achieved. It is possible to create paper.

[0165] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0166] (Embodiment 7) In this embodiment, a transistor using an oxide semiconductor and a transistor using a material other than an oxide semiconductor are used. An example of forming transistors on the same substrate is shown below.

[0167] Figure 7 shows an example of the configuration of a semiconductor device. Figure 7(A) shows a cross-section of the semiconductor device. Figure B) shows the planes of the semiconductor device. Here, Figure 7(A) is the same as A in Figure 7(B). This corresponds to the cross-sections at 1-A2 and B1-B2. (See Figures 7(A) and 7(B)) The semiconductor device has a transistor 160 made of a first semiconductor material at the bottom, and at the top The present invention has a transistor 162 made of a second semiconductor material. The first semiconductor material is a semiconductor material other than an oxide semiconductor (such as silicon), and the second semiconductor material is an oxide semiconductor. It is a material semiconductor. Transistors using materials other than oxide semiconductors are easy to operate at high speed. On the other hand, transistors using oxide semiconductors can retain charge for long periods of time due to their characteristics. Make it possible.

[0168] In Figure 7, transistor 160 is located on a substrate containing a semiconductor material (e.g., silicon). A channel formation region 116 is provided in 00, and is provided so as to sandwich the channel formation region 116 The impurity region 120, the metal compound region 124 adjacent to the impurity region 120, and the channel A gate insulating layer 108 provided on the gate forming region 116, and a gate insulating layer 108 provided on the gate insulating layer 108 It has a gate electrode 110.

[0169] The substrate 100 containing semiconductor material is a single-crystal semiconductor substrate such as silicon or silicon carbide, multi-layered Crystal semiconductor substrates, compound semiconductor substrates such as silicon germanium, and SOI substrates are used. This is possible. Generally, an "SOI substrate" has a silicon semiconductor layer on an insulating surface. This refers to a substrate having a configured structure, but in this specification, etc., a material other than silicon on the insulating surface The term "SOI substrate" is used as a concept that includes substrates with a configuration in which semiconductor layers are provided. The semiconductor layer of the " is not limited to a silicon semiconductor layer. Also, the SOI substrate has glass This includes configurations in which a semiconductor layer is provided on an insulating substrate such as a stainless steel substrate, with an insulating layer in between. Let's assume that.

[0170] An electrode 126 is connected to a portion of the metal compound region 124 of the transistor 160. Here, electrode 126 functions as the source electrode and drain electrode of transistor 160. Furthermore, an element isolation insulating layer 106 is provided on the substrate 100 so as to surround the transistor 160. The transistor 160 is covered by an insulating layer 128 and an insulating layer 130. Furthermore, in order to achieve high integration, the transistor 160 is as shown in Figure 7. It is desirable to have a configuration without a sidewall insulating layer. On the other hand, transistor 16 If the characteristics of 0 are important, a sidewall insulating layer is provided on the side of the gate electrode 110. An impurity region 120 may be provided, which includes regions with different impurity concentrations.

[0171] Transistor 160 can be fabricated using known techniques. The Ta160 has the characteristic of being capable of high-speed operation. Therefore, this transistor By using it as a readout transistor, information can be read out at high speed. ru.

[0172] After forming transistor 160, before forming transistor 162 and capacitive element 164 As a process, CMP treatment is applied to the insulating layer 128 and the insulating layer 130, and the gate electrode 110 and The upper surface of electrode 126 is exposed. The upper surface of gate electrode 110 and electrode 126 is exposed. In addition to CMP processing, etching processing can also be applied ( (The tuning process may be combined with the CMP process.) Note that the characteristics of transistor 162 To improve performance, the surfaces of insulating layer 128 and insulating layer 130 should be made as flat as possible. It is desirable.

[0173] Next, a conductive layer is applied to the gate electrode 110, electrode 126, insulating layer 128, insulating layer 130, etc. Form the conductive layer and selectively etch it to form the source electrode or drain electrode 142a. A source electrode or drain electrode 142b is formed.

[0174] The conductive layer is produced using PVD methods such as sputtering, or CVD methods such as plasma CVD. It can be formed by [method]. Furthermore, the conductive layer material can be Al, Cr, Cu, Ta, T Elements selected from i, Mo, and W, or alloys containing the aforementioned elements, can be used. Yes, it is possible. It can be any of Mn, Mg, Zr, Be, Nd, Sc, or a combination of these. You may use the materials shown.

[0175] The conductive layer may be a single layer or a laminated structure of two or more layers. For example, titanium Single-layer structures of silicon films and titanium nitride films, single-layer structures of silicon-containing aluminum films, aluminum A two-layer structure in which a titanium film is laminated on a titanium film, and a two-layer structure in which a titanium film is laminated on a titanium nitride film. Examples include a three-layer structure in which a titanium film, an aluminum film, and another titanium film are laminated. Oh, when the conductive layer is a single-layer structure of titanium film or titanium nitride film, it has a tapered shape. Source electrode or drain electrode 142a, and source electrode or drain electrode 142 One advantage is that it is easy to process into form b.

[0176] The channel length (L) of the upper transistor 162 is determined by the source electrode or drain electrode 142. This is determined by the distance between a and the lower end of the source electrode or drain electrode 142b. Note that the mask type used when forming transistors with a channel length (L) of less than 25 nm When performing exposure, it is desirable to use ultra-ultraviolet light with a short wavelength of a few nanometers to a few tens of nanometers. .

[0177] Next, an insulating layer 143a is placed on the source electrode or drain electrode 142a, and the source electrode or An insulating layer 143b is formed on the drain electrode 142b. The insulating layer 143b is connected to the source electrode or drain electrode 142a, or to the source electrode or drain After forming an insulating layer covering the rain electrode 142b, the insulating layer is selectively etched. It can be formed by the following. In addition, insulating layers 143a and 143b are formed later. It is formed so as to overlap with a part of the electrode. By providing such an insulating layer, It is possible to reduce the capacitance between the source electrode and the source or drain electrode.

[0178] Insulating layer 143a and insulating layer 143b are silicon oxide, silicon oxynitride, silicon nitride, acid It can be formed using materials containing inorganic insulating materials such as aluminum oxide.

[0179] Furthermore, this reduces the capacitance between the gate electrode and the source or drain electrode. Therefore, it is preferable to form insulating layer 143a and insulating layer 143b, but the insulating layer It is also possible to have a configuration that does not include this feature.

[0180] Next, source electrode or drain electrode 142a, and source electrode or drain electrode 1 After forming an oxide semiconductor layer to cover 42b, the oxide semiconductor layer is selectively etched. This process forms an oxide semiconductor layer 144.

[0181] The oxide semiconductor layer uses the materials and formation process shown in Embodiment 2.

[0182] Subsequently, it is desirable to perform a heat treatment (first heat treatment) on the oxide semiconductor layer. The first heat treatment removes excess hydrogen (including water and hydroxyl groups) from the oxide semiconductor layer. By optimizing the structure of the oxide semiconductor layer, the defect level density in the energy gap can be reduced. The temperature of the first heat treatment is, for example, 300°C or more but less than 550°C, or 400°C or higher. The temperature should be 500℃ or lower.

[0183] Heat treatment involves, for example, introducing the workpiece into an electric furnace using a resistance heating element, and performing the treatment under a nitrogen atmosphere. This can be done under conditions of 450°C for 1 hour. During this time, the oxide semiconductor layer is not exposed to the atmosphere. First, prevent contamination with water or hydrogen. The first heat treatment reduces impurities, resulting in Type I. By forming an oxide semiconductor layer that is (intrinsic) or very close to type I, extremely excellent properties are achieved. This allows us to realize a transistor.

[0184] Next, a first gate insulating layer 146a is formed in contact with the oxide semiconductor layer 144, and then the second The gate insulating layer 146b of the 2 is formed.

[0185] The first gate insulating layer 146a is formed using sputtering or plasma CVD, and silica oxide We use silicon nitride and silicon oxynitride.

[0186] Furthermore, the second gate insulating layer 146b has a relative permittivity of 10 or more as shown in Embodiment 2. A high-k film is used. By using a high-k film, the gate insulating layer can be thinned, resulting in a gate This suppresses the increase in gate current and enables miniaturization of semiconductor devices. The total film thickness of the edge layer 146a and the second gate insulating layer 146b is between 2 nm and 100 nm. Preferably, the wavelength is between 10 nm and 50 nm.

[0187] Next, in the region on the second gate insulating layer 146b that overlaps with the oxide semiconductor layer 144, A source electrode 148a is formed, and electricity is applied to the region that overlaps with the source electrode or drain electrode 142a. It forms pole 148b.

[0188] After the formation of the first gate insulating layer 146a or the second gate insulating layer 146b, the inert It is preferable to perform the second heat treatment under a gaseous or oxygen atmosphere. The heat treatment temperature is The temperature range is 200°C to 450°C, preferably 250°C to 350°C. For example, nitrogen A heat treatment at 250°C for 1 hour in an ambient atmosphere is sufficient. By performing a second heat treatment... This can reduce variations in the electrical characteristics of the transistor. Also, the first gate insulation Because the edge layer 146a or the second gate insulating layer 146b contains oxygen, the oxide semiconductor layer 1 Oxygen is supplied to 44, and the oxygen deficiencies in the oxide semiconductor layer 144 are filled, resulting in type I (intrinsic) or It is also possible to form an oxide semiconductor layer that is very close to type I.

[0189] The timing of the second heat treatment is not limited to this. For example, it may be performed after the formation of the gate electrode. A second heat treatment may be performed. Alternatively, the second heat treatment may be performed immediately after the first heat treatment. Furthermore, the first heat treatment may also serve as the second heat treatment, or the second heat treatment may also serve as the first heat treatment. It's fine to have them do both.

[0190] As described above, by applying at least one of the first heat treatment and the second heat treatment, The semiconductor layer 144 is purified to the highest possible degree so that it contains as few impurities as possible other than its main component. can.

[0191] The gate electrode 148a and electrode 148b form a conductive layer on the second gate insulating layer 146b. The conductive layer can be formed by selectively etching it after the initial stage.

[0192] Next, on the second gate insulating layer 146b, the gate electrode 148a, and the electrode 148b, An edge layer 150 and an insulating layer 152 are formed. The insulating layer 150 and the insulating layer 152 are spat It can be formed using methods such as the ionization process and CVD. Also, silicon oxide and silicon oxynitride can be formed. Materials containing inorganic insulating materials such as silicon nitride, hafnium oxide, and aluminum oxide are used. It can be formed by doing so.

[0193] Next, the first gate insulating layer 146a, the second gate insulating layer 146b, the insulating layer 150, and An opening is formed in the insulating layer 152 that extends to the source electrode or drain electrode 142b. The opening is formed by selective etching using a mask or the like.

[0194] Here, it is desirable to form the above-mentioned opening in a region that overlaps with electrode 126. By forming an opening in a specific region, the increase in element area caused by the electrode contact region is suppressed. This is possible. In other words, it is possible to increase the integration density of semiconductor devices.

[0195] Subsequently, an electrode 154 is formed in the opening, and wiring 15 is placed on the insulating layer 152 in contact with the electrode 154. Form 6.

[0196] Electrode 154 has a conductive layer formed in the region including the opening using methods such as PVD or CVD. Afterward, a portion of the conductive layer is removed using methods such as etching or CMP. It can be formed by the following.

[0197] Wiring 156 is used for PVD methods such as sputtering and CVD methods such as plasma CVD. The conductive layer is formed using [a specific method], and then the conductive layer is patterned to create the conductive layer. Furthermore, the conductive layer material is selected from Al, Cr, Cu, Ta, Ti, Mo, and W. Elements such as Mn, Mg, Zr, and Be can be used. Materials containing Nd, Sc, or a combination of these may be used. For details, see below. This is similar to the source electrode or drain electrode 142a, etc.

[0198] As described above, a transistor 162 using a highly purified oxide semiconductor layer 144, and The capacitive element 164 is completed. The capacitive element 164 is connected to the source electrode or drain electrode 142a , oxide semiconductor layer 144, first gate insulating layer 146a and second gate insulating layer 146b, It consists of and electrode 148b.

[0199] In addition, in the capacitive element 164 of Figure 7, the oxide semiconductor layer 144 and the first gate insulating layer 146a By laminating the second gate insulating layer 146b with the source electrode or drain electrode, Sufficient insulation can be ensured between electrode 142a and electrode 148b. Of course, To ensure sufficient capacitance, a capacitive element 164 without an oxide semiconductor layer 144 is adopted. It may also be used. Furthermore, a capacitive element having an insulating layer formed similarly to insulating layer 143a. 164 can also be used. Furthermore, if capacitance is not required, the capacitive element 164 can be omitted. It is also possible to do so.

[0200] By using a highly purified and intrinsically purified oxide semiconductor layer 144, the transistor can be turned off. The current can be significantly reduced. And by using such a transistor, A semiconductor device capable of retaining its contents for an extremely long period of time can be obtained.

[0201] Furthermore, in the semiconductor device shown in this embodiment, the wiring is standardized, so the integration density is A sufficiently enhanced semiconductor device is realized. In addition, electrodes 126 and 154 are superimposed. By forming it in this way, the increase in element area caused by the contact region of the electrodes is suppressed, and Further integration will be achieved.

[0202] The configurations and methods described in this embodiment are suitable for use with configurations and methods described in other embodiments. They can be used in any combination.

[0203] (Embodiment 8) The semiconductor devices disclosed herein are applicable to a variety of electronic devices (including amusement machines). This is possible. As an electronic device, for example, a television set (television, or television Receivers (also called receivers), computer monitors, digital cameras, digital video cameras Cameras such as LA, digital photo frames, and mobile phones (also called mobile phones or mobile phone devices). ), portable game consoles, personal digital assistants, audio playback devices, large game machines such as pachinko machines, etc. These are some examples.

[0204] In this embodiment, the gate leakage current obtained in any one of Embodiments 1 to 3 is reduced. An example of an electronic device equipped with a transistor will be explained using Figure 8.

[0205] Figure 8(A) shows a notebook-type personal computer that was fabricated with at least one display device mounted as a component. This is a computer consisting of a main unit 3001, a casing 3002, a display unit 3003, and a keyboard 3 It is composed of 004 ​​and the like. Notebook personal computers have transistors and power-saving display devices. I have it.

[0206] Figure 8(B) shows a portable information terminal (P) manufactured by mounting at least one display device as a component. DA) The main unit 3021 has a display unit 3023 and an external interface 3025, Operation buttons 3024 and other controls are provided. A stylus 3022 is also provided as an accessory for operation. There is also a transistor with low gate leakage current as shown in Embodiment 5, which saves power. The mobile information terminal has an automated display device.

[0207] Figure 8(C) shows a transistor with low gate leakage current as shown in Embodiment 6, and is energy-saving. This is an e-book created by implementing an electronically controlled paper as a single component. Figure 8(C) This shows an example of an e-book. For example, e-book 2700 is a casing 2701 and casing It consists of two housings, 2703. Housings 2701 and 2703 have a shaft portion 27 It is integrated with 11, and can open and close using the shaft portion 2711 as an axis. This configuration makes it possible to operate like a physical book.

[0208] The display unit 2705 is incorporated into the housing 2701, and the display unit 2707 is incorporated into the housing 2703. It is included. Display units 2705 and 2707 are configured to display a continuation screen. Alternatively, a configuration that displays different screens is also acceptable. For example, text is displayed in the display unit on the right (display unit 2705 in Figure 8(C)), and the table on the left... An image can be displayed on the display unit (display unit 2707 in Figure 8(C)).

[0209] Furthermore, Figure 8(C) shows an example in which the housing 2701 is equipped with an operating section, etc. Body 2701 is equipped with a power supply 2721, operation keys 2723, speaker 2725, etc. It is located on the same surface as the display unit of the casing. The page can be turned using operation key 2723. The configuration may also include a keyboard and a pointing device. On the side, there are external connection terminals (earphone jack, USB terminal, or AC adapter and USB terminal). A structure that includes terminals that can connect to various cables such as B cables, a recording medium insertion section, etc. It may also be considered complete. Furthermore, the eBook 2700 has a configuration that gives it the functionality of an electronic dictionary. You may do so.

[0210] Furthermore, the e-book 2700 may be configured to transmit and receive information wirelessly. By wireless means, The system will be configured to allow users to purchase and download desired book data from an e-book server. It is also possible.

[0211] Figure 8(D) shows a transistor with low gate leakage current as shown in Embodiment 5, saving This is a mobile phone manufactured by mounting an electrified display device as a single component, and the casing 2800 and It consists of two enclosures, enclosure 2801 and enclosure 2801. Speaker 2803, microphone 2804, pointing device 2806, It is equipped with a camera lens 2807, an external connection terminal 2808, etc., and the housing 2801 This includes a solar cell 2810 for charging the portable information terminal, and an external memory slot 2811. It is equipped with these features. Furthermore, the antenna is built into the 2801 housing.

[0212] Furthermore, the display panel 2802 is equipped with a touch panel, and as shown in Figure 8(D), it displays video. The multiple operation keys 2805 are shown with dotted lines. Note that the output from the solar cell 2810 A boost circuit is also implemented to increase the voltage from the source voltage to the voltage required for each circuit.

[0213] The display panel 2802 changes its orientation as appropriate depending on the usage mode. Since the camera lens 2807 is mounted on the same plane as the 2802, video calls are possible. Yes. Speaker 2803 and microphone 2804 are not limited to voice calls, but also to video calls. It can record, play back, and more. Furthermore, the casings 2800 and 2801 slide apart. As shown in Figure 8(D), it can be changed from an unfolded state to an overlapping state, making it suitable for carrying. Further miniaturization is possible.

[0214] External connection terminal 2808 can be connected to various cables such as AC adapters and USB cables. It is capable of charging and data communication with personal computers, etc. By inserting a recording medium into memory slot 2811, it becomes possible to store and move larger amounts of data. The semiconductor device shown in Embodiment 6 can be used as the recording medium. Embodiment According to 6, by using a transistor that can sufficiently reduce the off-current, This provides a semiconductor device capable of retaining its contents over a long period of time.

[0215] Furthermore, in addition to the above functions, it is equipped with infrared communication functions, television reception functions, etc. That's good too.

[0216] Figure 8(E) shows a transistor with low gate leakage current as shown in Embodiment 5, which saves power. This digital camera was manufactured by mounting an automated display device as a single component, and the main body 305 1. Display unit (A) 3057, eyepiece unit 3053, operation switch 3054, display unit (B) 30 It consists of components such as battery 3056 and 55.

[0217] This embodiment can be freely combined with any one of embodiments 1 to 6. [Explanation of Symbols]

[0218] 100 circuit boards 106 Element isolation insulating layer 108 Gate Insulation Layer 110 Guard Station 116 Channel formation region 120 Impurity region 124 Metal compound area 126 electrode 128 Insulating layer 130 Insulating layer 142a Drain electrode 142b Drain electrode 143a Insulating layer 143b Insulating layer 144 Oxide semiconductor layer 146a Gate insulating layer 146b Gate insulating layer 148a Token 148b Electrode 150 Insulating layer 152 Insulating layer 154 Electrode 156 Wiring 160 transistors 162 transistors 164 Capacitive elements 301 Chamber 302 Electrode 303 Electrode 304 RF power supply 305 substrate 306 Shutter 307 Holder 308 Target 400 circuit boards 401 Gate Shutdown 402a First gate insulating layer 402b Second gate insulating layer 403 Oxide semiconductor layer 405a Source electrode 405b Drain electrode 407 Insulating film 409 Protective insulating layer 410 transistors 420 transistors 427 Insulating layer 430 transistors 436a Wiring layer 436b wiring layer 437 Insulating layer 440 transistors 505 circuit board 506 Protective insulating layer 507a Gate Insulation Layer 507b Gate Insulation Layer 510 transistors 511 Guard Station 515a Source electrode 515b Drain electrode 516 Insulating layer 520 transistors 526 Insulating layer 530 Oxide semiconductor film 531 Oxide semiconductor layer 580 circuit boards 581 transistors 582a Gate Insulation Layer 582b Gate Insulation Layer 583 Insulating layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 590a black area 590b White area 595 Filling material 2700 eBooks 2701 enclosure 2703 Casing 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation Keys 2725 Speaker 2800 cabinets 2801 enclosure 2802 Display Panel 2803 Speaker 2804 Microphone 2805 Operation Keys 2806 Pointing device 2807 Camera Lens 2808 External connection terminal 2810 solar cells 2811 External memory slot 3001 Main Unit 3002 enclosure 3003 Display section 3004 Keyboard 3021 Main Unit 3022 Stylus 3023 Display section 3024 Operation Buttons 3025 External Interface 3051 Main Unit 3053 Eyepiece 3054 Operation switch 3055 Display section (B) 3056 Battery 3057 Display section (A) 4001 circuit board 4002 pixel section 4003 Signal Line Drive Circuit 4004 Scan Line Drive Circuit 4005 Sealant 4006 circuit board 4008 Liquid Crystal Layer 4010 Transistor 4011 Transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020a Gate Insulation Layer 4020b Gate Insulation Layer 4021 Insulating layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulating layer 4040 conductive layer 4041 Insulating layer 4042 Insulating layer

Claims

1. The device comprises a first transistor having silicon in its first channel formation region, and a second transistor having an oxide semiconductor containing indium, gallium, and zinc in its second channel formation region. The source electrode or drain electrode of the second transistor is electrically connected to the gate electrode of the first transistor. The source electrode or the other of the drain electrode of the second transistor is electrically connected to the first channel formation region of the first transistor, in a semiconductor device. A first conductive layer having a region positioned higher than the upper surface of the first channel forming region and functioning as the gate electrode of the first transistor, An oxide semiconductor layer having a region positioned higher than the upper surface of the first conductive layer and having the second channel-forming region, A second conductive layer having a region positioned higher than the upper surface of the first conductive layer, and having the function of either the source electrode or the drain electrode of the second transistor, A third conductive layer having a region positioned higher than the upper surface of the first conductive layer and functioning as the other of the source electrode or drain electrode of the second transistor, The present invention comprises a fourth conductive layer positioned higher than the upper surface of the second channel formation region, having a region that overlaps with the second channel formation region, and functioning as the gate electrode of the second transistor, The fourth conductive layer does not have a region that overlaps with the channel formation region of the first transistor. A semiconductor device wherein, in a plan view, the maximum length of the second conductive layer in the channel length direction of the second transistor is greater than the maximum length of the second conductive layer in the channel width direction of the second transistor.

2. The device comprises a first transistor having silicon in its first channel formation region, and a second transistor having an oxide semiconductor containing indium, gallium, and zinc in its second channel formation region. The source electrode or drain electrode of the second transistor is electrically connected to the gate electrode of the first transistor. The source electrode or the other of the drain electrode of the second transistor is electrically connected to the first channel formation region of the first transistor, in a semiconductor device. A first conductive layer having a region positioned above the first channel forming region and functioning as the gate electrode of the first transistor, A first insulating layer having a region in contact with the side surface of the first conductive layer, An oxide semiconductor layer having a region positioned above the first insulating layer and having the second channel-forming region, A second conductive layer having a region positioned above the first insulating layer and functioning as either the source electrode or the drain electrode of the second transistor, A third conductive layer having a region positioned above the first insulating layer and functioning as the other of the source electrode or drain electrode of the second transistor, A fourth conductive layer is provided, which is located above the second channel formation region, has a region that overlaps with the second channel formation region, and functions as the gate electrode of the second transistor. The fourth conductive layer does not have a region that overlaps with the channel formation region of the first transistor. A semiconductor device wherein, in a plan view, the maximum length of the second conductive layer in the channel length direction of the second transistor is greater than the maximum length of the second conductive layer in the channel width direction of the second transistor.

3. The device comprises a first transistor having silicon in its first channel formation region, and a second transistor having an oxide semiconductor containing indium, gallium, and zinc in its second channel formation region. The source electrode or drain electrode of the second transistor is electrically connected to the gate electrode of the first transistor. The source electrode or the other of the drain electrode of the second transistor is electrically connected to the first channel formation region of the first transistor, in a semiconductor device. A first conductive layer having a region positioned higher than the upper surface of the first channel forming region and functioning as the gate electrode of the first transistor, An oxide semiconductor layer having a region positioned higher than the upper surface of the first conductive layer and having the second channel-forming region, A second conductive layer having a region positioned higher than the upper surface of the first conductive layer, and having the function of either the source electrode or the drain electrode of the second transistor, A third conductive layer having a region positioned higher than the upper surface of the first conductive layer and functioning as the other of the source electrode or drain electrode of the second transistor, A fourth conductive layer is positioned lower than the lower surface of the second channel formation region, has a region that overlaps with the second channel formation region, and functions as the first gate electrode of the second transistor. The fifth conductive layer is positioned higher than the upper surface of the second channel formation region, has a region that overlaps with the second channel formation region, and functions as the second gate electrode of the second transistor. The fifth conductive layer does not have a region that overlaps with the channel formation region of the first transistor. A semiconductor device wherein, in a plan view, the maximum length of the second conductive layer in the channel length direction of the second transistor is greater than the maximum length of the second conductive layer in the channel width direction of the second transistor.

4. The device comprises a first transistor having silicon in its first channel formation region, and a second transistor having an oxide semiconductor containing indium, gallium, and zinc in its second channel formation region. The source electrode or drain electrode of the second transistor is electrically connected to the gate electrode of the first transistor. The source electrode or the other of the drain electrode of the second transistor is electrically connected to the first channel formation region of the first transistor, in a semiconductor device. A first conductive layer having a region positioned above the first channel forming region and functioning as the gate electrode of the first transistor, A first insulating layer having a region in contact with the side surface of the first conductive layer, An oxide semiconductor layer having a region positioned above the first insulating layer and having the second channel-forming region, A second conductive layer having a region positioned above the first insulating layer and functioning as either the source electrode or the drain electrode of the second transistor, A third conductive layer having a region positioned above the first insulating layer and functioning as the other of the source electrode or drain electrode of the second transistor, A fourth conductive layer is located below the second channel formation region, has a region that overlaps with the second channel formation region, and functions as the first gate electrode of the second transistor. The present invention comprises a fifth conductive layer positioned above the second channel formation region, having a region that overlaps with the second channel formation region, and functioning as the second gate electrode of the second transistor, The fifth conductive layer does not have a region that overlaps with the channel formation region of the first transistor. A semiconductor device wherein, in a plan view, the maximum length of the second conductive layer in the channel length direction of the second transistor is greater than the maximum length of the second conductive layer in the channel width direction of the second transistor.

5. The device comprises a first transistor having silicon in its first channel formation region, a second transistor having an oxide semiconductor containing indium, gallium, and zinc in its second channel formation region, and a capacitive element. The source electrode or drain electrode of the second transistor is electrically connected to the gate electrode of the first transistor. The source electrode or the other of the drain electrode of the second transistor is electrically connected to the first channel formation region of the first transistor, in a semiconductor device. A first conductive layer having a region positioned higher than the upper surface of the first channel forming region and functioning as the gate electrode of the first transistor, An oxide semiconductor layer having a region positioned higher than the upper surface of the first conductive layer and having the second channel-forming region, A second conductive layer having a region positioned higher than the upper surface of the first conductive layer, and having the function of either the source electrode or the drain electrode of the second transistor, and the function of one electrode of the capacitive element, A third conductive layer having a region positioned higher than the upper surface of the first conductive layer and functioning as the other of the source electrode or drain electrode of the second transistor, A fourth conductive layer having a region positioned higher than the upper surface of the second conductive layer and a region overlapping with the second conductive layer, and functioning as the other electrode of the capacitive element, The present invention comprises a fifth conductive layer positioned higher than the upper surface of the second channel formation region, having a region that overlaps with the second channel formation region, and functioning as the gate electrode of the second transistor, The fourth conductive layer has a region that overlaps with the first conductive layer, The fifth conductive layer does not have a region that overlaps with the channel formation region of the first transistor. A semiconductor device wherein, in a plan view, the length of the second conductive layer in the channel length direction of the second transistor is greater than the length of the second conductive layer in the channel width direction of the second transistor.

6. The device comprises a first transistor having silicon in its first channel formation region, a second transistor having an oxide semiconductor containing indium, gallium, and zinc in its second channel formation region, and a capacitive element. The source electrode or drain electrode of the second transistor is electrically connected to the gate electrode of the first transistor. The source electrode or the other of the drain electrode of the second transistor is electrically connected to the first channel formation region of the first transistor, in a semiconductor device. A first conductive layer having a region positioned above the first channel forming region and functioning as the gate electrode of the first transistor, A first insulating layer having a region in contact with the side surface of the first conductive layer, An oxide semiconductor layer having a region positioned above the first insulating layer and having the second channel-forming region, A second conductive layer having a region positioned above the first insulating layer, and having the function of either the source electrode or the drain electrode of the second transistor, and the function of one electrode of the capacitive element, A third conductive layer having a region positioned above the first insulating layer and functioning as the other of the source electrode or drain electrode of the second transistor, A fourth conductive layer having a region positioned above the second conductive layer and a region overlapping the second conductive layer, and functioning as the other electrode of the capacitive element, The present invention comprises a fifth conductive layer positioned higher than the upper surface of the second channel formation region, having a region that overlaps with the second channel formation region, and functioning as the gate electrode of the second transistor, The fourth conductive layer has a region that overlaps with the first conductive layer, The fifth conductive layer does not have a region that overlaps with the channel formation region of the first transistor. A semiconductor device wherein, in a plan view, the maximum length of the second conductive layer in the channel length direction of the second transistor is greater than the maximum length of the second conductive layer in the channel width direction of the second transistor.

7. The device comprises a first transistor having silicon in its first channel formation region, a second transistor having an oxide semiconductor containing indium, gallium, and zinc in its second channel formation region, and a capacitive element. The source electrode or drain electrode of the second transistor is electrically connected to the gate electrode of the first transistor. The source electrode or the other of the drain electrode of the second transistor is electrically connected to the first channel formation region of the first transistor, in a semiconductor device. A first conductive layer having a region positioned higher than the upper surface of the first channel forming region and functioning as the gate electrode of the first transistor, An oxide semiconductor layer having a region positioned higher than the upper surface of the first conductive layer and having the second channel-forming region, A second conductive layer having a region positioned higher than the upper surface of the first conductive layer, and having the function of either the source electrode or the drain electrode of the second transistor, and the function of one electrode of the capacitive element, A third conductive layer having a region positioned higher than the upper surface of the first conductive layer and functioning as the other of the source electrode or drain electrode of the second transistor, A fourth conductive layer having a region positioned higher than the upper surface of the second conductive layer and a region overlapping with the second conductive layer, and functioning as the other electrode of the capacitive element, A fifth conductive layer is positioned lower than the lower surface of the second channel formation region, has a region that overlaps with the second channel formation region, and functions as the first gate electrode of the second transistor. The present invention comprises a sixth conductive layer positioned higher than the upper surface of the second channel formation region, having a region that overlaps with the second channel formation region, and functioning as the second gate electrode of the second transistor, The fourth conductive layer has a region that overlaps with the first conductive layer, The sixth conductive layer does not have a region that overlaps with the channel formation region of the first transistor. A semiconductor device wherein, in a plan view, the maximum length of the second conductive layer in the channel length direction of the second transistor is greater than the maximum length of the second conductive layer in the channel width direction of the second transistor.

8. The device comprises a first transistor having silicon in its first channel formation region, a second transistor having an oxide semiconductor containing indium, gallium, and zinc in its second channel formation region, and a capacitive element. The source electrode or drain electrode of the second transistor is electrically connected to the gate electrode of the first transistor. The source electrode or the other of the drain electrode of the second transistor is electrically connected to the first channel formation region of the first transistor, in a semiconductor device. A first conductive layer having a region positioned above the first channel forming region and functioning as the gate electrode of the first transistor, A first insulating layer having a region in contact with the side surface of the first conductive layer, An oxide semiconductor layer having a region positioned above the first insulating layer and having the second channel-forming region, A second conductive layer having a region positioned above the first insulating layer, and having the function of either the source electrode or the drain electrode of the second transistor, and the function of one electrode of the capacitive element, A third conductive layer having a region positioned above the first insulating layer and functioning as the other of the source electrode or drain electrode of the second transistor, A fourth conductive layer having a region positioned above the second conductive layer and a region overlapping the second conductive layer, and functioning as the other electrode of the capacitive element, A fifth conductive layer is located below the second channel formation region, has a region that overlaps with the second channel formation region, and functions as the first gate electrode of the second transistor. A sixth conductive layer is provided, which is located above the second channel formation region, has a region that overlaps with the second channel formation region, and functions as the second gate electrode of the second transistor. The fourth conductive layer has a region that overlaps with the first conductive layer, The sixth conductive layer does not have a region that overlaps with the channel formation region of the first transistor. A semiconductor device wherein, in a plan view, the maximum length of the second conductive layer in the channel length direction of the second transistor is greater than the maximum length of the second conductive layer in the channel width direction of the second transistor.

9. In claim 1, The present invention comprises a fifth conductive layer positioned higher than the upper surface of the second conductive layer and having a region that overlaps with the second conductive layer, The semiconductor device wherein the fifth conductive layer has a region that overlaps with the third conductive layer.

10. In claim 2, The present invention comprises a fifth conductive layer disposed above the second conductive layer and having a region that overlaps with the second conductive layer, The semiconductor device wherein the fifth conductive layer has a region that overlaps with the third conductive layer.

11. In claim 3, The present invention comprises a sixth conductive layer positioned higher than the upper surface of the second conductive layer and having a region that overlaps with the second conductive layer, The semiconductor device wherein the sixth conductive layer has a region that overlaps with the third conductive layer.

12. In claim 4, The present invention comprises a sixth conductive layer disposed above the second conductive layer and having a region that overlaps with the second conductive layer, The semiconductor device wherein the sixth conductive layer has a region that overlaps with the third conductive layer.

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