SiC semiconductor device

Abstract

To provide a SiC semiconductor device that can reduce the impact on SiC semiconductor chips caused by the modified layer. [Solution] The SiC semiconductor device 1 includes a SiC semiconductor layer 2 having a first main surface 3 as a device surface, a second main surface 4 opposite to the first main surface 3, a first side surface 5A facing the a-face of the SiC single crystal, and a second side surface 5B facing the m-face of the SiC single crystal, a first modified layer 22A formed on the first side surface 5A of the SiC semiconductor layer 2 with a first occupancy ratio and modified to have properties different from the SiC single crystal, and a second modified layer formed on the second side surface 5B of the SiC semiconductor layer 2 with a second occupancy ratio less than the first occupancy ratio and modified to have properties different from the SiC single crystal.

Description

Technical Field

[0001] This disclosure relates to a SiC semiconductor device.

Background Art

[0002] In recent years, a method for processing a SiC semiconductor wafer called the stealth dicing method has attracted attention. In the stealth dicing method, after a laser beam is selectively irradiated onto a SiC semiconductor wafer, the SiC semiconductor wafer is cut along the portion irradiated with the laser beam. According to this method, since a SiC semiconductor wafer having a relatively high hardness can be cut without using a cutting member such as a dicing blade, the manufacturing time can be shortened.

[0003] Patent Document 1 discloses a method for manufacturing a SiC semiconductor device using the stealth dicing method. In the manufacturing method of Patent Document ①, a plurality of SiC semiconductor layers are cut out from a SiC semiconductor wafer having a predetermined off-angle. Two side surfaces facing the a-plane of the SiC single crystal in the SiC semiconductor layer are inclined surfaces along the c-axis of the SiC single crystal.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0005] [[ID=②]] [Summary] The SiC semiconductor device is mounted on a connection object such as a lead frame or a mounting substrate using a semiconductor assembly device. The transfer process of the SiC semiconductor device in the semiconductor assembly device is performed, for example, by a pickup nozzle that adsorbs and holds the main surface of the SiC semiconductor layer.

[0006] Note: There seems to be a typo in the original text where "特許文献1の製造方法では、所定のオフ角を有するSiC半導体ウエハから複数のSiC半導体層が切り出される。SiC半導体層においてSiC単結晶のa面に面する2つ側面は、SiC単結晶のc軸に沿う傾斜面となる。" in ID=16 has a "①" in the translated text which should be "1". Also, the "②" in ID=32 should be "32". These are corrected in the translation.When a SiC semiconductor device according to Patent Document 1 is brought into a semiconductor assembly apparatus, there is a risk that the suction by the pickup nozzle will be hindered by the inclined surface of the SiC semiconductor layer. In this case, the pickup nozzle will not be able to properly hold the SiC semiconductor device, resulting in a pickup error.

[0007] Furthermore, the modified layer is formed by modifying the SiC single crystal to have other properties. Therefore, considering the impact of the modified layer on the SiC semiconductor chip (SiC semiconductor layer), it is not desirable for multiple modified layers to be formed across the entire side surface of the SiC semiconductor chip. Examples of the impact of the modified layer on the SiC semiconductor chip include fluctuations in the electrical properties of the SiC semiconductor chip caused by the modified layer, and the generation of cracks in the SiC semiconductor chip originating from the modified layer.

[0008] One embodiment provides a SiC semiconductor device that can suppress pickup errors in semiconductor assembly equipment. Another embodiment provides a SiC semiconductor device that can reduce the impact on SiC semiconductor chips caused by the modified layer.

[0009] One embodiment provides a SiC semiconductor device that includes a hexagonal SiC single crystal, a first main surface as an element forming surface facing the c-face of the SiC single crystal and having an off-angle inclined with respect to the c-face, a second main surface opposite to the first main surface, and a SiC semiconductor layer facing the a-face of the SiC single crystal and having a side surface that, when the normal to the first main surface is 0°, has an angle less than the off-angle with respect to the normal.

[0010] This SiC semiconductor device can suppress pickup errors in semiconductor assembly equipment.

[0011] One embodiment provides a SiC semiconductor device that includes a hexagonal SiC single crystal, a first main surface as an element formation surface facing the c-plane of the SiC single crystal and having an off-angle inclined with respect to the c-plane, a second main surface opposite to the first main surface, and a SiC semiconductor layer facing the a-plane of the SiC single crystal and having a sloping portion inclined from the normal to the first main surface in a direction opposite to the c-axis of the SiC single crystal.

[0012] This SiC semiconductor device reduces the area where a sloping surface extending along the c-axis is formed on the side surface of the SiC semiconductor layer by using a sloping portion that is inclined in the direction opposite to the c-axis. This suppresses pickup errors in semiconductor assembly equipment.

[0013] One embodiment provides a SiC semiconductor device having a stacked structure including a SiC semiconductor substrate and a SiC epitaxial layer, comprising: a SiC semiconductor layer made of the SiC epitaxial layer having an element formation surface with an off-angle introduced that is inclined in the off-direction with respect to the c-plane of a SiC single crystal, and a SiC semiconductor layer having a side surface that extends in a direction orthogonal to the off-direction and is inclined at an angle less than the off-angle with respect to the normal to the element formation surface when the normal to the normal is set to 0°; and a plurality of modified layers formed at intervals in the thickness direction on the portion made of the SiC semiconductor substrate on the side surface so as to expose the SiC epitaxial layer, and modified to have properties different from the SiC semiconductor substrate.

[0014] This SiC semiconductor device can suppress pickup errors in semiconductor assembly equipment. Furthermore, it can reduce the impact of the modified layer on the SiC semiconductor chip.

[0015] One embodiment provides a SiC semiconductor device comprising: a SiC chip having a first main surface on one side, a second main surface and a side surface on the other side; a semiconductor region of a first conductivity type formed on the surface layer of the first main surface so as to be exposed from the first main surface and the side surface; a pn connection region formed on the surface layer of the first main surface at the periphery of the first main surface; an impurity region of a second conductivity type formed on the surface layer of the semiconductor region at the periphery of the first main surface and forming the semiconductor region and the pn connection region; and modified lines formed on the side surface at intervals from the depth position of the pn connection region toward the second main surface, which are modified to have properties different from SiC. The modified lines may be formed on the side surface at intervals from each other toward the second main surface at the depth position of the bottom of the semiconductor region.

[0016] One embodiment provides a SiC semiconductor device comprising: a SiC chip having a first main surface on one side, a second main surface and a side surface on the other side; an epitaxial layer which is a semiconductor region of a first conductivity type formed on the surface of the first main surface so as to be exposed from the first main surface and the side surface; a pn connection region formed on the surface of the first main surface at the periphery of the first main surface; an impurity region of a second conductivity type formed on the surface of the epitaxial layer at the periphery of the first main surface and forming the pn connection region with the epitaxial layer; and a plurality of modified lines formed on the side surface which are modified to have properties different from those of a SiC single crystal. The plurality of modified lines may have different thicknesses with respect to the normal direction of the first main surface. The plurality of modified lines may be formed on the side surface from a depth position at the bottom of the epitaxial layer toward the second main surface. [Brief explanation of the drawing]

[0017] [Figure 1] Figure 1 shows a unit cell of a 4H-SiC single crystal applied to an embodiment of the present disclosure. [Figure 2] Figure 2 is a plan view showing the silicon plane of the unit cell of the 4H-SiC single crystal shown in Figure 1. [Figure 3]Figure 3 is a perspective view of a SiC semiconductor device according to the first embodiment of this disclosure, viewed from one angle, and shows a first example of a modification line. [Figure 4] Figure 4 is a perspective view of the SiC semiconductor device shown in Figure 3, viewed from a different angle. [Figure 5] Figure 5 is an enlarged view of region V shown in Figure 3. [Figure 6] Figure 6 is an enlarged view of region VI shown in Figure 3. [Figure 7] Figure 7 is a plan view of the SiC semiconductor device shown in Figure 3. [Figure 8] Figure 8 is a cross-sectional view along the line VIII-VIII shown in Figure 7. [Figure 9] Figure 9 is a perspective view showing a SiC semiconductor wafer used in the manufacture of the SiC semiconductor device shown in Figure 3. [Figure 10A] Figure 10A is a cross-sectional view showing an example of a manufacturing method for the SiC semiconductor device shown in Figure 3. [Figure 10B] Figure 10B shows the process after Figure 10A. [Figure 10C] Figure 10C shows the process after Figure 10B. [Figure 10D] Figure 10D shows the process after Figure 10C. [Figure 10E] Figure 10E shows the process after Figure 10D. [Figure 10F] Figure 10F shows the process after Figure 10E. [Figure 10G] Figure 10G shows the process after Figure 10F. [Figure 10H] Figure 10H shows the process after Figure 10G. [Figure 10I] Figure 10I shows the process after Figure 10H. [Figure 10J] Figure 10J shows the process after Figure 10I. [Figure 10K] Figure 10K shows the process after Figure 10J. [Figure 10L] Figure 10L shows the process after Figure 10K. [Figure 10M] Figure 10M shows the process after Figure 10L. [Figure 11] Figure 11 is a perspective view showing a semiconductor package incorporating the SiC semiconductor device shown in Figure 3, seen through the sealing resin. [Figure 12] Figure 12 is a perspective view showing the transport state of the SiC semiconductor device shown in Figure 3. [Figure 13] Figure 13 is a diagram illustrating the structure of a SiC semiconductor device as an example. [Figure 14A] Figure 14A is a perspective view showing the SiC semiconductor device shown in Figure 3, and is a perspective view showing a second example of the modification line. [Figure 14B] Figure 14B is a perspective view showing the SiC semiconductor device shown in Figure 3, and is a perspective view showing a third embodiment of the modification line. [Figure 14C] Figure 14C is a perspective view showing the SiC semiconductor device shown in Figure 3, and is a perspective view showing a fourth embodiment of the modification line. [Figure 14D] Figure 14D is a perspective view showing the SiC semiconductor device shown in Figure 3, and is a perspective view showing a fifth example of the modification line. [Figure 15] Figure 15 is a perspective view showing a SiC semiconductor device according to a second embodiment of the present disclosure, and is a perspective view showing a structure to which the modification line according to the first embodiment is applied. [Figure 16] Figure 16 is a perspective view of a SiC semiconductor device according to the third embodiment of this disclosure, viewed from one angle, and shows a structure to which the modification line according to the first embodiment is applied. [Figure 17] Figure 17 is a perspective view of the SiC semiconductor device shown in Figure 16, viewed from a different angle. [Figure 18] Figure 18 is a plan view showing the SiC semiconductor device shown in Figure 16. [Figure 19] Figure 19 is a plan view obtained by removing the resin layer from Figure 18. [Figure 20] Figure 20 is an enlarged view of region XX shown in Figure 19, and is a diagram illustrating the structure of the first main surface of the SiC semiconductor layer. [Figure 21] Figure 21 is a cross-sectional view along the line XXI-XXI shown in Figure 20. [Figure 22] Figure 22 is a cross-sectional view along the line XXII-XXII shown in Figure 20. [Figure 23] Figure 23 is an enlarged view of region XXIII shown in Figure 21. [Figure 24] Figure 24 is a cross-sectional view along the line XXIV-XXIV shown in Figure 19. [Figure 25] Figure 25 is an enlarged view of region XXV shown in Figure 24. [Figure 26] Figure 26 is a graph illustrating sheet resistance. [Figure 27] Figure 27 is an enlarged view of the region corresponding to Figure 20, and shows an enlarged view of a SiC semiconductor device according to the fourth embodiment of this disclosure. [Figure 28] Figure 28 is a cross-sectional view along the line XXVIII-XXVIII shown in Figure 27. [Figure 29] Figure 29 is an enlarged view of the region corresponding to Figure 23, and shows an enlarged view of a SiC semiconductor device according to the fifth embodiment of this disclosure. [Figure 30] Figure 30 is an enlarged view of the region corresponding to Figure 20, and is an enlarged view showing a SiC semiconductor device according to the sixth embodiment of this disclosure.

[0018] [Detailed explanation] Embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0019] In embodiments of this disclosure, a hexagonal silicon carbide (SiC) single crystal is used. Hexagonal SiC single crystals have multiple polytypes, including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, and 6H-SiC single crystals, depending on the period of the atomic arrangement. While embodiments of this disclosure describe an example in which a 4H-SiC single crystal is used, other polytypes are not excluded from this disclosure.

[0020] The crystal structure of the 4H-SiC single crystal will be described below. Figure 1 shows a unit cell (hereinafter simply referred to as "unit cell") of a 4H-SiC single crystal applied to the embodiment of this disclosure. Figure 2 is a plan view showing the silicon plane of the unit cell shown in Figure 1.

[0021] Referring to Figures 1 and 2, the unit cell contains a tetrahedral structure in which four carbon atoms are bonded to one silicon atom in a tetrahedral arrangement (regular tetrahedral arrangement). The unit cell has an atomic arrangement in which four tetrahedral structures are stacked in a periodic manner. The unit cell has a regular hexagonal silicon face, a regular hexagonal carbon face, and a hexagonal prism structure having six sides connecting the silicon face and the carbon face.

[0022] A silicon plane is a terminal plane terminated by Si atoms. In a silicon plane, one Si atom is located at each of the six vertices of a regular hexagon, and one Si atom is located at the center of the regular hexagon.

[0023] A carbon plane is a terminal plane terminated by carbon atoms. In a carbon plane, one carbon atom is located at each of the six vertices of a regular hexagon, and one carbon atom is located at the center of the hexagon.

[0024] The crystal planes of a unit cell are defined by four coordinate axes (a1, a2, a3, c), including the a1, a2, a3, and c axes. The value of a3 among the four coordinate axes is -(a1+a2). Below, the crystal planes of a 4H-SiC single crystal will be described using the silicon plane as an example of a hexagonal end plane.

[0025] The a1, a2, and a3 axes are set in a plan view of the silicon surface from the c axis, with respect to the centrally located Si atom, and are aligned along the direction of the arrangement of the nearest Si atoms (hereinafter simply referred to as the "nearest-neighbor direction"). The a1, a2, and a3 axes are set with angles shifted by 120° each, following the arrangement of Si atoms.

[0026] The c-axis is set in the direction normal to the silicon plane, with the central Si atom as the reference point. The silicon plane is the (0001) plane. The carbon plane is the (000-1) plane.

[0027] The sides of the hexagonal prism contain six crystal planes aligned with the nearest-neighbor atomic direction in a plan view of the silicon plane viewed from the c-axis. More specifically, the sides of the hexagonal prism contain six crystal planes each containing two nearest-neighbor Si atoms in a plan view of the silicon plane viewed from the c-axis.

[0028] The sides of the hexagonal prism, in a plan view with the silicon surface viewed from the c-axis, include the (1-100) face, (0-110) face, (-1010) face, (-1100) face, (01-10) face, and (10-10) face, starting clockwise from the tip of the a1 axis.

[0029] The diagonal faces of a hexagonal prism, when viewed from the c-axis across the silicon plane, contain six crystal planes that intersect with the nearest-neighbor directions. More specifically, the diagonal faces of the hexagonal prism contain six crystal planes, each containing two non-neighboring Si atoms, when viewed from the c-axis across the silicon plane. When viewed with respect to the central Si atom, the intersecting directions of the nearest-neighbor directions become orthogonal directions perpendicular to the nearest-neighbor directions.

[0030] The diagonal faces of the hexagonal prism, in a plan view with the silicon face viewed from the c-axis, include the (11-20) face, the (1-210) face, the (-2110) face, the (-1-120) face, the (-12-10) face, and the (2-1-10) face.

[0031] The crystal orientation of a unit cell is defined by the normal direction of the crystal plane. The normal direction of the (1-100) plane is [1-100]. The normal direction of the (0-110) plane is [0-110]. The normal direction of the (-1010) plane is [-1010]. The normal direction of the (-1100) plane is [-1100]. The normal direction of the (01-10) plane is [01-10]. The normal direction of the (10-10) plane is [10-10].

[0032] The normal direction of the (11-20) plane is in the [11-20] direction. The normal direction of the (1-210) plane is in the [1-210] direction. The normal direction of the (-2110) plane is in the [-2110] direction. The normal direction of the (-1-120) plane is in the [-1-120] direction. The normal direction of the (-12-10) plane is in the [-12-10] direction. The normal direction of the (2-1-10) plane is in the [2-1-10] direction.

[0033] Hexagonal crystals are symmetrical six times, with equivalent crystal planes and crystal directions existing at 60° intervals. For example, the (1-100) plane, (0-110) plane, (-1010) plane, (-1100) plane, (01-10) plane, and (10-10) plane form equivalent crystal planes.

[0034] Furthermore, the [1-100], [0-110], [-1010], [-1100], [01-10], and [10-10] directions form equivalent crystal directions. Additionally, the [11-20], [1-210], [-2110], [-1-120], [-12-10], and [2-1-10] directions form equivalent crystal directions.

[0035] The c-axis is in the

[0001] direction ([000-1] direction). The a1-axis is in the [2-1-10] direction ([-2110] direction). The a2-axis is in the [-12-10] direction ([1-210] direction). The a3-axis is in the [-1-120] direction ([11-20] direction).

[0036] The (0001) plane and the (000-1) plane are collectively referred to as the c plane. The

[0001] direction and the [000-1] direction are collectively referred to as the c-axis direction. The (11-20) plane and the (-1-120) plane are collectively referred to as the a plane. The [11-20] direction and the [-1-120] direction are collectively referred to as the a-axis direction. The (1-100) plane and the (-1100) plane are collectively referred to as the m plane. The [1-100] direction and the [-1100] direction are collectively referred to as the m-axis direction.

[0037] Figure 3 is a perspective view of the SiC semiconductor device 1 according to the first embodiment of this disclosure, viewed from one angle, and shows a first embodiment example of modification lines 22A to 22D. Figure 4 is a perspective view of the SiC semiconductor device 1 shown in Figure 3, viewed from a different angle.

[0038] Figure 5 is an enlarged view of region V shown in Figure 3. Figure 6 is an enlarged view of region VI shown in Figure 3. Figure 7 is a plan view of the SiC semiconductor device 1 shown in Figure 3. Figure 8 is a cross-sectional view along the line VIII-VIII shown in Figure 7.

[0039] Referring to Figures 3 to 8, the SiC semiconductor device 1 includes a SiC semiconductor layer 2. The SiC semiconductor layer 2 includes a 4H-SiC single crystal, which is an example of a hexagonal SiC single crystal. The SiC semiconductor layer 2 is formed in the shape of a rectangular parallelepiped chip.

[0040] The SiC semiconductor layer 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and sides 5A, 5B, 5C, and 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrilateral shape (square in this form) when viewed from their normal direction Z in a plan view (hereinafter simply referred to as "plan view").

[0041] The first main surface 3 is the element formation surface on which the semiconductor element is formed. The second main surface 4 of the SiC semiconductor layer 2 consists of a ground surface with grinding marks. The sides 5A to 5D each consist of smooth cleavage planes facing the crystal plane of the SiC single crystal. Sides 5A to 5D do not have grinding marks.

[0042] The thickness TL of the SiC semiconductor layer 2 may be 40 μm or more and 200 μm or less. The thickness TL may be 40 μm or more and 60 μm or less, 60 μm or more and 80 μm or less, 80 μm or more and 100 μm or less, 100 μm or more and 120 μm or less, 120 μm or more and 140 μm or less, 140 μm or more and 160 μm or less, 160 μm or more and 180 μm or less, or 180 μm or more and 200 μm or less. Preferably, the thickness TL is 60 μm or more and 150 μm or less.

[0043] In this configuration, the first principal surface 3 and the second principal surface 4 face the c-plane of the SiC single crystal. The first principal surface 3 faces the (0001) plane (silicon plane). The second principal surface 4 faces the (000-1) plane (carbon plane) of the SiC single crystal.

[0044] The first principal surface 3 and the second principal surface 4 have an off-angle θ that is inclined at an angle of 10° or less in the [11-20] direction (off-direction) with respect to the c-plane of the SiC single crystal. The normal direction Z is inclined by the off-angle θ with respect to the c-axis (

[0001] direction) of the SiC single crystal.

[0045] The off-angle θ may be between 0° and 5.0°. The off-angle θ may be set within the range of angles between 0° and 1.0°, 1.0° and 1.5°, 1.5° and 2.0°, 2.0° and 2.5°, 2.5° and 3.0°, 3.0° and 3.5°, 3.5° and 4.0°, 4.0° and 4.5°, or 4.5° and 5.0°. It is preferable that the off-angle θ is greater than 0°. The off-angle θ may be less than 4.0°.

[0046] The off-angle θ may be set to an angle range of 3.0° or more and 4.5° or less. In this case, it is preferable that the off-angle θ is set to an angle range of 3.0° or more and 3.5° or less and 3.5° or more and 4.0° or less.

[0047] The off-angle θ may be set to an angle range of 1.5° or more and 3.0° or less. In this case, it is preferable that the off-angle θ is set to an angle range of 1.5° or more and 2.0° or more and 2.5° or less.

[0048] The lengths of sides 5A to 5D may be between 0.5 mm and 10 mm, respectively. In this configuration, the surface areas of sides 5A to 5D are equal to each other. When the first main surface 3 and the second main surface 4 are formed in a rectangular shape in plan view, the surface areas of sides 5A and 5C may be less than or greater than the surface areas of sides 5B and 5D.

[0049] In this embodiment, sides 5A and 5C extend along the first direction X and face each other in the second direction Y which intersects the first direction X. Sides 5B and 5D extend along the second direction Y and face each other in the first direction X. More specifically, the second direction Y is the direction perpendicular to the first direction X.

[0050] In this configuration, the first direction X is set to the m-axis direction ([1-100] direction) of the SiC single crystal. The second direction Y is set to the a-axis direction ([11-20] direction) of the SiC single crystal.

[0051] Sides 5A and 5C are formed by the a-planes of the SiC single crystal and face each other in the a-axis direction. Side 5A is formed by the (-1-120) plane of the SiC single crystal. Side 5C is formed by the (11-20) plane of the SiC single crystal.

[0052] Sides 5B and 5D are formed by the m-planes of the SiC single crystal and face each other in the m-axis direction. Side 5B is formed by the (-1100) plane of the SiC single crystal. Side 5D is formed by the (1-100) plane of the SiC single crystal.

[0053] Sides 5A and 5C have an angle θa (θa < θ) less than the off-angle θ with respect to the normal to the first main surface 3 of the SiC semiconductor layer 2, when the normal to the first main surface 3 of the SiC semiconductor layer 2 is set to 0°.

[0054] More specifically, the angle θa is greater than or equal to 0° and less than the off-angle θ (0° ≤ θa < θ). The angle θa may also be defined as the angle formed between the line connecting the peripheral points of the first principal surface 3 and the peripheral points of the second principal surface 4 in a cross-sectional view and the normal of the first principal surface 3.

[0055] On the other hand, sides 5B and 5D extend planarly along the normal to the first main surface 3 of the SiC semiconductor layer 2. More specifically, sides 5B and 5D are formed substantially perpendicular to the first main surface 3 and the second main surface 4.

[0056] In this form, the SiC semiconductor layer 2 has a stacked structure including an n-type SiC semiconductor substrate 6 and an n-type SiC epitaxial layer 7. The second main surface 4 of the SiC semiconductor layer 2 is formed by the SiC semiconductor substrate 6. + The first main surface 3 of the SiC semiconductor layer 2 is formed by the SiC epitaxial layer 7. The side surfaces 5A to 5D of the SiC semiconductor layer 2 are formed by the SiC semiconductor substrate 6 and the SiC epitaxial layer 7.

[0057] The n-type impurity concentration of the SiC epitaxial layer 7 is not more than the n-type impurity concentration of the SiC semiconductor substrate 6. More specifically, the n-type impurity concentration of the SiC epitaxial layer 7 is less than the n-type impurity concentration of the SiC semiconductor substrate 6. The n-type impurity concentration of the SiC semiconductor substrate 6 may be 1.0×10

[0058] cm 18 or more and 1.0×10 -3 cm 21 or less. The n-type impurity concentration of the SiC epitaxial layer 7 may be 1.0×10 -3 cm 15 or more and 1.0×10 -3 cm 18 or less. -3 The thickness TS of the SiC semiconductor substrate 6 may be 40 μm or more and 150 μm or less. The thickness TS may be 40 μm or more and 50 μm or less, 50 μm or more and 60 μm or less, 60 μm or more and 70 μm or less, 70 μm or more and 80 μm or less, 80 μm or more and 90 μm or less, 90 μm or more and 100 μm or less, 100 μm or more and 110 μm or less, 110 μm or more and 120 μm or less, 120 μm or more and 130 μm or less, 130 μm or more and 140 μm or less, or 140 μm or more and 150 μm or less. It is preferable that the thickness TS is 40 μm or more and 130 μm or less. By thinning the SiC semiconductor substrate 6, it is possible to reduce the resistance value due to shortening of the current path.

[0059]

[0060] ​The thickness TE of the SiC epitaxial layer 7 may be 1 μm or more and 50 μm or less. The thickness TE may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 35 μm or less, 35 μm or more and 40 μm or less, 40 μm or more and 45 μm or less, or 45 μm or more and 50 μm or less. Preferably, the thickness TE is 5 μm or more and 15 μm or less.

[0061] The SiC semiconductor layer 2 has an active region 8 and an outer region 9. The active region 8 is the region where a Schottky barrier diode D, an example of a semiconductor device, is formed. The outer region 9 is the region outside the active region 8.

[0062] The active region 8 is located in the central part of the SiC semiconductor layer 2, with a gap in the inward region from the sides 5A to 5D of the SiC semiconductor layer 2 in a plan view. The active region 8 is set to a rectangular shape with four sides parallel to the sides 5A to 5D of the SiC semiconductor layer 2 in a plan view.

[0063] The outer region 9 is defined as the area between the sides 5A to 5D of the SiC semiconductor layer 2 and the periphery of the active region 8. In a plan view, the outer region 9 is defined as an endless shape (a rectangular ring in this configuration) surrounding the active region 8.

[0064] A main surface insulating layer 10 is formed on the first main surface 3 of the SiC semiconductor layer 2. The main surface insulating layer 10 selectively covers the active region 8 and the outer region 9. The main surface insulating layer 10 may have a single-layer structure consisting of a silicon oxide (SiO2) layer or a silicon nitride (SiN) layer.

[0065] The main surface insulating layer 10 may have a laminated structure including a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may be formed on top of the silicon nitride layer. The silicon nitride layer may be formed on top of the silicon oxide layer. In this embodiment, the main surface insulating layer 10 has a single-layer structure consisting of a silicon oxide layer.

[0066] The main surface insulating layer 10 has insulating side surfaces 11A, 11B, 11C, and 11D that are exposed from the side surfaces 5A to 5D of the SiC semiconductor layer 2. The insulating side surfaces 11A to 11D are continuous with the side surfaces 5A to 5D. The insulating side surfaces 11A to 11D are formed flush with the side surfaces 5A to 5D. The insulating side surfaces 11A to 11D consist of cleavage surfaces.

[0067] The thickness of the main surface insulating layer 10 may be 1 μm or more and 50 μm or less. The thickness of the main surface insulating layer 10 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

[0068] A first main surface electrode layer 12 is formed on the main surface insulating layer 10. In a plan view, the first main surface electrode layer 12 is formed in the central part of the SiC semiconductor layer 2, with a gap in the inward region from the side surfaces 5A to 5D of the SiC semiconductor layer 2.

[0069] A passivation layer 13 (insulating layer) is formed on the main surface insulating layer 10. The passivation layer 13 may have a single-layer structure consisting of a silicon oxide layer or a silicon nitride layer.

[0070] The passivation layer 13 may have a multilayer structure including a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may be formed on top of the silicon nitride layer. The silicon nitride layer may be formed on top of the silicon oxide layer. In this embodiment, the passivation layer 13 has a single-layer structure consisting of a silicon nitride layer.

[0071] The side surfaces 14A, 14B, 14C, and 14D of the passivation layer 13 are formed with a gap in the inward region from the side surfaces 5A to 5D of the SiC semiconductor layer 2 in a plan view. The passivation layer 13 exposes the peripheral edge of the first main surface 3 of the SiC semiconductor layer 2 in a plan view. The passivation layer 13 also exposes the main surface insulating layer 10.

[0072] The passivation layer 13 has a sub-pad opening 15 that exposes a portion of the first main surface electrode layer 12 as a pad area. The sub-pad opening 15 is formed in a rectangular shape with four sides parallel to the sides 5A to 5D of the SiC semiconductor layer 2 when viewed from above.

[0073] The thickness of the passivation layer 13 may be 1 μm or more and 50 μm or less. The thickness of the passivation layer 13 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

[0074] A resin layer 16 (insulating layer) is formed on top of the passivation layer 13. The passivation layer 13 and the resin layer 16 form a single insulating laminated structure (insulating layer). In Figure 7, the resin layer 16 is indicated by hatching.

[0075] The resin layer 16 may contain a negative-type or positive-type photosensitive resin. In this embodiment, the resin layer 16 contains polybenzoxazole as an example of a positive-type photosensitive resin. The resin layer 16 may also contain polyimide as an example of a negative-type photosensitive resin.

[0076] The resin sides 17A, 17B, 17C, and 17D of the resin layer 16 are formed with a gap in the inward region from the sides 5A to 5D of the SiC semiconductor layer 2 in a plan view. The resin layer 16 exposes the peripheral edge of the first main surface 3 of the SiC semiconductor layer 2 in a plan view. The resin layer 16, together with the passivation layer 13, exposes the main surface insulating layer 10. In this configuration, the resin sides 17A to 17D of the resin layer 16 are formed flush with the sides 14A to 14D of the passivation layer 13.

[0077] The resin sides 17A to 17D of the resin layer 16 are the parts that demarcated the dicing streets when cutting the SiC semiconductor device 1 from a single SiC semiconductor wafer. In this configuration, the sides 14A to 14D of the passivation layer 13 are also the parts that demarcated the dicing streets. Furthermore, the insulation distance from the sides 5A to 5D of the SiC semiconductor layer 2 can be increased.

[0078] By exposing the peripheral edge of the first main surface 3 of the SiC semiconductor layer 2 from the resin layer 16 and the passivation layer 13, it becomes unnecessary to physically cut the resin layer 16 and the passivation layer 13. This allows for the smooth cutting of the SiC semiconductor device 1 from a single SiC semiconductor wafer.

[0079] The distance between sides 5A to 5D and resin sides 17A to 17D (sides 14A to 14D) may be 1 μm or more and 25 μm or less. The distance between sides 5A to 5D and resin sides 17A to 17D (sides 14A to 14D) may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, or 20 μm or more and 25 μm or less. Of course, sides 14A to 14D of the passivation layer 13 may be formed flush with sides 5A to 5D of the SiC semiconductor layer 2.

[0080] The resin layer 16 has a pad opening 18 that exposes a portion of the first main surface electrode layer 12 as a pad area. The pad opening 18 is formed in a rectangular shape with four sides parallel to the sides 5A to 5D of the SiC semiconductor layer 2 when viewed from above.

[0081] The pad opening 18 communicates with the sub-pad opening 15. The inner wall of the pad opening 18 is formed flush with the inner wall of the sub-pad opening 15. The inner wall of the pad opening 18 may be located on the side surfaces 5A to 5D of the SiC semiconductor layer 2 relative to the inner wall of the sub-pad opening 15. The inner wall of the pad opening 18 may be located in the inner region of the SiC semiconductor layer 2 relative to the inner wall of the sub-pad opening 15. The resin layer 16 may cover the inner wall of the sub-pad opening 15.

[0082] The thickness of the resin layer 16 may be 1 μm or more and 50 μm or less. The thickness of the resin layer 16 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

[0083] A second main surface electrode layer 19 is formed on the second main surface 4 of the SiC semiconductor layer 2. The second main surface electrode layer 19 forms ohmic contact with the second main surface 4 (SiC semiconductor substrate 6) of the SiC semiconductor layer 2.

[0084] Multiple modification lines 22A to 22D (modified layers) are formed on the sides 5A to 5D of the SiC semiconductor layer 2. The modification lines 22A to 22D are not formed on the main surface insulating layer 10, the passivation layer 13, and the resin layer 16. The modification lines 22A to 22D include modification line 22A formed on side 5A, modification line 22B formed on side 5B, modification line 22C formed on side 5C, and modification line 22D formed on side 5D.

[0085] Modification lines 22A and 22C are formed on the a-plane of the SiC single crystal, respectively, while modification lines 22B and 22D are formed on the m-plane of the SiC single crystal, respectively. Multiple modification lines 22A are formed on side surface 5A (two or more; three in this configuration). Multiple modification lines 22C are formed on side surface 5C (two or more; three in this configuration). The number of modification lines 22A and 22C is preferably between two and six.

[0086] Modification lines 22B are formed one or more times (two or more; one in this configuration) on side surface 5B. Modification lines 22D are formed one or more times (two or more; one in this configuration) on side surface 5D. The number of modification lines 22B and 22D is preferably less than or equal to the number of modification lines 22A and 22C. It is even more preferable that the number of modification lines 22B and 22D is less than the number of modification lines 22A and 22C.

[0087] Modification lines 22A to 22D include layered regions in which a portion of the SiC single crystal forming sides 5A to 5D has been modified to have properties different from those of the SiC single crystal. Modification lines 22A to 22D include regions in which density, refractive index, mechanical strength (crystal strength), or other physical properties have been modified to have properties different from those of the SiC single crystal.

[0088] Modification lines 22A to 22D may include at least one of the following layers: a melt-re-hardened layer, a defect layer, a breakdown layer, or a refractive index change layer. The melt-re-hardened layer is a layer in which a portion of the SiC semiconductor layer 2 has melted and then hardened again. The defect layer is a layer containing vacancies, cracks, etc., formed in the SiC semiconductor layer 2. The breakdown layer is a layer in which a portion of the SiC semiconductor layer 2 has broken down dielectrically. The refractive index change layer is a layer in which a portion of the SiC semiconductor layer 2 has changed to a refractive index different from that of the SiC single crystal.

[0089] The modification lines 22A to 22D extend in a strip-like manner along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. The tangential direction of the first main surface 3 is perpendicular to the normal direction Z. The tangential direction includes the first direction X (the m-axis direction of the SiC single crystal) and the second direction Y (the a-axis direction of the SiC single crystal).

[0090] Referring to Figure 3, the multiple modification lines 22A are each formed as strips extending linearly along the m-axis direction on the side surface 5A. The multiple modification lines 22A are formed offset from each other in the normal direction Z.

[0091] It is preferable that the multiple modification lines 22A are formed with intervals in the normal direction Z. The multiple modification lines 22A may overlap each other in the normal direction Z. Each of the multiple modification lines 22A has a thickness TR with respect to the normal direction Z. The thicknesses TR of the multiple modification lines 22A may be equal to each other or may be different.

[0092] Of the multiple modification lines 22A, the modification line 22A on the first main surface 3 side is formed with a gap between the first main surface 3 and the second main surface 4 of the SiC semiconductor layer 2. The modification line 22A on the first main surface 3 side exposes the surface layer of the first main surface 3 of the SiC semiconductor layer 2 from the side surface 5A.

[0093] Of the multiple modification lines 22A, the modification line 22A on the second main surface 4 side is formed with a gap between the second main surface 4 and the first main surface 3 of the SiC semiconductor layer 2. The modification line 22A on the second main surface 4 side exposes the surface layer of the second main surface 4 of the SiC semiconductor layer 2 from the side surface 5A.

[0094] Multiple modification lines 22A are formed on the SiC semiconductor substrate 6. The multiple modification lines 22A are formed at intervals from the boundary between the SiC semiconductor substrate 6 and the SiC epitaxial layer 7 to the second main surface 4. The multiple modification lines 22A expose the SiC epitaxial layer 7 in the surface layer portion of the first main surface 3 of the SiC semiconductor layer 2.

[0095] The side surface 5A facing the a-face of the SiC single crystal has the property of cleaving with the c-axis of the SiC single crystal as the cleavage direction. Therefore, when multiple modification lines 22A are formed along the normal direction Z of the first main surface 3 or along the c-axis of the SiC single crystal, the side surface 5A becomes an inclined surface along the c-axis of the SiC single crystal.

[0096] Therefore, in this embodiment, referring to Figure 8, one or more (one in this embodiment) inclined portions are introduced on the side surface 5A, inclined in the direction opposite to the c-axis of the SiC single crystal from the normal of the first main surface 3 with respect to the a-axis. More specifically, the direction opposite to the c-axis is the direction between the normal direction Z and the a-axis direction ([11-20] direction) of the SiC single crystal.

[0097] In this configuration, multiple modification lines 22A, formed offset from each other in the a-axis direction of the SiC single crystal in a cross-sectional view, introduce a sloping portion toward the side surface 5A that is opposite to the c-axis of the SiC single crystal (towards the side surface 5C).

[0098] One or more inclined portions are also formed on the side surface 5A, along the c-axis of the SiC single crystal. The inclined portions facing away from the c-axis of the SiC single crystal reduce the area where inclined portions toward the c-axis are formed.

[0099] More specifically, the multiple modification lines 22A are formed with alternating offsets in the cross-sectional view, with respect to the normal direction Z, on one side ([11-20] direction) and the other side ([-1-120] direction) in the a-axis direction.

[0100] If four or more modification lines 22A are formed on the side surface 5A, it is not necessary for all modification lines 22A to be formed with alternating offsets on one side and the other side in the a-axis direction. Multiple modification lines 22A may include portions that are formed with alternating offsets on one side and the other side in the a-axis direction.

[0101] It is preferable that the multiple modification lines 22A are formed such that a straight line connecting any two modification lines 22A intersects at least the normal to the first main surface 3. It is preferable that the straight line connecting any two modification lines 22A intersects the c-axis of the SiC single crystal. It is preferable that the straight line connecting any two modification lines 22A intersects the normal to the first main surface 3 and the c-axis of the SiC single crystal.

[0102] Preferably, the multiple modification lines 22A include one or more modification lines 22A formed offset inward (towards the [11-20] direction) of the SiC semiconductor layer 2 with respect to the a-axis direction relative to the modification line 22A on the second main surface 4 side.

[0103] In this configuration, an example is shown in which the intermediate modification line 22A is formed offset inward from the modification line 22A on the second main surface 4 side within the SiC semiconductor layer 2. The inclined portion, which is directed away from the c-axis of the SiC single crystal, is formed in the region between the modification line 22A on the second main surface 4 side and the intermediate modification line 22A. The straight line connecting the modification line 22A on the second main surface 4 side and the intermediate modification line 22A intersects the normal to the first main surface 3 and the c-axis of the SiC single crystal.

[0104] Preferably, the multiple modification lines 22A include one or more modification lines 22A formed offset inward (towards the [11-20] direction) of the SiC semiconductor layer 2 with respect to the a-axis direction relative to the modification line 22A on the first main surface 3 side.

[0105] In this configuration, an example is shown in which the intermediate modification line 22A is formed shifted inward within the SiC semiconductor layer 2 relative to the modification line 22A on the first main surface 3 side. The inclined portion toward the c-axis of the SiC single crystal is formed in the region between the modification line 22A on the first main surface 3 side and the intermediate modification line 22A.

[0106] The straight line connecting the modification line 22A on the first main surface 3 side and the intermediate modification line 22A intersects the normal to the first main surface 3. The straight line connecting the modification line 22A on the first main surface 3 side and the intermediate modification line 22A may extend along the c-axis of the SiC single crystal or may intersect the c-axis of the SiC single crystal.

[0107] When three or more modification lines 22A are formed, it is preferable that the multiple modification lines 22A include one or more modification lines 22A that are offset inward (towards the [11-20] direction) of the SiC semiconductor layer 2 with respect to a straight line connecting any two modification lines 22A.

[0108] In this form, an example is shown in which the intermediate modification line 22A is formed so as to be shifted inward of the SiC semiconductor layer 2 with respect to a straight line connecting the modification line 22A on the first main surface 3 side and the modification line 22A on the second main surface 4 side.

[0109] The distance DR between two modification lines 22A adjacent to each other with respect to the a-axis direction of the SiC single crystal may be more than 0 μm and 20 μm or less. The distance DR may be more than 0 μm and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, or 15 μm or more and 20 μm or less.

[0110] The maximum distance DD between the outermost modification line 22A and the innermost modification line 22A with respect to the a-axis direction may be more than 0 μm and 40 μm or less. The maximum distance DD may be more than 0 μm and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 35 μm or less, 35 μm or more and 40 μm or less, 40 μm or more and 45 μm or less, 45 μm or more and 50 μm or less. The maximum distance DD may coincide with the distance DR.

[0111] The distance DR is preferably a value less than TL×tanθ (0 < DR < TL×tanθ) using the off-angle θ and the thickness TL of the SiC semiconductor layer 2. Also, the maximum distance DD is preferably a value less than TL×tanθ (0 < DD < TL×tanθ). In this case, it is preferable that three or more modification lines 22A are formed.

[0112] The side surface 5A of the SiC semiconductor layer 2 has a raised portion having a plurality of modification lines 22A at the top or the base. In this form, an example is shown in which the modification line 22A on the first main surface 3 side and the modification line 22A on the second main surface 4 side form the top of the raised portion, and the intermediate modification line 22A forms the base of the raised portion.

[0113] The modification line 22B is formed as a strip extending linearly along the a-axis on the side surface 5B. The modification line 22B has a thickness TR with respect to the normal direction Z. The modification line 22B is formed at a gap between the first main surface 3 and the second main surface 4 of the SiC semiconductor layer 2. The modification line 22B exposes the surface layer of the first main surface 3 of the SiC semiconductor layer 2 from the side surface 5B.

[0114] The modification line 22B is formed with a gap between the second main surface 4 and the first main surface 3 of the SiC semiconductor layer 2. The modification line 22B exposes the surface layer of the second main surface 4 of the SiC semiconductor layer 2 from the side surface 5B.

[0115] The modification line 22B is formed on the SiC semiconductor substrate 6. The modification line 22B is formed at a distance from the boundary between the SiC semiconductor substrate 6 and the SiC epitaxial layer 7 to the second main surface 4. The modification line 22B exposes the SiC epitaxial layer 7 at the surface of the first main surface 3 of the SiC semiconductor layer 2.

[0116] Of course, multiple modification lines 22B may be formed on the side surface 5B. In this case, the multiple modification lines 22B are formed offset from each other in the normal direction Z. Preferably, the multiple modification lines 22B are formed with gaps between them in the normal direction Z. The multiple modification lines 22B may overlap each other in the normal direction Z. The thicknesses TR of the multiple modification lines 22B may be equal to each other or may be different.

[0117] Referring to Figure 4, the multiple modification lines 22C are each formed as a strip extending linearly along the m-axis direction on the side surface 5C. The multiple modification lines 22C are formed offset from each other in the normal direction Z.

[0118] It is preferable that the multiple modification lines 22C are formed with intervals in the normal direction Z. The multiple modification lines 22C may overlap each other in the normal direction Z. Each of the multiple modification lines 22C has a thickness TR with respect to the normal direction Z. The thicknesses TR of the multiple modification lines 22C may be equal to each other or may be different.

[0119] Of the multiple modification lines 22C, the modification line 22C on the first main surface 3 side is formed with a gap between the first main surface 3 and the second main surface 4 of the SiC semiconductor layer 2. The modification line 22C on the first main surface 3 side exposes the surface layer of the first main surface 3 of the SiC semiconductor layer 2 from the side surface 5C.

[0120] Of the multiple modification lines 22C, the modification line 22C on the second main surface 4 side is formed with a gap between the second main surface 4 and the first main surface 3 of the SiC semiconductor layer 2. The modification line 22C on the second main surface 4 side exposes the surface layer of the second main surface 4 of the SiC semiconductor layer 2 from the side surface 5C.

[0121] Multiple modification lines 22C are formed on the SiC semiconductor substrate 6. The multiple modification lines 22C are formed at intervals from the boundary between the SiC semiconductor substrate 6 and the SiC epitaxial layer 7 to the second main surface 4. The multiple modification lines 22C expose the SiC epitaxial layer 7 at the surface layer of the first main surface 3 of the SiC semiconductor layer 2.

[0122] The side surface 5C facing the a-face of the SiC single crystal has the property of cleaving along the c-axis of the SiC single crystal as the cleavage direction. Therefore, when multiple modification lines 22C are formed along the normal direction Z of the first principal surface 3 or along the c-axis of the SiC single crystal, the side surface 5C becomes an inclined surface along the c-axis of the SiC single crystal.

[0123] Therefore, in this embodiment, referring to Figure 8, one or more (one in this embodiment) inclined portions are introduced on side surface 5C, inclined from the normal of the first main surface 3 in the direction opposite to the c-axis of the SiC single crystal (opposite to side surface 5A). More specifically, the direction opposite to the c-axis is the direction between the normal direction Z and the a-axis direction ([11-20] direction) of the SiC single crystal.

[0124] In this configuration, multiple modification lines 22C, formed offset from each other in the a-axis direction of the SiC single crystal in a cross-sectional view, introduce a sloping portion toward the side surface 5C that is opposite to the c-axis of the SiC single crystal (opposite to side surface 5A).

[0125] One or more inclined portions are also formed on the side surface 5C, along the c-axis of the SiC single crystal. The inclined portions directed away from the c-axis of the SiC single crystal reduce the area where inclined portions toward the c-axis are formed.

[0126] More specifically, the multiple modification lines 22C are formed alternately offset in the cross-sectional view with respect to the normal direction Z, on one side ([11-20] direction) and the other side ([-1-120] direction) in the a-axis direction.

[0127] If four or more modification lines 22C are formed on the side surface 5C, it is not necessary for all modification lines 22C to be formed with alternating offsets on one side and the other side in the a-axis direction. Multiple modification lines 22C may include portions that are formed with alternating offsets on one side and the other side in the a-axis direction.

[0128] It is preferable that the multiple modification lines 22C are formed such that a straight line connecting any two modification lines 22C intersects at least the normal to the first main surface 3. It is preferable that the straight line connecting any two modification lines 22C intersects the c-axis of the SiC single crystal. It is preferable that the straight line connecting any two modification lines 22C intersects the normal to the first main surface 3 and the c-axis of the SiC single crystal.

[0129] Preferably, the multiple modification lines 22C include one or more modification lines 22C formed offset outward (towards the [11-20] direction) of the SiC semiconductor layer 2 with respect to the a-axis direction relative to the modification line 22C on the second main surface 4 side.

[0130] In this configuration, an example is shown in which the intermediate modification line 22C is formed offset outward from the SiC semiconductor layer 2 relative to the modification line 22C on the second main surface 4 side. The inclined portion directed away from the c-axis of the SiC single crystal is formed in the region between the modification line 22C on the second main surface 4 side and the intermediate modification line 22C. The straight line connecting the modification line 22C on the second main surface 4 side and the intermediate modification line 22C intersects the normal to the first main surface 3 and the c-axis of the SiC single crystal.

[0131] Preferably, the multiple modification lines 22C include one or more modification lines 22C formed offset outward (towards the [11-20] direction) of the SiC semiconductor layer 2 with respect to the a-axis direction relative to the modification line 22C on the first main surface 3 side.

[0132] In this configuration, an example is shown in which the intermediate modification line 22C is formed shifted outward from the SiC semiconductor layer 2 relative to the modification line 22C on the first main surface 3 side. The inclined portion toward the c-axis of the SiC single crystal is formed in the region between the modification line 22C on the first main surface 3 side and the intermediate modification line 22C.

[0133] The straight line connecting the modification line 22C on the first main surface 3 side and the intermediate modification line 22C intersects the normal to the first main surface 3. The straight line connecting the modification line 22C on the first main surface 3 side and the intermediate modification line 22C may extend along the c-axis of the SiC single crystal or may intersect the c-axis of the SiC single crystal.

[0134] When three or more modification lines 22C are formed, it is preferable that the multiple modification lines 22C include one or more modification lines 22C formed offset outward (towards the [11-20] direction) from the straight line connecting any two modification lines 22A.

[0135] In this form, an example is shown in which the intermediate modification line 22C is formed offset outward from the SiC semiconductor layer 2 with respect to a straight line connecting the modification line 22C on the side of the first main surface 3 and the modification line 22C on the side of the second main surface 4.

[0136] The distance DR between two modification lines 22C adjacent to each other with respect to the a-axis direction of the SiC single crystal may be more than 0 μm and 20 μm or less. The distance DR may be more than 0 μm and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, or 15 μm or more and 20 μm or less.

[0137] The maximum distance DD between the outermost modification line 22C and the innermost modification line 22C with respect to the a-axis direction may be more than 0 μm and 40 μm or less. The maximum distance DD may be more than 0 μm and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 35 μm or less, 35 μm or more and 40 μm or less, 40 μm or more and 45 μm or less, 45 μm or more and 50 μm or less. The maximum distance DD may coincide with the distance DR.

[0138] The distance DR is preferably a value less than TL×tanθ (0 < DR < TL×tanθ) using the off-angle θ and the thickness TL of the SiC semiconductor layer 2. Also, the maximum distance DD is preferably a value less than TL×tanθ (0 < DD < TL×tanθ). In this case, it is preferable that three or more modification lines 22C are formed.

[0139] The side surface 5C of the SiC semiconductor layer 2 has a raised portion having a plurality of modification lines 22C at the top or the base. In this form, an example is shown in which the modification line 22C on the side of the first main surface 3 and the modification line 22C on the side of the second main surface 4 form the base of the raised portion, and the intermediate modification line 22C forms the top of the raised portion.

[0140] The modification line 22D is formed as a strip extending linearly along the a-axis on the side surface 5D. The modification line 22D has a thickness TR with respect to the normal direction Z. The modification line 22D is formed at a gap between the first main surface 3 and the second main surface 4 of the SiC semiconductor layer 2. The modification line 22D exposes the surface layer of the first main surface 3 of the SiC semiconductor layer 2 from the side surface 5D.

[0141] The modification line 22D is formed with a gap between the second main surface 4 and the first main surface 3 of the SiC semiconductor layer 2. The modification line 22D exposes the surface layer of the second main surface 4 of the SiC semiconductor layer 2 from the side surface 5D.

[0142] The modification line 22D is formed on the SiC semiconductor substrate 6. The modification line 22D is formed at a distance from the boundary between the SiC semiconductor substrate 6 and the SiC epitaxial layer 7 to the second main surface 4. The modification line 22D exposes the SiC epitaxial layer 7 at the surface of the first main surface 3 of the SiC semiconductor layer 2.

[0143] Of course, multiple modification lines 22D may be formed on the side surface 5D. In this case, the multiple modification lines 22D are formed offset from each other in the normal direction Z. Preferably, the multiple modification lines 22D are formed with gaps between them in the normal direction Z. The multiple modification lines 22D may overlap each other in the normal direction Z. The thicknesses TR of the multiple modification lines 22D may be equal to each other or may be different.

[0144] Modification lines 22A and 22B may be connected to each other at the corners connecting sides 5A and 5B of the SiC semiconductor layer 2. Modification lines 22B and 22C may be connected to each other at the corners connecting sides 5B and 5C of the SiC semiconductor layer 2.

[0145] Modification lines 22C and 22D may be connected to each other at the corners connecting side surfaces 5C and 5D in the SiC semiconductor layer 2. Modification lines 22D and 22A may be connected to each other at the corners connecting side surfaces 5D and 5A in the SiC semiconductor layer 2.

[0146] The modification lines 22A to 22D may be integrally formed so as to surround the SiC semiconductor layer 2. In other words, the modification lines 22A to 22D may form a single endless (ring-shaped) modification line surrounding the SiC semiconductor layer 2 on the side surfaces 5A to 5D of the SiC semiconductor layer 2.

[0147] The modification lines 22A to 22D are formed on the sides 5A to 5D of the SiC semiconductor layer 2 with different occupancy ratios RA, RB, RC, and RD. Occupancy ratio RA is the proportion of side 5A occupied by modification line 22A. Occupancy ratio RB is the proportion of side 5B occupied by modification line 22B. Occupancy ratio RC is the proportion of side 5C occupied by modification line 22C. Occupancy ratio RD is the proportion of side 5D occupied by modification line 22D.

[0148] The occupied proportions RA to RD differ more specifically depending on the crystal plane of the SiC single crystal. The occupied proportions RB and RD of the modification lines 22B and 22D formed on the m plane of the SiC single crystal are less than or equal to the occupied proportions RA and RC of the modification lines 22A and 22C formed on the a plane of the SiC single crystal (RB, RD ≤ RA, RC). More specifically, the occupied proportions RB and RD are less than or equal to the occupied proportions RA and RC (RB, RD ≤ RA, RC). <RA,RC)である。

[0149] The occupancy ratios RA and RC for reforming lines 22A and 22C may be equal or different. Similarly, the occupancy ratios RB and RD for reforming lines 22B and 22D may be equal or different.

[0150] The exclusive ratios RA to RD are adjusted according to the number, thickness TR, total surface area, etc. of the modification lines 22A to 22D. In this form, as an example, the exclusive ratios RA to RD of the modification lines 22A to 22D are adjusted by adjusting the number and thickness TR of the modification lines 22A to 22D.

[0151] The number of the modification lines 22B and 22D is less than the number of the modification lines 22A and 22C, respectively. Also, the total value of the thicknesses TR of the modification lines 22B and 22D is less than the total value of the thicknesses TR of the modification lines 22A and 22C, respectively. Further, the total value of the surface areas of the modification lines 22B and 22D is less than the total value of the surface areas of the modification lines 22A and 22C, respectively.

[0152] Regarding the normal direction Z, the thickness TR of the modification lines 22A to 22D is preferably not more than the thickness TL of the SiC semiconductor layer 2 (TR≦TL). More preferably, the thickness TR of the modification lines 22A to 22D is less than the thickness TS of the SiC semiconductor substrate 6 (TR<TS).

[0153] The thickness TR of the modification lines 22A to 22D may be not less than the thickness TE of the SiC epitaxial layer 7 (TR≧TE). The thicknesses of the thickness TR of the modification line 22A, the thickness TR of the modification line 22B, the thickness TR of the modification line 22C, and the thickness TR of the modification line 22D may be equal to each other or different from each other.

[0154] The ratio TR / TL of the thickness TR of the modification lines 22A to 22D to the thickness TL of the SiC semiconductor layer 2 is preferably not less than 0.1 and less than 1.0. The ratio TR / TL may be not less than 0.1 and not more than 0.2, not less than 0.2 and not more than 0.4, not less than 0.4 and not more than 0.6, not less than 0.6 and not more than 0.8, or not less than 0.8 and less than 1.0.

[0155] The ratio TR / TL may be 0.1 to 0.2, 0.2 to 0.3, 0.3 to 0.4, 0.4 to 0.5, 0.5 to 0.6, 0.6 to 0.7, 0.7 to 0.8, 0.8 to 0.9, or 0.9 to less than 1.0. Preferably, the ratio TR / TL is 0.2 to 0.5.

[0156] The ratio TR / TS of the thickness TR of the modified lines 22A to 22D to the thickness TS of the SiC semiconductor substrate 6 is more preferably 0.1 or more and less than 1.0. The ratio TR / TS may also be 0.1 or more and 0.2 or less, 0.2 or more and 0.4 or less, 0.4 or more and 0.6 or less, 0.6 or more and 0.8 or less, or 0.8 or more and less than 1.0.

[0157] The ratio TR / TS may be 0.1 to 0.2, 0.2 to 0.3, 0.3 to 0.4, 0.4 to 0.5, 0.5 to 0.6, 0.6 to 0.7, 0.7 to 0.8, 0.8 to 0.9, or 0.9 to less than 1.0. Preferably, the ratio TR / TS is 0.2 to 0.5.

[0158] Referring to Figure 5, the modification line 22A includes a plurality of a-plane modification portions 28 (modified portions). In other words, the modification line 22A is formed by an aggregate of a plurality of a-plane modification portions 28. The plurality of a-plane modification portions 28 are portions in which the SiC single crystal exposed from the side surface 5A has been modified to have properties different from those of the SiC single crystal. The region surrounding each a-plane modification portion 28 on the side surface 5A may also be modified to have properties different from those of the SiC single crystal.

[0159] Each of the multiple surface modification sections 28 includes one end 28a located on the first main surface 3 side, another end 28b located on the second main surface 4 side, and a connecting section 28c connecting the one end 28a and the other end 28b.

[0160] Each of the multiple a-surface modification portions 28 is formed in a linear shape extending in the normal direction Z. As a result, the multiple a-surface modification portions 28 are formed in a striped pattern as a whole. The multiple a-surface modification portions 28 may include multiple a-surface modification portions 28 that are formed in a tapered shape, with the width in the m-axis direction narrowing from one end 28a to the other end 28b.

[0161] Multiple a-surface modification sections 28 are formed with spacing in the m-axis direction so that they face each other in the m-axis direction. Multiple a-surface modification sections 28 may overlap each other in the m-axis direction. A band-shaped region extending in the m-axis direction is formed by a line connecting one end 28a of the multiple a-surface modification sections 28 and a line connecting the other end 28b of the multiple a-surface modification sections 28. The modification line 22A is formed by this band-shaped region.

[0162] Multiple a-surface modification portions 28 may each have a notch formed by cutting out the side surface 5A. Multiple a-surface modification portions 28 may each have a recess formed in the direction of the a-axis from the side surface 5A. Multiple a-surface modification portions 28 may be formed in a dot-like manner depending on the length in the normal direction Z and the width in the m-axis direction.

[0163] With respect to the m-axis direction, the pitch PR between the centers of multiple adjacent a-surface modified portions 28 may be greater than 0 μm and less than or equal to 20 μm. The pitch PR may be greater than 0 μm and less than or equal to 5 μm, 5 μm or more and less than or equal to 10 μm, 10 μm or more and less than or equal to 15 μm, or 15 μm or more and less than or equal to 20 μm.

[0164] With respect to the m-axis direction, the width WR of each a-surface modified portion 28 may be greater than 0 μm and less than or equal to 20 μm. The width WR may be greater than 0 μm and less than or equal to 5 μm, 5 μm or more and less than or equal to 10 μm, 10 μm or more and less than or equal to 15 μm, or 15 μm or more and less than or equal to 20 μm.

[0165] The modification line 22C has the same structure as the modification line 22A, except that it is formed on side surface 5C. The description of the modification line 22A is applied mutatis mutandis to the description of the modification line 22C, by substituting "side surface 5A" for "side surface 5C".

[0166] Referring to Figure 6, the modification line 22D includes a plurality of m-plane modification sections 29 (modified sections). In other words, the modification line 22D is formed by an aggregate of a plurality of m-plane modification sections 29. The plurality of m-plane modification sections 29 are portions of the SiC single crystal exposed from the side surface 5D that have been modified to properties different from those of the SiC single crystal. The region surrounding each m-plane modification section 29 on the side surface 5D may also be modified to properties different from those of the SiC single crystal.

[0167] Each of the multiple m-surface modification sections 29 includes one end 29a located on the first main surface 3 side, the other end 29b located on the second main surface 4 side, and a connecting section 29c connecting the one end 29a and the other end 29b.

[0168] Each of the multiple m-plane modified portions 29 is formed in a linear shape extending in the normal direction Z. As a result, the multiple m-plane modified portions 29 are formed in a striped pattern as a whole. The multiple m-plane modified portions 29 may include multiple m-plane modified portions 29 that are formed in a tapered shape, with the width in the a-axis direction narrowing from one end 29a to the other end 29b.

[0169] Multiple m-plane modified portions 29 are formed with spacing in the a-axis direction so that they face each other in the a-axis direction. Multiple m-plane modified portions 29 may overlap each other in the a-axis direction. A band-shaped region extending in the a-axis direction is formed by a line connecting one end 29a of the multiple m-plane modified portions 29 and a line connecting the other end 29b of the multiple m-plane modified portions 29. The modification line 22D is formed by this band-shaped region.

[0170] Multiple m-plane modified portions 29 may each have a notch formed by cutting out the side surface 5D. Multiple m-plane modified portions 29 may each have a recess formed in the direction of the m-axis from the side surface 5D. Multiple m-plane modified portions 29 may be formed in a dot-like manner depending on the length in the normal direction Z and the width in the a-axis direction.

[0171] With respect to the a-axis, the pitch PR between the centers of multiple adjacent m-surface modified portions 29 may be 0 μm or more and 20 μm or less. The pitch PR may be 0 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, or 15 μm or more and 20 μm or less.

[0172] With respect to the a-axis, the width WR of each m-surface modified portion 29 may be greater than 0 μm and less than or equal to 20 μm. The width WR may be greater than 0 μm and less than or equal to 5 μm, 5 μm or more and less than or equal to 10 μm, 10 μm or more and less than or equal to 15 μm, or 15 μm or more and less than or equal to 20 μm.

[0173] The modification line 22B has the same structure as the modification line 22D, except that it is formed on side 5B. The description of the modification line 22D is applied mutatis mutandis to the description of the modification line 22B, by substituting "side 5D" for "side 5B".

[0174] Referring to Figure 8, in the active region 8, an n-type diode region 35 is formed on the surface of the first main surface 3 of the SiC semiconductor layer 2. In this configuration, the diode region 35 is formed in the central part of the first main surface 3 of the SiC semiconductor layer 2. In this configuration, the diode region 35 is set to a rectangular shape with four sides parallel to the sides 5A to 5D of the SiC semiconductor layer 2 in a plan view.

[0175] The n-type impurity concentration in the diode region 35 may be greater than or equal to the n-type impurity concentration in the SiC epitaxial layer 7. In this embodiment, the diode region 35 is formed using a portion of the SiC epitaxial layer 7. The n-type impurity concentration in the diode region 35 is equal to the n-type impurity concentration in the SiC epitaxial layer 7. The diode region 35 may also be formed by introducing n-type impurities into the surface layer of the SiC epitaxial layer 7.

[0176] In the outer region 9, the surface layer of the first main surface 3 of the SiC semiconductor layer 2 is p + A type of guard region 36 is formed. The guard region 36 is formed in a strip shape that extends along the diode region 35 in a plan view.

[0177] More specifically, the guard region 36 is formed in an endless shape (for example, a square ring, a square ring with chamfered corners, or a circular ring) surrounding the diode region 35 in a plan view. Thus, the guard region 36 is formed as a guard ring region. In this configuration, the diode region 35 is defined by the guard region 36. The active region 8 is also defined by the guard region 36.

[0178] The p-type impurities in the guard region 36 do not need to be activated. In this case, the guard region 36 is formed as a non-semiconductor region. The p-type impurities in the guard region 36 do need to be activated. In this case, the guard region 36 is formed as a p-type semiconductor region.

[0179] The aforementioned main surface insulating layer 10 is formed on the first main surface 3 of the SiC semiconductor layer 2. Diode openings 37 are formed in the main surface insulating layer 10, exposing the diode region 35. The diode openings 37 expose not only the diode region 35 but also the inner periphery of the guard region 36. In a plan view, the diode openings 37 are formed in a rectangular shape with four sides parallel to the sides 5A to 5D of the SiC semiconductor layer 2.

[0180] The aforementioned first main surface electrode layer 12 is formed on the main surface insulating layer 10. The first main surface electrode layer 12 extends from above the insulating layer into the diode opening 37. The first main surface electrode layer 12 is electrically connected to the diode region 35 within the diode opening 37.

[0181] More specifically, the first main surface electrode layer 12 forms a Schottky junction with the diode region 35. This forms a Schottky barrier diode D with the first main surface electrode layer 12 as the anode and the diode region 35 as the cathode. The aforementioned passivation layer 13 and resin layer 16 are formed on the main surface insulating layer 10.

[0182] FIG. 9 is a perspective view showing a SiC semiconductor wafer 41 used in the manufacture of the SiC semiconductor device 1 shown in FIG. 3.

[0183] The SiC semiconductor wafer 41 is a member serving as the base of the SiC semiconductor substrate 6. The SiC semiconductor wafer 41 includes a 4H-SiC single crystal as an example of a hexagonal SiC single crystal. In this form, the SiC semiconductor wafer 41 has an n-type impurity concentration corresponding to the n-type impurity concentration of the SiC semiconductor substrate 6.

[0184] The SiC semiconductor wafer 41 is formed in a plate shape or a disk shape. The SiC semiconductor wafer 41 may be formed in a disk shape. The SiC semiconductor wafer 41 has a first wafer main surface 42 on one side, a second wafer main surface 43 on the other side, and a wafer side surface 44 connecting the first wafer main surface 42 and the second wafer main surface 43.

[0185] The thickness TW of the SiC semiconductor wafer 41 exceeds the thickness TS of the SiC semiconductor substrate 6 (TS < TW). The thickness TW of the SiC semiconductor wafer 41 is adjusted to the thickness TS of the SiC semiconductor substrate 6 by grinding.

[0186] The thickness TW may be more than 150 μm and 750 μm or less. The thickness TW may be more than 150 μm and 300 μm or less, 300 μm or more and 450 μm or less, 450 μm or more and 600 μm or less, or 600 μm or more and 750 μm or less. In view of the grinding time of the SiC semiconductor wafer 41, the thickness TW is preferably more than 150 μm and 500 μm or less. The thickness TW is typically 300 μm or more and 450 μm or less.

[0187] In this form, the first wafer main surface 42 and the second wafer main surface 43 face the c-plane of the SiC single crystal. The first wafer main surface 42 faces the (0001) plane (silicon plane). The second wafer main surface 43 faces the (000-1) plane (carbon plane) of the SiC single crystal.

[0188] The first wafer main surface 42 and the second wafer main surface 43 have an off-angle θ that is inclined at an angle of 10° or less in the [11-20] direction with respect to the c-plane of the SiC single crystal. The normal direction Z of the first wafer main surface 42 is inclined by the off-angle θ with respect to the c-axis (

[0001] direction) of the SiC single crystal.

[0189] The off-angle θ may be between 0° and 5.0°. The off-angle θ may be set within the range of angles between 0° and 1.0°, 1.0° and 1.5°, 1.5° and 2.0°, 2.0° and 2.5°, 2.5° and 3.0°, 3.0° and 3.5°, 3.5° and 4.0°, 4.0° and 4.5°, or 4.5° and 5.0°. It is preferable that the off-angle θ is greater than 0°. The off-angle θ may be less than 4.0°.

[0190] The off-angle θ may be set to an angle range of 3.0° or more and 4.5° or less. In this case, it is preferable that the off-angle θ is set to an angle range of 3.0° or more and 3.5° or less and 3.5° or more and 4.0° or less.

[0191] The off-angle θ may be set to an angle range of 1.5° or more and 3.0° or less. In this case, it is preferable that the off-angle θ is set to an angle range of 1.5° or more and 2.0° or more and 2.5° or less.

[0192] The SiC semiconductor wafer 41 includes a first wafer corner 45 connecting the first wafer main surface 42 and the wafer side surface 44, and a second wafer corner 46 connecting the second wafer main surface 43 and the wafer side surface 44. The first wafer corner 45 has a first chamfered portion 47 that slopes downward from the first wafer main surface 42 toward the wafer side surface 44. The second wafer corner 46 has a second chamfered portion 48 that slopes downward from the second wafer main surface 43 toward the wafer side surface 44.

[0193] The first chamfered portion 47 may be formed in a convex curved shape. The second chamfered portion 48 may also be formed in a convex curved shape. The first chamfered portion 47 and the second chamfered portion 48 suppress cracks in the SiC semiconductor wafer 41.

[0194] An orientation flat 49 is formed on the wafer side surface 44 of the SiC semiconductor wafer 41 as an example of a marker indicating the crystal orientation of the SiC single crystal. The orientation flat 49 is a notch formed on the wafer side surface 44 of the SiC semiconductor wafer 41. In this configuration, the orientation flat 49 extends linearly along the a-axis direction ([11-20] direction) of the SiC single crystal.

[0195] Multiple (for example, two) orientation flats 49 indicating the crystal orientation may be formed on the wafer side surface 44 of the SiC semiconductor wafer 41. The multiple (for example, two) orientation flats 49 may include a first orientation flat and a second orientation flat.

[0196] The first orientation flat may be a notch extending linearly along the a-axis direction ([11-20] direction) of the SiC single crystal. The second orientation flat may be a notch extending linearly along the m-axis direction ([1-100] direction) of the SiC single crystal.

[0197] Multiple device formation regions 51, each corresponding to a SiC semiconductor device 1, are set on the first wafer main surface 42 of the SiC semiconductor wafer 41. The multiple device formation regions 51 are set in a matrix arrangement with spacing in the m-axis direction ([1-100] direction) and the a-axis direction ([11-20] direction).

[0198] Each apparatus formation region 51 has four sides 52A, 52B, 52C, and 52D aligned with the crystal orientation of the SiC single crystal. The four sides 52A to 52D correspond to the four sides 5A to 5D of the SiC semiconductor layer 2, respectively. In other words, the four sides 52A to 52D include two sides 52A and 52C aligned with the m-axis direction ([1-100] direction) and two sides 52B and 52D aligned with the a-axis direction ([11-20] direction).

[0199] Multiple apparatus forming regions 51 are each demarcated by grid-like cutting lines 53 extending along the m-axis direction ([1-100] direction) and the a-axis direction ([11-20] direction). The cutting lines 53 include multiple first cutting lines 54 and multiple second cutting lines 55.

[0200] Multiple first cutting lines 54 extend along the m-axis direction ([1-100] direction). Multiple second cutting lines 55 extend along the a-axis direction ([11-20] direction). After predetermined structures are fabricated in multiple device formation regions 51, multiple SiC semiconductor devices 1 are cut out by cutting the SiC semiconductor wafer 41 along the cutting lines 53.

[0201] Figures 10A to 10M are cross-sectional views showing an example of a manufacturing method for the SiC semiconductor device 1 shown in Figure 3. For the sake of explanation, Figures 10A to 10M show only the regions where the three SiC semiconductor devices 1 are formed, and the other regions are omitted from the illustration.

[0202] Referring to Figure 10A, in manufacturing the SiC semiconductor device 1, first a SiC semiconductor wafer 41 is prepared (see also Figure 9). Next, an n-type SiC epitaxial layer 7 is formed on the first wafer main surface 42 of the SiC semiconductor wafer 41.

[0203] In the SiC epitaxial layer 7 formation process, SiC is epitaxially grown from the first wafer main surface 42 of the SiC semiconductor wafer 41. The thickness TE of the SiC epitaxial layer 7 may be 1 μm or more and 50 μm or less.

[0204] This forms a SiC semiconductor wafer structure 61 including a SiC semiconductor wafer 41 and a SiC epitaxial layer 7. The SiC semiconductor wafer structure 61 includes a first main surface 62 and a second main surface 63.

[0205] The first main surface 62 and the second main surface 63 of the SiC semiconductor wafer structure 61 correspond to the first main surface 3 and the second main surface 4 of the SiC semiconductor layer 2, respectively. The thickness TWS of the SiC semiconductor wafer structure 61 may be greater than 150 μm and less than or equal to 800 μm. Preferably, the thickness TWS is greater than 150 μm and less than or equal to 550 μm.

[0206] Next, referring to Figure 10B, p + A p-type guard region 36 is formed. The process of forming the guard region 36 includes selectively introducing p-type impurities to the surface layer of the first main surface 62 of the SiC semiconductor wafer structure 61 via an ion implantation mask (not shown). More specifically, the guard region 36 is formed on the surface layer of the SiC epitaxial layer 7.

[0207] The guard region 36 demarcates the active region 8 and the outer region 9 in the SiC semiconductor wafer structure 61. The region surrounded by the guard region 36 (active region 8) is demarcated to an n-type diode region 35.

[0208] The diode region 35 may be formed by selectively introducing n-type impurities into the surface layer of the first main surface 62 of the SiC semiconductor wafer structure 61 via an ion implantation mask (not shown).

[0209] Next, with reference to Figure 10C, a main surface insulating layer 10 is formed on the first main surface 62 of the SiC semiconductor wafer structure 61. The main surface insulating layer 10 contains silicon oxide (SiO2). The main surface insulating layer 10 may be formed by a CVD (Chemical Vapor Deposition) method or an oxidation treatment method (e.g., a thermal oxidation treatment method).

[0210] Next, referring to Figure 10D, a mask 64 having a predetermined pattern is formed on the main surface insulating layer 10. The mask 64 has a plurality of openings 65. Each of the plurality of openings 65 exposes a region in the main surface insulating layer 10 where a diode opening 37 should be formed.

[0211] Next, unnecessary portions of the main surface insulating layer 10 are removed by etching through the mask 64. This forms diode openings 37 in the main surface insulating layer 10. After the formation of the diode openings 37, the mask 64 is removed.

[0212] Next, referring to Figure 10E, a base electrode layer 66, which will serve as the base for the first main surface electrode layer 12, is formed on the first main surface 62 of the SiC semiconductor wafer structure 61. The base electrode layer 66 is formed over the entire area of ​​the first main surface 62 of the SiC semiconductor wafer structure 61 and covers the main surface insulating layer 10. The first main surface electrode layer 12 may be formed by vapor deposition, sputtering, or plating.

[0213] Next, referring to Figure 10F, a mask 67 having a predetermined pattern is formed on the base electrode layer 66. The mask 67 has an opening 68 that exposes areas of the base electrode layer 66 other than the area where the first main surface electrode layer 12 is to be formed.

[0214] Next, the unnecessary portion of the base electrode layer 66 is removed by etching through the mask 67. This divides the base electrode layer 66 into multiple first main surface electrode layers 12. After the formation of the first main surface electrode layers 12, the mask 67 is removed.

[0215] Next, referring to Figure 10G, a passivation layer 13 is formed on the first main surface 62 of the SiC semiconductor wafer structure 61. The passivation layer 13 contains silicon nitride (SiN). The passivation layer 13 may be formed by the CVD method.

[0216] Next, referring to Figure 10H, a resin layer 16 is applied on the passivation layer 13. The resin layer 16 covers the active region 8 and the outer region 9 together. The resin layer 16 may contain polybenzoxazole as an example of a positive-type photosensitive resin.

[0217] Next, referring to Figure 10I, the resin layer 16 is selectively exposed and then developed. This forms pad openings 18 in the resin layer 16. Additionally, dicing streets 69 are demarcated in the resin layer 16 along the planned cutting lines 53 (sides 52A to 52D of each apparatus forming area 51).

[0218] Next, the unnecessary portion of the passivation layer 13 is removed. The unnecessary portion of the passivation layer 13 may also be removed by etching through the resin layer 16. This forms the sub-pad opening 15 in the passivation layer 13. In addition, a dicing street 69 along the planned cutting line 53 is demarcated in the passivation layer 13.

[0219] In this embodiment, the process of removing unnecessary portions of the passivation layer 13 using the resin layer 16 has been described. However, the resin layer 16 and the pad opening 18 may be formed after the sub-pad opening 15 has been formed in the passivation layer 13.

[0220] In this case, prior to the formation of the resin layer 16, unnecessary portions of the passivation layer 13 are removed by etching via a mask, thereby forming the sub-pad opening 15. This process allows the passivation layer 13 to be formed into any desired shape.

[0221] Next, referring to Figure 10J, the second main surface 63 of the SiC semiconductor wafer structure 61 (the second wafer main surface 43 of the SiC semiconductor wafer 41) is ground. This thins the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41). In addition, grinding marks are formed on the second main surface 63 of the SiC semiconductor wafer structure 61.

[0222] The SiC semiconductor wafer structure 61 is ground down to a thickness TWS corresponding to the thickness TL of the SiC semiconductor layer 2. The SiC semiconductor wafer structure 61 may also be ground down to a thickness TWS of 40 μm or more and 200 μm or less.

[0223] In other words, the SiC semiconductor wafer 41 is ground down to a thickness TW corresponding to the thickness TS of the SiC semiconductor substrate 6. The SiC semiconductor wafer 41 may also be ground down to a thickness TW of 40 μm or more and 150 μm or less.

[0224] Next, referring to Figure 10K, multiple modification lines 70 (modified layers) that form the base of modification lines 22A to 22D are formed. In the modification line 70 formation process, pulsed laser light is irradiated from a laser light irradiation device 71 toward the SiC semiconductor wafer structure 61.

[0225] In this embodiment, the laser light is irradiated onto the SiC semiconductor wafer structure 61 from the first main surface 62 side through the main surface insulating layer 10. Alternatively, the laser light may be irradiated directly onto the SiC semiconductor wafer structure 61 from the second main surface 63 side.

[0226] The focal point of the laser beam is set to a point midway along the thickness of the SiC semiconductor wafer structure 61. The irradiation position of the laser beam onto the SiC semiconductor wafer structure 61 is moved along the planned cutting line 53 (the four sides 52A to 52D of each apparatus formation region 51).

[0227] More specifically, the laser beam irradiation position on the SiC semiconductor wafer structure 61 is moved along the first planned cutting line 54. Furthermore, the laser beam irradiation position on the SiC semiconductor wafer structure 61 is moved along the second planned cutting line 55.

[0228] As a result, multiple modified lines 70 are formed in the middle of the thickness direction of the SiC semiconductor wafer structure 61, extending along the planned cutting lines 53 (the four sides 52A to 52D of each apparatus formation region 51), in which the crystalline state of the SiC single crystal is modified to have different properties from other regions.

[0229] Multiple modification lines 70 are formed in one or more layers, corresponding one-to-one to each of the four sides 52A to 52D of the device formation region 51. In this configuration, multiple (three in this configuration) modification lines 70 are formed on the first planned cutting line 54, and one modification line 70 is formed on the second planned cutting line 55.

[0230] The multiple modification lines 70 formed in the first planned cutting line 54 correspond to modification line 22A (modification line 22C). The single-layer modification line 70 formed in the second planned cutting line 55 corresponds to modification line 22B (modification line 22D).

[0231] The multiple modification lines 70 formed on the first planned cutting line 54 are formed with alternating offsets in the cross-sectional view, with respect to the normal direction Z, to one side and the other side in the a-axis direction. The multiple modification lines 70 formed on the first planned cutting line 54 include one or more modification lines 70 that are offset in the a-axis direction to the opposite side of the c-axis direction of the SiC single crystal ([11-20] direction side) when the modification lines 70 on the second main surface 63 side and / or the modification lines 70 on the first main surface 62 side are used as a reference.

[0232] The two modification lines 70 along sides 52A and 52C of the apparatus formation region 51 each include an a-plane modification section 28. The two modification lines 70 along sides 52B and 52D of the apparatus formation region 51 each include an m-plane modification section 29.

[0233] The multiple modification lines 70 are also laser processing marks formed in the middle of the thickness direction of the SiC semiconductor wafer structure 61. More specifically, the a-plane modification section 28 and the m-plane modification section 29 of the modification line 70 are laser processing marks.

[0234] The laser beam's focusing point, laser energy, pulse duty cycle, irradiation speed, etc., are determined to arbitrary values ​​depending on the position, size, shape, thickness, etc., of the modification line 70 (modification lines 22A to 22D) to be formed.

[0235] Next, referring to FIG. 10L, a second main surface electrode layer 19 is formed on the second main surface 63 of the SiC semiconductor wafer structure 61. The second main surface electrode layer 19 may be formed by vapor deposition, sputtering, or plating.

[0236] Prior to the formation process of the second main surface electrode layer 19, annealing treatment may be performed on the second main surface 63 (grinding surface) of the SiC semiconductor wafer structure 61. The annealing treatment may be performed by a laser annealing treatment method using laser light.

[0237] According to the laser annealing treatment method, the SiC single crystal in the surface layer portion of the second main surface 63 of the SiC semiconductor wafer structure 61 is modified to form a Si amorphous layer. In this case, a SiC semiconductor device 1 having a Si amorphous layer in the surface layer portion of the second main surface 4 of the SiC semiconductor layer 2 is manufactured. On the second main surface 4 of the SiC semiconductor layer 2, grinding marks and a Si amorphous layer coexist. According to the laser annealing treatment method, the ohmic property of the second main surface electrode layer 19 with respect to the second main surface 4 of the SiC semiconductor layer 2 can be enhanced.

[0238] Next, referring to FIG. 10M, a plurality of SiC semiconductor devices 1 are cut out from the SiC semiconductor wafer structure 61. In this process, a tape-shaped support member 73 is adhered to the second main surface 63 side of the SiC semiconductor wafer structure 61.

[0239] Next, an external force is applied to the planned cutting line 53 from the second main surface 63 side of the SiC semiconductor wafer structure 61 through the support member 73. The external force on the planned cutting line 53 may be applied by a pressing member such as a blade.

[0240] In another form, the support member 73 may be adhered to the first main surface 62 side of the SiC semiconductor wafer structure 61. In this case, an external force may be applied to the planned cutting line 53 from the first main surface 62 side of the SiC semiconductor wafer structure 61 through the support member 73. The external force may be applied by a pressing member such as a blade.

[0241] In further embodiments, an expandable support member 73 may be attached to the first main surface 62 side or the second main surface 63 side of the SiC semiconductor wafer structure 61. In this case, the SiC semiconductor wafer structure 61 may be cleaved by stretching the expandable support member 73 in the m-axis direction and the a-axis direction.

[0242] When cleaving the SiC semiconductor wafer structure 61 using the support member 73, it is preferable that the support member 73 be attached to the second main surface 63 side of the SiC semiconductor wafer structure 61 where there are fewer obstacles.

[0243] In this way, the SiC semiconductor wafer structure 61 is cleaved along the planned cutting lines 53 starting from the modification lines 70 (modification lines 22A to 22D), and multiple SiC semiconductor devices 1 are cut out from a single SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41).

[0244] The multiple modification lines 70 formed on the first planned cutting line 54 are formed with alternating offsets in the cross-sectional view, with respect to the normal direction Z, to one side and the other side in the a-axis direction. The straight line connecting at least two of the multiple modification lines 70 formed on the first planned cutting line 54 is inclined from the normal of the first main surface 62 toward the direction opposite to the c-axis of the SiC single crystal.

[0245] The SiC semiconductor wafer structure 61 is cleaved along the first planned cutting line 54, not only along the c-axis direction of the SiC single crystal, but also along a straight line connecting two adjacent modification lines 70. This suppresses the formation of inclined surfaces along the c-axis direction of the SiC single crystal on the side surfaces 5A, 5C of the multiple SiC semiconductor layers 2 cut from the SiC semiconductor wafer structure 61.

[0246] The portion of the modification line 70 that follows the edge 52A of each device formation area 51 becomes modification line 22A. The portion of the modification line 70 that follows the edge 52B of each device formation area 51 becomes modification line 22B. The portion of the modification line 70 that follows the edge 52C of each device formation area 51 becomes modification line 22C. The portion of the modification line 70 that follows the edge 52D of each device formation area 51 becomes modification line 22D. The SiC semiconductor device 1 is manufactured through a process including the above.

[0247] In this configuration, the grinding process of the SiC semiconductor wafer structure 61 (Figure 10J) was performed prior to the formation process of the modification line 70 (modification lines 22A to 22D) (Figure 10K). However, the grinding process of the SiC semiconductor wafer structure 61 (Figure 10J) can be performed at any timing after the preparation process of the SiC semiconductor wafer 41 (Figure 10A) and before the formation process of the second main surface electrode layer 19 (Figure 10L).

[0248] For example, the grinding process of the SiC semiconductor wafer structure 61 (Figure 10J) may be performed prior to the formation process of the SiC epitaxial layer 7 (Figure 10A). Alternatively, the grinding process of the SiC semiconductor wafer structure 61 (Figure 10J) may be performed after the formation process of the modification line 70 (modification lines 22A to 22D) (Figure 10K).

[0249] Furthermore, the grinding process of the SiC semiconductor wafer structure 61 (Figure 10J) may be carried out in multiple steps at any timing after the preparation process of the SiC semiconductor wafer 41 (Figure 10A) and before the formation process of the modification line 70 (modification lines 22A to 22D) (Figure 10K). Also, the grinding process of the SiC semiconductor wafer structure 61 (Figure 10J) may be carried out in multiple steps at any timing after the preparation process of the SiC semiconductor wafer 41 (Figure 10A) and before the formation process of the second main surface electrode layer 19 (Figure 10L).

[0250] Figure 11 is a perspective view showing a semiconductor package 74, into which the SiC semiconductor device 1 shown in Figure 3 is incorporated, through the sealing resin 79.

[0251] Referring to Figure 11, the semiconductor package 74 in this embodiment is a so-called TO-220 type. The semiconductor package 74 includes a SiC semiconductor device 1, a pad portion 75, a heat sink 76, a plurality of (two in this embodiment) terminals 77, a plurality of (two in this embodiment) conductors 78, and a sealing resin 79. The pad portion 75, the heat sink 76, and the plurality of terminals 77 form a lead frame as an example of an object to be connected.

[0252] The pad portion 75 includes a metal plate. The pad portion 75 may also contain iron, gold, silver, copper, aluminum, etc. The pad portion 75 is formed in a rectangular shape in plan view. The pad portion 75 has a planar area greater than or equal to the planar area of ​​the SiC semiconductor device 1. The SiC semiconductor device 1 is placed on the pad portion 75.

[0253] The second main surface electrode layer 19 of the SiC semiconductor device 1 is electrically connected to the pad portion 75 via a conductive bonding material 80. The conductive bonding material 80 is interposed in the region between the second main surface electrode layer 19 and the pad portion 75.

[0254] The conductive bonding material 80 may be a metal paste or solder. The metal paste may be a conductive paste containing Au (gold), Ag (silver), or Cu (copper). Preferably, the conductive bonding material 80 is solder. The solder may be lead-free solder. The solder may contain at least one of SnAgCu, SnZnBi, SnCu, SnCuNi, or SnSbNi.

[0255] The heatsink 76 is connected to one side of the pad portion 75. In this configuration, the pad portion 75 and the heatsink 76 are formed from a single metal plate. The heatsink 76 has a through hole 76a. The through hole 76a is circular in shape.

[0256] Multiple terminals 77 are arranged along the side of the pad portion 75 opposite to the heat sink 76. Each of the multiple terminals 77 includes a metal plate. The terminals 77 may include iron, gold, silver, copper, aluminum, etc.

[0257] The multiple terminals 77 include a first terminal 77A and a second terminal 77B. The first terminal 77A and the second terminal 77B are spaced apart along the side of the pad portion 75 opposite to the heat sink 76. The first terminal 77A and the second terminal 77B extend in a strip-like shape along a direction perpendicular to their arrangement direction.

[0258] The multiple conductors 78 may be bonding wires or the like. The multiple conductors 78 include conductor 78A and conductor 78B. Conductor 78A is electrically connected to the first terminal 77A and the first main surface electrode layer 12 of the SiC semiconductor device 1. Thus, the first terminal 77A is electrically connected to the first main surface electrode layer 12 of the SiC semiconductor device 1 via conductor 78A.

[0259] The conductor 78B is electrically connected to the second terminal 77B and the pad portion 75. As a result, the second terminal 77B is electrically connected to the second main surface electrode layer 19 of the SiC semiconductor device 1 via the conductor 78B. The second terminal 77B may be formed integrally with the pad portion 75.

[0260] The sealing resin 79 seals the SiC semiconductor device 1, the pad portion 75, and the multiple conductors 78, exposing parts of the heat sink 76 and the multiple terminals 77. The sealing resin 79 is formed in a rectangular parallelepiped shape.

[0261] The form of the semiconductor package 74 is not limited to TO-220. As the semiconductor package 74, SOP (Small Outline Package), QFN (Quad For Non Lead Package), DFP (Dual Flat Package), DIP (Dual Inline Package), QFP (Quad Flat Package), SIP (Single Inline Package) or SOJ (Small Outline J-leaded Package), or various forms similar to these may be applied.

[0262] FIG. 12 is a perspective view showing the transport state of the SiC semiconductor device 1 shown in FIG. 3.

[0263] The SiC semiconductor device 1 is mounted on the pad portion 75 of the semiconductor package 74 using a semiconductor assembly device. The transport process of the SiC semiconductor device 1 in the semiconductor assembly device is performed by a pickup nozzle PN that adsorbs and holds the first main surface 3 of the SiC semiconductor layer 2.

[0264] FIG. 13 is a diagram for explaining the structure of the SiC semiconductor device 99 according to the reference example.

[0265] The SiC semiconductor device 99 has the same structure as the SiC semiconductor device 1, except that the side surfaces 5A, 5C of the SiC semiconductor layer 2 have inclined surfaces along the c-axis. For the structure corresponding to the structure described for the SiC semiconductor device 1 in FIG. 13, the same reference numerals are given and the description is omitted.

[0266] The side surfaces 5A, 5C facing the a-plane of the SiC single crystal have the physical property of cleaving with the c-axis of the SiC single crystal as the cleavage direction. Therefore, when a plurality of modification lines 70 (modification lines 22A, 22C) are formed along the normal direction Z of the first main surface 3 or the c-axis of the SiC single crystal, the side surfaces 5A, 5C become inclined surfaces along the c-axis of the SiC single crystal.

[0267] In this case, the apparent planar area S of the SiC semiconductor layer 2 increases by the amount of the planar area corresponding to the inclined surface. More specifically, the apparent planar area S of the SiC semiconductor layer 2 is expressed by equations (1) and (2) below.

[0268] S = SM + SI ... (1) SI = W × TL × tanθ ... (2) In equations (1) and (2) above, "SM" is the planar area of ​​the first main surface 3, "SI" is the planar area increased by the inclined surface, "W" is the length of the side surfaces 5A and 5C of the SiC semiconductor layer 2, and "θ" is the off-angle.

[0269] When the SiC semiconductor device 99, as shown in the reference example, is brought into a semiconductor assembly apparatus, there is a risk that the suction by the pickup nozzle PN will be hindered by the side surfaces 5A and 5C (inclined surfaces) of the SiC semiconductor layer 2. In this case, the pickup nozzle PN will not be able to properly hold the SiC semiconductor device 99, resulting in a pickup error in the semiconductor assembly apparatus.

[0270] In contrast, according to the SiC semiconductor device 1, the side surfaces 5A and 5C facing the a-face of the SiC single crystal in the SiC semiconductor layer 2 have an angle θa less than the off-angle θ with respect to the normal of the first main surface 3, when the normal of the first main surface 3 is set to 0°.

[0271] The angle θa is more specifically defined as 0° or greater and less than the off-angle θ (0° ≤ θa < θ). This allows for a reduction in "SI" in equation (1) above, thereby providing a SiC semiconductor device 1 that can suppress pickup errors in semiconductor assembly equipment.

[0272] Furthermore, in the SiC semiconductor device 1, one or more (one in this embodiment) inclined portions are introduced on the sides 5A and 5C, which are inclined from the normal to the first main surface 3 toward the direction opposite to the c-axis of the SiC single crystal.

[0273] As a result, the formation region of the inclined surface extending along the c-axis is reduced, so that "SI" in the above formula (1) can be reduced. As a result, it is possible to provide the SiC semiconductor device 1 that can suppress the pickup error in the semiconductor assembly apparatus.

[0274] Further, according to the SiC semiconductor device 1, the plurality of modified lines 22A and 22C formed on the side surfaces 5A and 5C are displaced from each other in the a-axis direction of the SiC single crystal in a cross-sectional view. More specifically, the plurality of modified lines 22A and 22C are alternately displaced on one side and the other side in the a-axis direction with respect to the normal direction Z in a cross-sectional view.

[0275] The distance DR between two adjacent modified lines 22A and 22C with respect to the a-axis direction of the SiC single crystal is a value less than TL×tanθ (0 < DR < TL×tanθ) using the off angle θ and the thickness TL of the SiC semiconductor layer 2.

[0276] Further, the distance DD between the two modified lines 22A and 22C that are the farthest apart in the a-axis direction among the plurality of modified lines 22A and 22C is a value less than TL×tanθ (0 < DD < TL×tanθ). Thereby, the inclination width (TL×tanθ) of the side surfaces 5A and 5C can be appropriately reduced. Therefore, "SI" in the above formula (1) can be appropriately reduced.

[0277] Further, according to the SiC semiconductor device 1, the side surfaces 5A and 5C having the angle θa can be realized by six or less modified lines 22A and 22C. Thereby, it is possible to shorten the time required for the formation process of the modified line 70 that is the basis of the modified lines 22A and 22C.

[0278] The SiC single crystal has a physical property that it is easily cracked along the nearest neighbor atom direction (see also FIGS. 1 and 2) in a plan view of the c-plane (silicon plane) seen from the c-axis, and is difficult to crack along the crossing direction of the nearest neighbor atom direction. The nearest neighbor atom direction is the a-axis direction and its equivalent direction. The crossing direction of the nearest neighbor atom direction is the m-axis direction and its equivalent direction.

[0279] Therefore, in the process of forming the modification line 70, the SiC single crystal has a relatively brittle property with respect to the crystal plane along the direction of the nearest neighbor atom, so the SiC single crystal can be appropriately cut (cleaved) even without forming a modification line 70 that occupies a relatively large proportion (see also Figure 10L).

[0280] In other words, in the process of forming the modification line 70, the proportion (number) of modification lines 70 along the second planned cutting line 55 extending in the a-axis direction can be made smaller than the proportion (number) of modification lines 70 along the first planned cutting line 54 extending in the m-axis direction. The crystal planes along the direction of the nearest neighbor atoms are the m-plane and its equivalent planes.

[0281] On the other hand, modification lines 70 with a relatively large proportion (relatively large number) are formed on the crystal planes along the intersecting direction of the nearest nearest atom in the SiC single crystal. This suppresses improper cutting (cleavage) of the SiC semiconductor wafer structure 61, thereby appropriately suppressing the occurrence of cracks caused by the physical properties of the SiC single crystal. The crystal planes along the intersecting direction of the nearest nearest atom are the a-plane and its equivalent planes.

[0282] Thus, with the SiC semiconductor device 1, the proportion and number of modification lines 22A to 22D on the sides 5A to 5D can be adjusted by utilizing the physical properties of the SiC single crystal. This allows for an appropriate reduction in the formation area of ​​modification lines 22A to 22D on the sides 5A to 5D. Therefore, the impact of modification lines 22A to 22D on the SiC semiconductor layer 2 can also be reduced. Furthermore, the formation process time for the modification lines 70 can be shortened.

[0283] Examples of effects on the SiC semiconductor layer 2 due to the modification line include fluctuations in the electrical properties of the SiC semiconductor layer 2 caused by the modification line, and the generation of cracks in the SiC semiconductor layer 2 originating from the modification line.

[0284] Fluctuations in leakage current characteristics are exemplified as fluctuations in the electrical characteristics of the SiC semiconductor layer 2 caused by the modification line. The SiC semiconductor device may be sealed with a sealing resin 79, as shown in Figure 11.

[0285] In this case, it is conceivable that mobile ions in the sealing resin 79 could enter the SiC semiconductor layer 2 via the modification lines. In a structure where multiple modification lines are formed at intervals along the normal direction Z across the entire area of ​​each side surface 5A to 5D, the risk of current path formation due to such external structures increases.

[0286] Furthermore, in a structure where multiple modification lines are formed along the normal direction Z across the entire area of ​​each side surface 5A to 5D of the SiC semiconductor layer 2, the risk of crack formation in the SiC semiconductor layer 2 also increases. Therefore, as in the SiC semiconductor device 1, by limiting the formation area of ​​the modification lines 22A to 22D, fluctuations in the electrical properties of the SiC semiconductor layer 2 and the occurrence of cracks can be suppressed.

[0287] Furthermore, since the SiC semiconductor device 1 performs a thinning process on the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41), the SiC semiconductor wafer structure 61 can be properly cleaved by a small number of modification lines 70 (modification lines 22A to 22D), for example, 6 or fewer lines (preferably 3 or fewer lines).

[0288] In other words, with a thinned SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41), the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41) can be properly cleaved without forming modification lines 70 (modification lines 22A to 22D) at intervals in the normal direction Z across the entire thickness direction of the SiC semiconductor wafer structure 61.

[0289] In this case, the second main surface 4 of the SiC semiconductor layer 2 is a ground surface. The SiC semiconductor device 1 preferably includes a SiC semiconductor layer 2 having a thickness TL of 40 μm or more and 200 μm or less. A SiC semiconductor layer 2 having such a thickness TL can be appropriately cut from a SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41).

[0290] In the SiC semiconductor layer 2, the thickness TS of the SiC semiconductor substrate 6 may be between 40 μm and 150 μm. In the SiC semiconductor layer 2, the thickness TE of the SiC epitaxial layer 7 may be between 1 μm and 50 μm. Thinning the SiC semiconductor layer 2 is also effective in reducing the resistance value.

[0291] Furthermore, in the SiC semiconductor device 1, the modification lines 22A to 22D are formed at intervals from the first main surface 3 to the second main surface 4 of the SiC semiconductor layer 2. Stress tends to concentrate at the corners connecting the first main surface 3 and the side surfaces 5A to 5D of the SiC semiconductor layer 2.

[0292] Therefore, by forming modification lines 22A to 22D at intervals from the corners connecting the first main surface 3 and side surfaces 5A to 5D of the SiC semiconductor layer 2, the occurrence of cracks at the corners of the SiC semiconductor layer 2 can be appropriately suppressed.

[0293] In particular, in the SiC semiconductor device 1, the modification lines 22A to 22D are formed on the SiC semiconductor substrate 6 while avoiding the SiC epitaxial layer 7. In other words, the modification lines 22A to 22D expose the SiC epitaxial layer 7 on which the main part of the semiconductor device (Schottky barrier diode D in this configuration) is formed. This allows for an appropriate reduction in the impact of the modification lines 22A to 22D on the semiconductor device.

[0294] Furthermore, in the SiC semiconductor device 1, the modification lines 22A to 22D are formed at intervals from the second main surface 4 to the first main surface 3 of the SiC semiconductor layer 2. Stress tends to concentrate at the corners connecting the second main surface 4 and the side surfaces 5A to 5D of the SiC semiconductor layer 2.

[0295] Therefore, by forming modification lines 22A to 22D at intervals from the corners connecting the second main surface 4 and side surfaces 5A to 5D of the SiC semiconductor layer 2, the occurrence of cracks at the corners of the SiC semiconductor layer 2 can be appropriately suppressed.

[0296] Furthermore, the SiC semiconductor device 1 includes a main surface insulating layer 10 and a first main surface electrode layer 12 formed on the first main surface 3 of the SiC semiconductor layer 2. The main surface insulating layer 10 has insulating side surfaces 11A to 11D that are connected to the side surfaces 5A to 5D of the SiC semiconductor layer 2.

[0297] The main surface insulating layer 10 enhances the insulation between the side surfaces 5A to 5D of the SiC semiconductor layer 2 and the first main surface electrode layer 12 in a structure in which the modification lines 22A to 22D are formed. This enhances the stability of the electrical properties of the SiC semiconductor layer 2 in a structure in which the modification lines 22A to 22D are formed on the side surfaces 5A to 5D of the SiC semiconductor layer 2.

[0298] Figure 14A is a perspective view showing the SiC semiconductor device 1 shown in Figure 3, and is a perspective view showing a second embodiment example of modification lines 22A to 22D. In the following, structures corresponding to the structures described for the SiC semiconductor device 1 are given the same reference numerals and their explanations are omitted.

[0299] In the first embodiment, the modification lines 22B and 22D are formed in a strip shape that extends linearly along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. In contrast, in the second embodiment, the modification lines 22B and 22D are formed in a strip shape that extends in a downward sloping manner from the first main surface 3 to the second main surface 4 of the SiC semiconductor layer 2. More specifically, the modification lines 22B and 22D in the second embodiment include a first end region 81, a second end region 82, and a sloping region 83, respectively.

[0300] The first end region 81 is located near the corner of the SiC semiconductor layer 2, on the side of the first main surface 3 of the SiC semiconductor layer 2. The second end region 82 is located near the corner of the SiC semiconductor layer 2, on the side of the second main surface 4 of the SiC semiconductor layer 2 relative to the first end region 81.

[0301] The inclined region 83 slopes downward from the first main surface 3 to the second main surface 4 in the region between the first end region 81 and the second end region 82. The inclination direction and angle of the modification lines 22B and 22D are arbitrary and are not limited to the configuration shown in Figure 14A.

[0302] The modification lines 22B and 22D according to the second embodiment are formed by adjusting the focusing part (focus) of the laser beam during the formation process of the modification line 70 (modification lines 22B and 22D) (see also Figure 10K). Even when the modification lines 22B and 22D according to the second embodiment are formed, the same effects as when the modification lines 22A to 22D according to the first embodiment are formed can be achieved.

[0303] In particular, according to the modification lines 22B and 22D of the second embodiment, cleavage starting points can be formed in different regions in the thickness direction of the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41). As a result, even when forming modification lines 22B and 22D consisting of a single layer, the SiC semiconductor wafer structure 61 can be properly cleaved.

[0304] Of course, the modification lines 22A and 22C may also be formed in the same way as the modification lines 22B and 22D, as a band extending in an inclined manner from the first main surface 3 to the second main surface 4. In other words, the modification lines 22A and 22C may each include a first end region 81, a second end region 82, and an inclined region 83, respectively.

[0305] However, since it is assumed that multiple modification lines 22A and 22C are formed on the sides 5A and 5C, there is little need to deliberately tilt the modification line 70 during laser irradiation.

[0306] Figure 14B is a perspective view showing the SiC semiconductor device 1 shown in Figure 3, and is a perspective view showing a third embodiment example of modification lines 22A to 22D. In the following, structures corresponding to the structures described for the SiC semiconductor device 1 are given the same reference numerals and their explanations are omitted.

[0307] In the first embodiment, the modification lines 22B and 22D are formed in a strip shape that extends linearly along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. In contrast, in the third embodiment, the modification lines 22B and 22D are formed in a strip shape that slopes downward from the first main surface 3 to the second main surface 4 of the SiC semiconductor layer 2 and extends in a curved (curved) shape. More specifically, the modification lines 22B and 22D in the third embodiment include a first end region 84, a second end region 85, and a curved region 86, respectively.

[0308] The first end region 84 is located near the corner of the SiC semiconductor layer 2, on the side of the first main surface 3 of the SiC semiconductor layer 2. The second end region 85 is located near the corner of the SiC semiconductor layer 2, on the side of the second main surface 4 of the SiC semiconductor layer 2 relative to the first end region 84.

[0309] The curved region 86 slopes downward in a concave curve from the first main surface 3 to the second main surface 4, connecting the first end region 84 and the second end region 85. The inclination direction and angle of the modification lines 22B and 22D are arbitrary and are not limited to the configuration shown in Figure 14B.

[0310] The modification lines 22B and 22D according to the third embodiment are formed by adjusting the focusing portion (focus) of the laser beam during the formation process of the modification line 70 (modification lines 22B and 22D) (see also Figure 10K). Even when the modification lines 22B and 22D according to the third embodiment are formed, the same effects as when the modification lines 22A to 22D according to the first embodiment are formed can be achieved.

[0311] In particular, according to the modification lines 22B and 22D of the third embodiment, cleavage starting points can be formed in different regions in the thickness direction of the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41). As a result, even when forming modification lines 22B and 22D consisting of a single layer, the SiC semiconductor wafer structure 61 can be properly cleaved.

[0312] Of course, the modification lines 22A and 22C may also be sloped downward in a concave curve from the first main surface 3 to the second main surface 4, similar to the modification lines 22B and 22D. In other words, the modification lines 22A and 22C may each include a first end region 84, a second end region 85, and a curved region 86, respectively.

[0313] However, since it is assumed that multiple modification lines 22A and 22C are formed on the sides 5A and 5C, there is little need to implement control to deliberately tilt the modification line 70 when irradiated with laser light.

[0314] Figure 14C is a perspective view showing the SiC semiconductor device 1 shown in Figure 3, and is a perspective view showing a fourth embodiment example of modification lines 22A to 22D. In the following, structures corresponding to the structures described for the SiC semiconductor device 1 are given the same reference numerals and their explanations are omitted.

[0315] In the first embodiment, the modified lines 22B and 22D are formed in a strip shape that extends linearly along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. In contrast, in the fourth embodiment, the modified lines 22B and 22D are formed in a strip shape that slopes downward from the first main surface 3 to the second main surface 4 of the SiC semiconductor layer 2 and extends in a curved (bent) shape. In the third embodiment, the modified lines 22B and 22D more specifically include a first end region 84, a second end region 85, and a curved region 86, respectively.

[0316] The first end region 84 is located near the corner of the SiC semiconductor layer 2, on the side of the first main surface 3 of the SiC semiconductor layer 2. The second end region 85 is located near the corner of the SiC semiconductor layer 2, on the side of the second main surface 4 of the SiC semiconductor layer 2 relative to the first end region 84.

[0317] The curved region 86 slopes downward in a convex curve from the second main surface 4 toward the first main surface 3, connecting the first end region 84 and the second end region 85. The inclination direction and angle of the modification lines 22B and 22D are arbitrary and are not limited to the configuration shown in Figure 14C.

[0318] The modification lines 22B and 22D according to the fourth embodiment are formed by adjusting the focusing part (focus) of the laser beam during the formation process of the modification line 70 (modification lines 22B and 22D) (see also Figure 10K). Even when the modification lines 22B and 22D according to the fourth embodiment are formed, the same effects as when the modification lines 22A to 22D according to the first embodiment are formed can be achieved.

[0319] In particular, according to the modification lines 22B and 22D of the fourth embodiment, cleavage starting points can be formed in different regions in the thickness direction of the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41). As a result, even when forming modification lines 22B and 22D consisting of a single layer, the SiC semiconductor wafer structure 61 can be properly cleaved.

[0320] Of course, the modification lines 22A and 22C may also have a downward slope in a convex curved shape from the second main surface 4 toward the first main surface 3, similar to the modification lines 22B and 22D. In other words, the modification lines 22A and 22C may each include a first end region 84, a second end region 85, and a curved region 86, respectively.

[0321] However, since it is assumed that multiple modification lines 22A and 22C are formed on the sides 5A and 5C, there is little need to implement control to deliberately tilt the modification line 70 when irradiated with laser light.

[0322] Figure 14D is a perspective view showing the SiC semiconductor device 1 shown in Figure 3, and is a perspective view showing a fifth embodiment example of modification lines 22A to 22D. In the following, structures corresponding to the structures described for the SiC semiconductor device 1 are given the same reference numerals and their explanations are omitted.

[0323] In the first embodiment, the modification lines 22B and 22D are formed in a strip shape that extends linearly along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. In contrast, in the fifth embodiment, the modification lines 22B and 22D are formed in a strip shape that extends in a meandering curved (curved) manner toward the first main surface 3 and the second main surface 4 of the SiC semiconductor layer 2. More specifically, the modification lines 22B and 22D in the fifth embodiment include a plurality of first regions 87, a plurality of second regions 88, and a plurality of connection regions 89, respectively.

[0324] Multiple first regions 87 are located in the region of the SiC semiconductor layer 2 on the first main surface 3 side. Multiple second regions 88 are located in the region of the SiC semiconductor layer 2 on the second main surface 4 side relative to the multiple first regions 87. Multiple curved regions 86 connect the corresponding first regions 87 and second regions 88, respectively.

[0325] The meandering period of the modification lines 22B and 22D is arbitrary. The modification lines 22B and 22D may each be formed as a single strip extending in a concave curve from the first main surface 3 to the second main surface 4. In this case, the modification lines 22B and 22D may each include two first regions 87, one second region 88, and two connecting regions 89.

[0326] Furthermore, the modification lines 22B and 22D may each be formed as a single strip extending in a convex curve from the second main surface 4 toward the first main surface 3. In this case, the modification lines 22B and 22D may each include one first region 87, two second regions 88, and two connecting regions 89.

[0327] The modification lines 22B and 22D according to the fifth embodiment are formed by adjusting the focusing portion (focus) of the laser beam during the formation process of the modification line 70 (modification lines 22B and 22D) (see also Figure 10K). Even when the modification lines 22B and 22D according to the fifth embodiment are formed, the same effects as when the modification lines 22A to 22D according to the first embodiment are formed can be achieved.

[0328] In particular, according to the fifth embodiment, the modification lines 22B and 22D can form cleavage starting points in different regions in the thickness direction of the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41). As a result, even when forming modification lines 22B and 22D consisting of a single layer, the SiC semiconductor wafer structure 61 can be properly cleaved.

[0329] Of course, the reforming lines 22A and 22C may also be formed in the same way as the reforming lines 22B and 22D, extending in a meandering, curved (bent) shape toward the first main surface 3 and second main surface 4 of the SiC semiconductor layer 2. In other words, the reforming lines 22A and 22C may each include a first region 87, a second region 88, and a connecting region 89, respectively.

[0330] However, since it is assumed that multiple modification lines 22A and 22C are formed on the sides 5A and 5C, there is little need to implement control to deliberately cause the modification line 70 to meander when irradiated with laser light.

[0331] A SiC semiconductor device 1 may be formed that simultaneously includes at least two of the modification lines 22A to 22D related to the first, second, third, fourth, and fifth embodiments (hereinafter simply referred to as "first to fifth embodiments").

[0332] Furthermore, the features of the modification lines 22A to 22D according to the first to fifth embodiments can be combined in any manner and in any form among them. In other words, modification lines 22A to 22D having a form in which at least two of the features of the modification lines 22A to 22D according to the first to fifth embodiments are combined may be adopted.

[0333] Figure 15 is a perspective view showing a SiC semiconductor device 91 according to a second embodiment of the present disclosure, and is a perspective view showing a structure to which modification lines 22A to 22D according to the first embodiment are applied. In the following, structures corresponding to the structure described for the SiC semiconductor device 1 are denoted by the same reference numerals and their descriptions are omitted.

[0334] In this configuration, the modification lines 22A to 22D according to the first configuration example are applied. However, the modification lines 22A to 22D according to the second, third, fourth, or fifth configuration example may be used instead of or in addition to the modification lines 22A to 22D according to the first configuration example. Furthermore, modification lines 22A to 22D having a configuration that combines at least two of the features of the modification lines 22A to 22D according to the first to fifth configuration examples may be used.

[0335] Referring to Figure 15, in this configuration, the insulating side surfaces 11A to 11D of the main surface insulating layer 10 are formed with a gap in the inward region from the side surfaces 5A to 5D of the SiC semiconductor layer 2 in a plan view. The main surface insulating layer 10 exposes the peripheral edge of the first main surface 3 of the SiC semiconductor layer 2 in a plan view.

[0336] The main surface insulating layer 10, together with the resin layer 16 and the passivation layer 13, exposes the peripheral edge of the first main surface 3 of the SiC semiconductor layer 2. In this configuration, the insulating sides 11A to 11D of the main surface insulating layer 10 are formed flush with the resin sides 17A to 17D of the resin layer 16 and the sides 14A to 14D of the passivation layer 13. In this configuration, the insulating sides 11A to 11D of the main surface insulating layer 10 also constitute the portion that demarcates the dicing street.

[0337] This main surface insulating layer 10 is formed in the process shown in Figure 10I above, by performing a step of removing the main surface insulating layer 10 by etching after the step of removing the passivation layer 13.

[0338] In this case, in the process shown in Figure 10K above, laser light may be directly irradiated into the interior of the SiC semiconductor wafer structure 61 from the first main surface 62 side of the SiC semiconductor wafer structure 61 without going through the main surface insulating layer 10.

[0339] As described above, the SiC semiconductor device 91 can achieve the same effects as those described for the SiC semiconductor device 1. However, the structure of the SiC semiconductor device 1 according to the first embodiment is preferred for improving the insulation between the side surfaces 5A to 5D of the SiC semiconductor layer 2 and the first main surface electrode layer 12.

[0340] Figure 16 is a perspective view of the SiC semiconductor device 101 according to the third embodiment of this disclosure, viewed from one angle, showing a structure to which the modification lines 22A to 22D according to the first embodiment are applied. Figure 17 is a perspective view of the SiC semiconductor device 101 shown in Figure 16, viewed from a different angle. Figure 18 is a plan view of the SiC semiconductor device 101 shown in Figure 16. Figure 19 is a plan view of Figure 18 with the resin layer 129 removed.

[0341] In this configuration, the modification lines 22A to 22D described in the first configuration example are applied. In other words, the manufacturing process for the SiC semiconductor device 101 is the same as the process described in Figures 10A to 10M above.

[0342] In the SiC semiconductor device 101, the modification lines 22A to 22D according to the second, third, fourth, or fifth embodiment may be used instead of or in addition to the modification lines 22A to 22D according to the first embodiment. Furthermore, modification lines 22A to 22D having a configuration that combines at least two of the features of the modification lines 22A to 22D according to the first to fifth embodiments may be used.

[0343] Referring to Figures 16 to 19, the SiC semiconductor device 101 includes a SiC semiconductor layer 102. The SiC semiconductor layer 102 includes a 4H-SiC single crystal as an example of a hexagonal SiC single crystal. The SiC semiconductor layer 102 is formed in the shape of a rectangular parallelepiped chip.

[0344] The SiC semiconductor layer 102 has a first main surface 103 on one side, a second main surface 104 on the other side, and sides 105A, 105B, 105C, and 105D connecting the first main surface 103 and the second main surface 104. The first main surface 103 and the second main surface 104 are formed in a quadrilateral shape (rectangular in this form) when viewed in a plan view from their normal direction Z (hereinafter simply referred to as "plan view").

[0345] The first main surface 103 is the element formation surface on which the semiconductor element is formed. The second main surface 104 of the SiC semiconductor layer 102 consists of a ground surface with grinding marks. The side surfaces 105A to 105D each consist of smooth cleavage planes facing the crystal plane of the SiC single crystal. Side surfaces 105A to 105D do not have grinding marks.

[0346] The thickness TL of the SiC semiconductor layer 102 may be 40 μm or more and 200 μm or less. The thickness TL may be 40 μm or more and 60 μm or less, 60 μm or more and 80 μm or less, 80 μm or more and 100 μm or less, 100 μm or more and 120 μm or less, 120 μm or more and 140 μm or less, 140 μm or more and 160 μm or less, 160 μm or more and 180 μm or less, or 180 μm or more and 200 μm or less. Preferably, the thickness TL is 60 μm or more and 150 μm or less.

[0347] In this embodiment, the first principal surface 103 and the second principal surface 104 face the c-plane of the SiC single crystal. The first principal surface 103 faces the (0001) plane (silicon plane). The second principal surface 104 faces the (000-1) plane (carbon plane) of the SiC single crystal.

[0348] The first principal surface 103 and the second principal surface 104 have an off-angle θ that is inclined at an angle of 10° or less in the [11-20] direction with respect to the c-plane of the SiC single crystal. The normal direction Z is inclined by the off-angle θ with respect to the c-axis (

[0001] direction) of the SiC single crystal.

[0349] The off-angle θ may be between 0° and 5.0°. The off-angle θ may be set within the range of angles between 0° and 1.0°, 1.0° and 1.5°, 1.5° and 2.0°, 2.0° and 2.5°, 2.5° and 3.0°, 3.0° and 3.5°, 3.5° and 4.0°, 4.0° and 4.5°, or 4.5° and 5.0°. It is preferable that the off-angle θ is greater than 0°. The off-angle θ may be less than 4.0°.

[0350] The off-angle θ may be set to an angle range of 3.0° or more and 4.5° or less. In this case, it is preferable that the off-angle θ is set to an angle range of 3.0° or more and 3.5° or less and 3.5° or more and 4.0° or less.

[0351] The off-angle θ may be set to an angle range of 1.5° or more and 3.0° or less. In this case, it is preferable that the off-angle θ is set to an angle range of 1.5° or more and 2.0° or more and 2.5° or less.

[0352] The lengths of sides 105A to 105D may be between 1 mm and 10 mm (for example, between 2 mm and 5 mm). In this configuration, the surface areas of sides 105B and 105D exceed the surface areas of sides 105A and 105C. The first main surface 103 and the second main surface 104 may be formed in a square shape in plan view. In this case, the surface areas of sides 105A and 105C are equal to those of sides 105B and 105D.

[0353] In this embodiment, sides 105A and 105C extend along a first direction X and face each other in a second direction Y that intersects the first direction X. Sides 105B and 105D extend along a second direction Y and face each other in a first direction X. More specifically, the second direction Y is perpendicular to the first direction X.

[0354] In this configuration, the first direction X is set to the m-axis direction ([1-100] direction) of the SiC single crystal. The second direction Y is set to the a-axis direction ([11-20] direction) of the SiC single crystal.

[0355] Sides 105A and 105C form the short sides of the SiC semiconductor layer 102 in a plan view. Sides 105A and 105C are formed by the a-planes of the SiC single crystal and face each other in the a-axis direction. Side 105A is formed by the (-1-120) plane of the SiC single crystal. Side 105C is formed by the (11-20) plane of the SiC single crystal.

[0356] Sides 105B and 105D form the long sides of the SiC semiconductor layer 102 in a plan view. Sides 105B and 105D are formed by the m-planes of the SiC single crystal and face each other in the m-axis direction. Side 105B is formed by the (-1100) plane of the SiC single crystal. Side 105D is formed by the (1-100) plane of the SiC single crystal.

[0357] Side surfaces 105A and 105C may form inclined surfaces that are tilted in the c-axis direction (

[0001] direction) of the SiC single crystal with respect to the normal, when the normal to the first main surface 103 of the SiC semiconductor layer 102 is used as a reference.

[0358] In this case, the sides 105A and 105C may be inclined at an angle corresponding to the off-angle θ with respect to the normal to the first main surface 103 of the SiC semiconductor layer 102, when the normal to the first main surface 103 of the SiC semiconductor layer 102 is set to 0°. The angle corresponding to the off-angle θ may be equal to the off-angle θ, or it may be an angle greater than 0° and less than the off-angle θ.

[0359] In this configuration, the SiC semiconductor layer 102 is n +The structure has a laminated form including an n-type SiC semiconductor substrate 106 and an n-type SiC epitaxial layer 107. The SiC semiconductor substrate 106 and the SiC epitaxial layer 107 correspond to the SiC semiconductor substrate 6 and the SiC epitaxial layer 7 according to the first embodiment, respectively. The second main surface 104 of the SiC semiconductor layer 102 is formed by the SiC semiconductor substrate 106.

[0360] The first main surface 103 of the SiC semiconductor layer 102 is formed by the SiC epitaxial layer 107. The side surfaces 105A to 105D of the SiC semiconductor layer 102 are formed by the SiC semiconductor substrate 106 and the SiC epitaxial layer 107.

[0361] The thickness TS of the SiC semiconductor substrate 106 may be 40 μm or more and 150 μm or less. The thickness TS may be 40 μm or more and 50 μm or less, 50 μm or more and 60 μm or less, 60 μm or more and 70 μm or less, 70 μm or more and 80 μm or less, 80 μm or more and 90 μm or less, 90 μm or more and 100 μm or less, 100 μm or more and 110 μm or less, 110 μm or more and 120 μm or less, 120 μm or more and 130 μm or less, 130 μm or more and 140 μm or more and 150 μm or less. It is preferable that the thickness TS is 40 μm or more and 130 μm or less. By thinning the SiC semiconductor substrate 106, the resistance value can be reduced by shortening the current path.

[0362] The thickness TE of the SiC epitaxial layer 107 may be 1 μm or more and 50 μm or less. The thickness TE may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 35 μm or less, 35 μm or more and 40 μm or less, 40 μm or more and 45 μm or less, or 45 μm or more and 50 μm or less. Preferably, the thickness TE is 5 μm or more and 15 μm or less.

[0363] The n-type impurity concentration in the SiC epitaxial layer 107 is less than or equal to the n-type impurity concentration in the SiC semiconductor substrate 106. More specifically, the n-type impurity concentration in the SiC epitaxial layer 107 is less than the n-type impurity concentration in the SiC semiconductor substrate 106. The n-type impurity concentration in the SiC semiconductor substrate 106 is 1.0 × 10⁻⁶ 18 cm -3 The above 1.0 × 10 21 cm -3 The following may also apply: The n-type impurity concentration in the SiC epitaxial layer 107 is 1.0 × 10⁻⁶. 15 cm -3 The above 1.0 × 10 18 cm -3 The following is also acceptable.

[0364] In this embodiment, the SiC epitaxial layer 107 has multiple regions having different n-type impurity concentrations along the normal direction Z. More specifically, the SiC epitaxial layer 107 includes a high-concentration region 108 with a relatively high n-type impurity concentration, and a low-concentration region 109 with a lower n-type impurity concentration compared to the high-concentration region 108.

[0365] The high-concentration region 108 is formed in the region of the SiC semiconductor layer 102 on the side of the first main surface 103. The low-concentration region 109 is formed in the region of the SiC semiconductor layer 102 on the side of the second main surface 104 relative to the high-concentration region 108.

[0366] The n-type impurity concentration in the high-concentration region 10⁸ is 1 × 10⁸. 16 cm -3 The above 1 x 10 18 cm -3 The following may also apply: The n-type impurity concentration in the low concentration region 10⁹ is 1 × 10⁻⁶. 15 cm -3 The above 1 x 10 16 cm -3 The following is also acceptable.

[0367] The thickness of the high-concentration region 108 is less than or equal to the thickness of the low-concentration region 109. More specifically, the thickness of the high-concentration region 108 is less than the thickness of the low-concentration region 109. The thickness of the high-concentration region 108 is less than half the total thickness of the SiC epitaxial layer 107.

[0368] The SiC semiconductor layer 102 has an active region 111 and an outer region 112. The active region 111 is the region where a vertical MISFET (Metal Insulator Field Effect Transistor), an example of a semiconductor device, is formed. The outer region 112 is the region outside the active region 111.

[0369] The active region 111 is located in the center of the SiC semiconductor layer 102, with a gap in the inward region from the sides 105A to 105D of the SiC semiconductor layer 102 in a plan view. The active region 111 is set in a quadrilateral shape (rectangular in this form) with four sides parallel to the sides 105A to 105D of the SiC semiconductor layer 102 in a plan view.

[0370] The outer region 112 is defined as the region between the side surfaces 105A to 105D of the SiC semiconductor layer 102 and the periphery of the active region 111. In a plan view, the outer region 112 is defined as an endless shape (a rectangular ring in this configuration) surrounding the active region 111.

[0371] A main surface insulating layer 113 is formed on the first main surface 103 of the SiC semiconductor layer 102. The main surface insulating layer 113 selectively covers the active region 111 and the outer region 112. The main surface insulating layer 113 may contain silicon oxide (SiO2).

[0372] The main surface insulating layer 113 has insulating side surfaces 114A, 114B, 114C, and 114D that are exposed from the side surfaces 105A to 105D of the SiC semiconductor layer 102. The insulating side surfaces 114A to 114D are continuous with the side surfaces 105A to 105D. The insulating side surfaces 114A to 114D are formed flush with the side surfaces 105A to 105D. The insulating side surfaces 114A to 114D consist of cleavage surfaces.

[0373] The thickness of the main surface insulating layer 113 may be 1 μm or more and 50 μm or less. The thickness of the main surface insulating layer 113 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

[0374] A main surface gate electrode layer 115 is formed on the main surface insulating layer 113 as one of the first main surface electrode layers. The main surface gate electrode layer 115 penetrates the main surface insulating layer 113 and is electrically connected to any region of the SiC semiconductor layer 102.

[0375] The main surface gate electrode layer 115 includes a gate pad 116 and gate fingers 117, 118. The gate pad 116 and gate fingers 117, 118 are located in the active region 111.

[0376] The gate pad 116 is formed along the side surface 105A of the SiC semiconductor layer 102 in a plan view. The gate pad 116 is formed along the central region of the side surface 105A of the SiC semiconductor layer 102 in a plan view.

[0377] The gate pad 116 may be formed along the corner connecting any two of the sides 105A to 105D of the SiC semiconductor layer 102 in a plan view. The gate pad 116 may be formed in a square shape in a plan view.

[0378] The gate fingers 117, 118 include an outer gate finger 117 and an inner gate finger 118. The outer gate finger 117 extends from the gate pad 116 and extends in a band along the periphery of the active region 111.

[0379] In this embodiment, the outer gate finger 117 is formed along the three sides 105A, 105B, and 105D of the SiC semiconductor layer 102 so as to divide the inner region of the active region 111 from three directions.

[0380] The outer gate finger 117 has a pair of open ends 119, 120. The pair of open ends 119, 120 are formed in the region facing the gate pad 116, with the inner region of the active region 111 in between. In this embodiment, the pair of open ends 119, 120 are formed along the side surface 105C of the SiC semiconductor layer 102.

[0381] The inner gate finger 118 is drawn out from the gate pad 116 into the inner region of the active region 111. The inner gate finger 118 extends in a band-like manner within the inner region of the active region 111. The inner gate finger 118 extends from the gate pad 116 toward the side surface 105C.

[0382] A main surface source electrode layer 121 is further formed on the main surface insulating layer 113 as one of the first main surface electrode layers. The main surface source electrode layer 121 penetrates the main surface insulating layer 113 and is electrically connected to any region of the SiC semiconductor layer 102. In this embodiment, the main surface source electrode layer 121 includes a source pad 122, source routing 123, and a source connection portion 124.

[0383] The source pad 122 is formed in the active region 111, spaced apart from the gate pads 116 and gate fingers 117, 118. The source pad 122 is formed in a C-shape (inverted C-shape in Figures 18 and 19) in plan view so as to cover the C-shaped region (inverted C-shape in Figures 18 and 19) demarcated by the gate pads 116 and gate fingers 117, 118.

[0384] The source routing 123 is formed in the outer region 112. The source routing 123 extends in a strip shape along the active region 111. In this configuration, the source routing 123 is formed in an endless shape (a rectangular ring in this configuration) surrounding the active region 111 in a plan view. The source routing 123 is electrically connected to the SiC semiconductor layer 102 in the outer region 112.

[0385] The source connection section 124 connects the source pad 122 and the source routing wiring 123. The source connection section 124 is located in the region between the pair of open ends 119 and 120 of the outer gate finger 117. The source connection section 124 extends from the source pad 122 across the boundary region between the active region 111 and the outer region 112 and connects to the source routing wiring 123.

[0386] The MISFET formed in the active region 111 contains, due to its structure, an npn-type parasitic bipolar transistor. When an avalanche current generated in the outer region 112 flows into the active region 111, the parasitic bipolar transistor turns on. In this case, the control of the MISFET may become unstable, for example, due to latch-up.

[0387] Therefore, in the SiC semiconductor device 101, an avalanche current absorption structure is formed by utilizing the structure of the main surface source electrode layer 121 to absorb the avalanche current generated in the outer region 112.

[0388] More specifically, the avalanche current generated in the outer region 112 is absorbed by the source routing wiring 123 and reaches the source pad 122 via the source connection 124. If an external connection wire (e.g., bonding wire) is connected to the source pad 122, the avalanche current is extracted by this wire.

[0389] This prevents the parasitic bipolar transistor from being turned on by unwanted currents generated in the outer region 112. Therefore, latch-up can be suppressed, and the control stability of the MISFET can be improved.

[0390] A gate voltage is applied to the main surface gate electrode layer 115. The gate voltage may be between 10V and 50V (for example, around 30V). A source voltage is applied to the main surface source electrode layer 121. The source voltage may be a reference voltage (for example, GND voltage).

[0391] A passivation layer 125 (insulating layer) is formed on the main surface insulating layer 113. The passivation layer 125 may have a single-layer structure consisting of a silicon oxide layer or a silicon nitride layer.

[0392] The passivation layer 125 may have a laminated structure including a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may be formed on top of the silicon nitride layer. The silicon nitride layer may be formed on top of the silicon oxide layer. In this embodiment, the passivation layer 125 has a single-layer structure consisting of a silicon nitride layer.

[0393] The side surfaces 126A, 126B, 126C, and 126D of the passivation layer 125 are formed with a gap in the inward region from the side surfaces 105A to 105D of the SiC semiconductor layer 102 in a plan view. The passivation layer 125 exposes the peripheral edge of the SiC semiconductor layer 102 in a plan view. The passivation layer 125 exposes the main surface insulating layer 113.

[0394] The passivation layer 125 selectively covers the main surface gate electrode layer 115 and the main surface source electrode layer 121. The passivation layer 125 has a gate subpad opening 127 and a source subpad opening 128. The gate subpad opening 127 exposes the gate pad 116. The source subpad opening 128 exposes the source pad 122.

[0395] The thickness of the passivation layer 125 may be 1 μm or more and 50 μm or less. The thickness of the passivation layer 125 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

[0396] A resin layer 129 (insulating layer) is formed on top of the passivation layer 125. The passivation layer 125 and the resin layer 129 form a single insulating laminated structure (insulating layer). In Figure 18, the resin layer 129 is indicated by hatching.

[0397] The resin layer 129 may contain a negative-type or positive-type photosensitive resin. In this embodiment, the resin layer 129 contains polybenzoxazole as an example of a positive-type photosensitive resin. The resin layer 129 may also contain polyimide as an example of a negative-type photosensitive resin.

[0398] The resin layer 129 selectively covers the main surface gate electrode layer 115 and the main surface source electrode layer 121. The resin sides 130A, 130B, 130C, and 130D of the resin layer 129 are formed with a gap inward from the sides 105A to 105D of the SiC semiconductor layer 102. The resin layer 129, together with the passivation layer 125, exposes the main surface insulating layer 113. In this configuration, the resin sides 130A to 130D of the resin layer 129 are formed flush with the sides 126A to 126D of the passivation layer 125.

[0399] The resin side surfaces 130A to 130D of the resin layer 129 are the parts that demarcated the dicing streets when cutting the SiC semiconductor device 101 from a single SiC semiconductor wafer. In this configuration, the side surfaces 126A to 126D of the passivation layer 125 are also the parts that demarcated the dicing streets.

[0400] By exposing the peripheral portion of the SiC semiconductor layer 102 from the resin layer 129 and the passivation layer 125, it becomes unnecessary to physically cut the resin layer 129 and the passivation layer 125. This allows for the smooth cutting of the SiC semiconductor device 101 from a single SiC semiconductor wafer. Furthermore, the insulation distance from the side surfaces 105A to 105D of the SiC semiconductor layer 102 can be increased.

[0401] The distance between the side surfaces 105A to 105D and the resin side surfaces 130A to 130D (side surfaces 126A to 126D) may be 1 μm or more and 25 μm or less. The distance between the side surfaces 105A to 105D and the resin side surfaces 130A to 130D (side surfaces 126A to 126D) may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, or 20 μm or more and 25 μm or less. Of course, the side surfaces 126A to 126D of the passivation layer 125 may be formed flush with the side surfaces 105A to 105D of the SiC semiconductor layer 102.

[0402] The resin layer 129 has a gate pad opening 131 and a source pad opening 132. The gate pad opening 131 exposes the gate pad 116. The source pad opening 132 exposes the source pad 122.

[0403] The gate pad opening 131 of the resin layer 129 communicates with the gate sub-pad opening 127 of the passivation layer 125. The inner wall of the gate pad opening 131 may be located outside the inner wall of the gate sub-pad opening 127. The inner wall of the gate pad opening 131 may be located inside the inner wall of the gate sub-pad opening 127. The resin layer 129 may cover the inner wall of the gate sub-pad opening 127.

[0404] The source pad opening 132 of the resin layer 129 communicates with the source sub-pad opening 128 of the passivation layer 125. The inner wall of the gate pad opening 131 may be located outside the inner wall of the source sub-pad opening 128. The inner wall of the source pad opening 132 may be located inside the inner wall of the source sub-pad opening 128. The resin layer 129 may cover the inner wall of the source sub-pad opening 128.

[0405] The thickness of the resin layer 129 may be 1 μm or more and 50 μm or less. The thickness of the resin layer 129 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

[0406] A drain electrode layer 133, which serves as a second main surface electrode layer, is connected to the second main surface 104 of the SiC semiconductor layer 102. The maximum voltage that can be applied between the main surface source electrode layer 121 and the drain electrode layer 133 when the system is off may be between 1000V and 10000V.

[0407] The drain electrode layer 133 may include at least one of a Ti layer, a Ni layer, an Au layer, an Ag layer, or an Al layer. The drain electrode layer 133 may have a single-layer structure including a Ti layer, a Ni layer, an Au layer, an Ag layer, or an Al layer.

[0408] The drain electrode layer 133 may have a laminated structure in which at least two of the Ti layer, Ni layer, Au layer, Ag layer, and Al layer are stacked in any manner. The drain electrode layer 133 may have a four-layer structure including a Ti layer, Ni layer, Au layer, and Ag layer stacked in this order from the second main surface 104 of the SiC semiconductor layer 102.

[0409] The SiC semiconductor substrate 106 is formed as the drain region 134 of the MISFET. The SiC epitaxial layer 107 is formed as the drift region 135 of the MISFET.

[0410] Multiple modification lines 22A to 22D according to the first embodiment are formed on the side surfaces 105A to 105D of the SiC semiconductor layer 102. The structure of the modification lines 22A to 22D according to the third embodiment is the same as the structure of the modification lines 22A to 22D according to the first embodiment, except that they are formed on the SiC semiconductor layer 102 instead of the SiC semiconductor layer 2.

[0411] The descriptions of the modification lines 22A to 22D according to the first embodiment will be applied mutatis mutandis to the descriptions of the modification lines 22A to 22D according to the third embodiment, and a specific description of the modification lines 22A to 22D according to the third embodiment will be omitted.

[0412] Figure 20 is an enlarged view of region XX shown in Figure 19, illustrating the structure of the first main surface 103 of the SiC semiconductor layer 102. Figure 21 is a cross-sectional view along the line XXI-XXI shown in Figure 20. Figure 22 is a cross-sectional view along the line XXII-XXII shown in Figure 20. Figure 23 is an enlarged view of region XXIII shown in Figure 21. Figure 24 is a cross-sectional view along the line XXIV-XXIV shown in Figure 19. Figure 25 is an enlarged view of region XXV shown in Figure 24.

[0413] Referring to Figures 20 to 24, a p-type body region 141 is formed on the surface of the first main surface 103 of the SiC semiconductor layer 102 in the active region 111. The body region 141 defines the active region 111.

[0414] In this configuration, the body region 141 is formed over the entire area of ​​the region that forms the active region 111 on the first main surface 103 of the SiC semiconductor layer 102. The p-type impurity concentration of the body region 141 is 1.0 × 10⁻⁶. 17 cm -3 The above 1.0 × 10 19 cm -3 The following is also acceptable.

[0415] In the active region 111, a plurality of gate trenches 142 are formed on the surface of the first main surface 103 of the SiC semiconductor layer 102. The plurality of gate trenches 142 are each formed in a band shape extending along the first direction X (the m-axis direction of the SiC single crystal) in a plan view, and are formed at intervals along the second direction Y (the a-axis direction of the SiC single crystal).

[0416] In this configuration, each gate trench 142 extends from one periphery (side 105B) to the other periphery (side 105D) in the active region 111. The multiple gate trenches 142 are formed in a striped pattern as a whole in plan view.

[0417] Each gate trench 142 crosses the intermediate portion between one periphery and the other periphery in the active region 111. One end of each gate trench 142 is located at one periphery in the active region 111. The other end of each gate trench 142 is located at the other periphery in the active region 111.

[0418] The length of each gate trench 142 may be 0.5 mm or more. The length of each gate trench 142 is the length from the end of each gate trench 142 on the connection side to the outer gate finger 117 to the opposite end in the cross-section shown in Figure 22.

[0419] In this configuration, the length of each gate trench 142 is between 1 mm and 10 mm (for example, between 2 mm and 5 mm). The total length of one or more gate trenches 142 per unit area is 0.5 μm / μm. 2 More than 0.75μm / μm 2 The following is also acceptable.

[0420] Each gate trench 142 integrally includes an active trench portion 143 and a contact trench portion 144. The active trench portion 143 is the portion that aligns with the channel of the MISFET in the active region 111.

[0421] The contact trench portion 144 is primarily intended to make contact with the outer gate finger 117 in the gate trench 142. The contact trench portion 144 extends from the active trench portion 143 to the periphery of the active region 111. The contact trench portion 144 is formed in the region directly below the outer gate finger 117. The amount of extension of the contact trench portion 144 is arbitrary.

[0422] Each gate trench 142 penetrates the body region 141 and reaches the SiC epitaxial layer 107. Each gate trench 142 includes side walls and a bottom wall. The side walls forming the long sides of each gate trench 142 are formed by the a-plane of the SiC single crystal. The side walls forming the short sides of each gate trench 142 are formed by the m-plane of the SiC single crystal.

[0423] The side walls of each gate trench 142 may extend along the normal direction Z. The side walls of each gate trench 142 may be formed substantially perpendicular to the first main surface 103 of the SiC semiconductor layer 102.

[0424] Within the SiC semiconductor layer 102, the angle that the sidewall of each gate trench 142 makes with respect to the first main surface 103 of the SiC semiconductor layer 102 may be 90° or more and 95° or less (for example, 91° or more and 93° or less). Each gate trench 142 may be formed in a tapered shape in cross-sectional view, where the opening area on the bottom wall side is smaller than the opening area on the opening side.

[0425] The bottom wall of each gate trench 142 is located in the SiC epitaxial layer 107. More specifically, the bottom wall of each gate trench 142 is located in the high-concentration region 108 of the SiC epitaxial layer 107.

[0426] The bottom wall of each gate trench 142 faces the c-plane of the SiC single crystal. The bottom wall of each gate trench 142 has an off-angle θ inclined in the [11-20] direction with respect to the c-plane of the SiC single crystal.

[0427] The bottom wall of each gate trench 142 may be formed parallel to the first main surface 103 of the SiC semiconductor layer 102. Of course, the bottom wall of each gate trench 142 may be formed in a convex curve toward the second main surface 104 of the SiC semiconductor layer 102.

[0428] With respect to the normal direction Z, the depth of each gate trench 142 may be between 0.5 μm and 3.0 μm. The depth of each gate trench 142 may be between 0.5 μm and 1.0 μm, between 1.0 μm and 1.5 μm, between 1.5 μm and 2.0 μm, between 2.0 μm and 2.5 μm, or between 2.5 μm and 3.0 μm.

[0429] The width of each gate trench 142 along the second direction Y may be 0.1 μm or more and 2 μm or less. The width of each gate trench 142 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1.0 μm or less, 1.0 μm or more and 1.5 μm or less, or 1.5 μm or more and 2 μm or less.

[0430] Referring to Figure 23, the opening edge portion 146 of each gate trench 142 includes an inclined portion 147 that slopes downward from the first main surface 103 of the SiC semiconductor layer 102 toward the inside of each gate trench 142. The opening edge portion 146 of each gate trench 142 is a corner connecting the first main surface 103 of the SiC semiconductor layer 102 and the side wall of each gate trench 142.

[0431] In this configuration, the inclined portion 147 is formed in a concave curve that curves inward toward the SiC semiconductor layer 102. The inclined portion 147 may also be formed in a convex curve that curves inward toward each gate trench 142. The inclined portion 147 mitigates electric field concentration with respect to the opening edge portion 146 of each gate trench 142.

[0432] A gate insulating layer 148 and a gate electrode layer 149 are formed within each gate trench 142. In Figure 20, the gate insulating layer 148 and the gate electrode layer 149 are indicated by hatching.

[0433] The gate insulating layer 148 contains at least one of the following: silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), zirconium oxide (ZrO2), or tantalum oxide (Ta2O3).

[0434] The gate insulating layer 148 may have a laminated structure including a SiN layer and an SiO2 layer stacked in this order from the first main surface 103 side of the SiC semiconductor layer 102. The gate insulating layer 148 may have a single-layer structure consisting of an SiO2 layer or a SiN layer. In this embodiment, the gate insulating layer 148 has a single-layer structure consisting of an SiO2 layer.

[0435] The gate insulating layer 148 is formed in a film-like manner along the inner wall surface of the gate trench 142 such that a concave space is defined within the gate trench 142. The gate insulating layer 148 includes a first region 148a, a second region 148b, and a third region 148c.

[0436] The first region 148a is formed along the side wall of the gate trench 142. The second region 148b is formed along the bottom wall of the gate trench 142. The third region 148c is formed along the first main surface 103 of the SiC semiconductor layer 102. The third region 148c of the gate insulating layer 148 forms part of the main surface insulating layer 113.

[0437] The thickness Ta of the first region 148a is smaller than the thickness Tb of the second region 148b and the thickness Tc of the third region 148c. The ratio Tb / Ta of the thickness Tb of the second region 148b to the thickness Ta of the first region 148a may be between 2 and 5. The ratio T3 / Ta of the thickness Tc of the third region 148c to the thickness Ta of the first region 148a may be between 2 and 5.

[0438] The thickness Ta of the first region 148a may be between 0.01 μm and 0.2 μm. The thickness Tb of the second region 148b may be between 0.05 μm and 0.5 μm. The thickness Tc of the third region 148c may be between 0.05 μm and 0.5 μm.

[0439] By thinning the first region 148a of the gate insulating layer 148, the increase in carriers induced in the region near the side walls of each gate trench 142 in the body region 141 can be suppressed. This suppresses the increase in channel resistance. By thickening the second region 148b of the gate insulating layer 148, the electric field concentration on the bottom wall of each gate trench 142 can be mitigated.

[0440] By increasing the thickness of the third region 148c of the gate insulating layer 148, the breakdown voltage of the gate insulating layer 148 near the opening edge portion 146 of each gate trench 142 can be improved. Furthermore, by increasing the thickness of the third region 148c, the disappearance of the third region 148c by the etching method can be suppressed.

[0441] This prevents the first region 148a from being removed by etching due to the disappearance of the third region 148c. As a result, the gate electrode layer 149 can be properly positioned opposite the SiC semiconductor layer 102 (body region 141) with the gate insulating layer 148 in between.

[0442] The gate insulating layer 148 further includes bulges 148d that bulge inward into each gate trench 142 at the opening edge portion 146 of each gate trench 142. The bulges 148d are formed at the corners connecting the first region 148a and the third region 148c of the gate insulating layer 148.

[0443] The bulging portion 148d protrudes inward in a convex curved shape from each gate trench 142. The bulging portion 148d narrows the opening of each gate trench 142 at the opening edge portion 146 of each gate trench 142.

[0444] The bulging portion 148d improves the dielectric strength of the gate insulating layer 148 at the opening edge portion 146. Of course, a gate insulating layer 148 without the bulging portion 148d may be formed. Alternatively, a gate insulating layer 148 with a uniform thickness may be formed.

[0445] The gate electrode layer 149 is embedded in each gate trench 142, sandwiched between the gate insulating layer 148. More specifically, the gate electrode layer 149 is embedded in the concave space partitioned by the gate insulating layer 148 in each gate trench 142. The gate electrode layer 149 is controlled by the gate voltage.

[0446] The gate electrode layer 149 has an upper end located on the opening side of each gate trench 142. The upper end of the gate electrode layer 149 is formed in a concave curve that is recessed toward the bottom wall of each gate trench 142. The upper end of the gate electrode layer 149 has a constricted portion that is aligned with the bulge 148d of the gate insulating layer 148.

[0447] The cross-sectional area of ​​the gate electrode layer 149 (the cross-sectional area perpendicular to the direction in which each gate trench 142 extends) is 0.05 μm². 2 Above 0.5 μm 2 The following is also possible: The cross-sectional area of ​​the gate electrode layer 149 is defined as the product of the depth of the gate electrode layer 149 and the width of the gate electrode layer 149.

[0448] The depth of the gate electrode layer 149 is the distance from the upper end to the lower end of the gate electrode layer 149. The width of the gate electrode layer 149 is the width of the gate trench 142 at an intermediate position between the upper and lower ends of the gate electrode layer 149. If the upper end is curved (concave in this form), the position of the upper end of the gate electrode layer 149 is an intermediate position in the depth direction on the upper surface of the gate electrode layer 149.

[0449] The gate electrode layer 149 contains p-type polysilicon doped with p-type impurities. The p-type impurities in the gate electrode layer 149 may include at least one of boron (B), aluminum (Al), indium (In), or gallium (Ga).

[0450] The p-type impurity concentration in the gate electrode layer 149 is greater than or equal to the p-type impurity concentration in the body region 141. More specifically, the p-type impurity concentration in the gate electrode layer 149 is greater than the p-type impurity concentration in the body region 141.

[0451] The p-type impurity concentration in the gate electrode layer 149 is 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 22 cm -3 The following is also possible: The sheet resistance of the gate electrode layer 149 may be 10Ω / □ or more and 500Ω / □ or less (approximately 200Ω / □ in this configuration).

[0452] Referring to Figures 20 and 22, a gate wiring layer 150 is formed in the active region 111. The gate wiring layer 150 is electrically connected to the gate pad 116 and gate fingers 117, 118. In Figure 22, the gate wiring layer 150 is indicated by hatching.

[0453] The gate wiring layer 150 is formed on the first main surface 103 of the SiC semiconductor layer 102. More specifically, the gate wiring layer 150 is formed on the third region 148c of the gate insulating layer 148.

[0454] In this embodiment, the gate wiring layer 150 is formed along the outer gate finger 117. More specifically, the gate wiring layer 150 is formed along the three sides 105A, 105B, and 105D of the SiC semiconductor layer 102 so as to partition the inner region of the active region 111 from three directions.

[0455] The gate wiring layer 150 is connected to the gate electrode layer 149 exposed from the contact trench portion 144 of each gate trench 142. In this embodiment, the gate wiring layer 150 is formed by the pull-out portions of the gate electrode layer 149 that are pulled out from each gate trench 142 onto the first main surface 103 of the SiC semiconductor layer 102. The upper end of the gate wiring layer 150 is connected to the upper end of the gate electrode layer 149.

[0456] Referring to Figures 20, 21, and 23, in the active region 111, a plurality of source trenches 155 are formed on the first main surface 103 of the SiC semiconductor layer 102. Each source trench 155 is formed in the region between two adjacent gate trenches 142.

[0457] Each of the multiple source trenches 155 is formed in a strip-like shape extending along the first direction X (the m-axis direction of the SiC single crystal). In a plan view, the multiple source trenches 155 are formed as a stripe as a whole. With respect to the second direction Y, the pitch between the centers of adjacent source trenches 155 may be between 1.5 μm and 3 μm.

[0458] Each source trench 155 penetrates the body region 141 and reaches the SiC epitaxial layer 107. Each source trench 155 includes side walls and a bottom wall. The side walls forming the long sides of each source trench 155 are formed by the a-plane of the SiC single crystal. The side walls forming the short sides of each source trench 155 are formed by the m-plane of the SiC single crystal.

[0459] The sidewalls of each source trench 155 may extend along the normal direction Z. The sidewalls of each source trench 155 may be formed substantially perpendicular to the first main surface 103 of the SiC semiconductor layer 102.

[0460] Within the SiC semiconductor layer 102, the angle that the sidewall of each source trench 155 makes with respect to the first main surface 103 of the SiC semiconductor layer 102 may be 90° or more and 95° or less (for example, 91° or more and 93° or less). Each source trench 155 may be formed in a tapered shape in cross-sectional view, where the opening area on the bottom wall side is smaller than the opening area on the opening side.

[0461] The bottom wall of each source trench 155 is located in the SiC epitaxial layer 107. More specifically, the bottom wall of each source trench 155 is located in the high-concentration region 108 of the SiC epitaxial layer 107. More specifically, the bottom wall of each source trench 155 is located in the region between the bottom wall and the low-concentration region 109 of each gate trench 142.

[0462] The bottom wall of each source trench 155 faces the c-plane of the SiC single crystal. The bottom wall of each source trench 155 has an off-angle θ inclined in the [11-20] direction with respect to the c-plane of the SiC single crystal.

[0463] The bottom wall of each source trench 155 may be formed parallel to the first main surface 103 of the SiC semiconductor layer 102. Of course, the bottom wall of each source trench 155 may be formed in a convex curve toward the second main surface 104 of the SiC semiconductor layer 102.

[0464] In this configuration, the depth of each source trench 155 is greater than or equal to the depth of each gate trench 142. More specifically, the depth of each source trench 155 is greater than the depth of each gate trench 142.

[0465] The bottom wall of each source trench 155 is located on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of each gate trench 142. Of course, the depth of each source trench 155 may be equal to the depth of each gate trench 142.

[0466] With respect to the normal direction Z, the depth of each source trench 155 may be 0.5 μm or more and 10 μm or less (for example, about 2 μm). The ratio of the depth of each source trench 155 to the depth of each gate trench 142 may be 1.5 or more. Preferably, the ratio of the depth of each source trench 155 to the depth of each gate trench 142 is 2 or more.

[0467] The first directional width of each source trench 155 may be approximately equal to the first directional width of each gate trench 142. The first directional width of each source trench 155 may be greater than or equal to the first directional width of each gate trench 142. The first directional width of each source trench 155 may be between 0.1 μm and 2 μm (for example, about 0.5 μm).

[0468] A source insulating layer 156 and a source electrode layer 157 are formed within each source trench 155. In Figure 20, the source insulating layer 156 and the source electrode layer 157 are indicated by hatching.

[0469] The source insulating layer 156 contains at least one of the following: silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), zirconium oxide (ZrO2), or tantalum oxide (Ta2O3).

[0470] The source insulating layer 156 may have a laminated structure including a SiN layer and an SiO2 layer stacked in this order from the first main surface 103 side of the SiC semiconductor layer 102. The source insulating layer 156 may have a laminated structure including an SiO2 layer and a SiN layer stacked in this order from the first main surface 103 side of the SiC semiconductor layer 102. The source insulating layer 156 may have a single-layer structure consisting of an SiO2 layer or a SiN layer. In this embodiment, the source insulating layer 156 has a single-layer structure consisting of an SiO2 layer.

[0471] The source insulating layer 156 is formed in a film-like manner along the inner wall surface of each source trench 155 such that a concave space is defined within each source trench 155. The source insulating layer 156 includes a first region 156a and a second region 156b.

[0472] The first region 156a is formed along the side wall of each source trench 155. The second region 156b is formed along the bottom wall of each source trench 155. The thickness Tsa of the first region 156a is less than the thickness Tsb of the second region 156b.

[0473] The ratio Tsb / Tsa of the thickness Tsb of the second region 156b to the thickness Tsa of the first region 156a may be between 2 and 5. The thickness Tsa of the first region 156a may be between 0.01 μm and 0.2 μm. The thickness Tsb of the second region 156b may be between 0.05 μm and 0.5 μm.

[0474] The thickness Tsa of the first region 156a may be approximately equal to the thickness Ta of the first region 156a of the gate insulating layer 148. The thickness Tsb of the second region 156b may be approximately equal to the thickness Tb of the second region 156b of the gate insulating layer 148. Of course, a source insulating layer 156 having a uniform thickness may be formed.

[0475] The source electrode layer 157 is embedded in each source trench 155, sandwiched between the source insulating layer 156. More specifically, the source electrode layer 157 is embedded in the concave space partitioned by the source insulating layer 156 in each source trench 155. The source electrode layer 157 is controlled by the source voltage.

[0476] The source electrode layer 157 has an upper end located on the opening side of each source trench 155. The upper end of the source electrode layer 157 is formed below the first main surface 103 of the SiC semiconductor layer 102. The upper end of the source electrode layer 157 may be located above the first main surface 103 of the SiC semiconductor layer 102.

[0477] The upper end of the source electrode layer 157 is formed in a concave curved shape that is recessed toward the bottom wall of each source trench 155. The upper end of the source electrode layer 157 may also be formed parallel to the first main surface 103 of the SiC semiconductor layer 102.

[0478] The upper end of the source electrode layer 157 may protrude above the upper end of the source insulating layer 156. The upper end of the source electrode layer 157 may be located below the upper end of the source insulating layer 156. The thickness of the source electrode layer 157 may be 0.5 μm or more and 10 μm or less (for example, about 1 μm).

[0479] The source electrode layer 157 preferably contains polysilicon having properties similar to SiC in terms of material properties. This reduces the stress generated within the SiC semiconductor layer 102. In this embodiment, the source electrode layer 157 contains p-type polysilicon with p-type impurities added. In this case, the source electrode layer 157 can be formed simultaneously with the gate electrode layer 149.

[0480] The p-type impurity concentration in the source electrode layer 157 is greater than or equal to the p-type impurity concentration in the body region 141. More specifically, the p-type impurity concentration in the source electrode layer 157 is greater than the p-type impurity concentration in the body region 141. The p-type impurities in the source electrode layer 157 may include at least one of boron (B), aluminum (Al), indium (In), or gallium (Ga).

[0481] The p-type impurity concentration in the source electrode layer 157 is 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 22 cm -3 The following is also possible: The sheet resistance of the source electrode layer 157 may be 10Ω / □ or more and 500Ω / □ or less (approximately 200Ω / □ in this configuration).

[0482] The p-type impurity concentration in the source electrode layer 157 may be approximately equal to that of the gate electrode layer 149. The sheet resistance of the source electrode layer 157 may be approximately equal to that of the gate electrode layer 149.

[0483] The source electrode layer 157 may contain n-type polysilicon in place of or in addition to p-type polysilicon. The source electrode layer 157 may contain at least one of tungsten, aluminum, copper, aluminum alloy, or copper alloy in place of or in addition to p-type polysilicon.

[0484] Thus, the SiC semiconductor device 101 has a plurality of trench gate structures 161 and a plurality of trench source structures 162. Each trench gate structure 161 includes a gate trench 142, a gate insulating layer 148, and a gate electrode layer 149. Each trench source structure 162 includes a source trench 155, a source insulating layer 156, and a source electrode layer 157.

[0485] In the surface portion of the body region 141, the region along the side wall of each gate trench 142 is n + A source region 163 of type n is formed. The n-type impurity concentration in the source region 163 is 1.0 × 10⁻⁶. 18 cm -3 The above 1.0 × 10 21 cm -3 The following may also apply: The n-type impurity in source region 163 may be phosphorus (P).

[0486] Multiple source regions 163 are formed along one side wall and the other side wall of each gate trench 142. Each of the multiple source regions 163 is formed in a strip shape extending along the first direction X.

[0487] The multiple source regions 163 are formed in a striped pattern as a whole in a plan view. Each source region 163 is exposed from the side walls of each gate trench 142 and each source trench 155.

[0488] Thus, in the surface layer of the first main surface 103 of the SiC semiconductor layer 102, the region along the side wall of the gate trench 142 is formed in the order of source region 163, body region 141, and drift region 135 from the first main surface 103 to the second main surface 104 of the SiC semiconductor layer 102.

[0489] In the body region 141, a channel for the MISFET is formed in the region along the side wall of the gate trench 142. The channel is formed in the region along the side wall facing the a-face of the SiC single crystal in the gate trench 142. The ON / OFF state of the channel is controlled by the gate electrode layer 149.

[0490] In the active region 111, the surface layer of the first main surface 103 of the SiC semiconductor layer 102 has multiple p + A type of contact region 164 is formed. Each contact region 164 is formed in the region between two gate trenches 142 that are adjacent to each other in a plan view. Each contact region 164 is formed in the region opposite to each source region 163 from the gate trench 142.

[0491] Each contact region 164 is formed along the inner wall of each source trench 155. In this configuration, multiple contact regions 164 are formed at intervals along the inner wall of each source trench 155. Each contact region 164 is formed at intervals from each gate trench 142.

[0492] The p-type impurity concentration in each contact region 164 is greater than the p-type impurity concentration in the body region 141. The p-type impurity concentration in each contact region 164 is 1.0 × 10⁻⁶. 18 cm -3 The above 1.0 × 10 21 cm -3 The following may also apply: The p-type impurity in each contact region 164 may be aluminum (Al).

[0493] Each contact region 164 covers the side and bottom walls of each source trench 155. The bottom of each contact region 164 may be formed parallel to the bottom wall of each source trench 155. More specifically, each contact region 164 integrally includes a first surface region 164a, a second surface region 164b, and an inner wall region 164c.

[0494] The first surface region 164a covers one side wall of the source trench 155 in the surface portion of the body region 141. The first surface region 164a is electrically connected to the body region 141 and the source region 163.

[0495] The first surface region 164a is located on the side of the first main surface 103 of the SiC semiconductor layer 102 relative to the bottom of the source region 163. In this embodiment, the first surface region 164a has a bottom that extends parallel to the first main surface 103 of the SiC semiconductor layer 102.

[0496] In this embodiment, the bottom of the first surface region 164a is located in the region between the bottom of the body region 141 and the bottom of the source region 163. The bottom of the first surface region 164a may also be located in the region between the first main surface 103 of the SiC semiconductor layer 102 and the bottom of the body region 141.

[0497] In this embodiment, the first surface region 164a extends from the source trench 155 toward the adjacent gate trench 142. The first surface region 164a may extend to an intermediate region between the gate trench 142 and the source trench 155. The first surface region 164a is formed with a gap between the gate trench 142 and the source trench 155.

[0498] The second surface region 164b covers the other side wall of the source trench 155 in the surface portion of the body region 141. The second surface region 164b is electrically connected to the body region 141 and the source region 163.

[0499] The second surface region 164b is located on the side of the first main surface 103 of the SiC semiconductor layer 102 relative to the bottom of the source region 163. In this configuration, the second surface region 164b has a bottom that extends parallel to the first main surface 103 of the SiC semiconductor layer 102.

[0500] In this embodiment, the bottom of the second surface region 164b is located in the region between the bottom of the body region 141 and the bottom of the source region 163. The bottom of the second surface region 164b may also be located in the region between the first main surface 103 of the SiC semiconductor layer 102 and the bottom of the body region 141.

[0501] In this embodiment, the second surface region 164b extends from the other side wall of the source trench 155 toward the adjacent gate trench 142. The second surface region 164b may extend to an intermediate region between the source trench 155 and the gate trench 142. The second surface region 164b is formed with a gap between the gate trench 142 and the source trench 155.

[0502] The inner wall region 164c is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the first surface region 164a and the second surface region 164b (bottom of the source region 163). The inner wall region 164c is formed in the SiC semiconductor layer 102 in the region along the inner wall of the source trench 155. The inner wall region 164c covers the side wall of the source trench 155.

[0503] The inner wall region 164c covers the corners connecting the side walls and bottom walls of the source trench 155. The inner wall region 164c covers the bottom wall of the source trench 155 from the side walls through the corners. The bottom of the contact region 164 is formed by the inner wall region 164c.

[0504] Multiple deep well regions 165 are formed on the surface of the first main surface 103 of the SiC semiconductor layer 102. Each deep well region 165 is also called a breakdown voltage adjustment region (breakdown voltage holding region) that adjusts the breakdown voltage of the SiC semiconductor layer 102 in the active region 111.

[0505] Each deep well region 165 is formed in the SiC epitaxial layer 107. More specifically, each deep well region 165 is formed in the high-concentration region 108 of the SiC epitaxial layer 107.

[0506] Each deep well region 165 is formed along the inner wall of each source trench 155 so as to cover each contact region 164. Each deep well region 165 is electrically connected to each contact region 164.

[0507] Each deep well region 165 is formed in a strip shape that extends along each source trench 155 in a plan view. Each deep well region 165 covers the side wall of each source trench 155.

[0508] Each deep well region 165 covers the corners connecting the side walls and bottom walls of each source trench 155. Each deep well region 165 covers the bottom wall of each source trench 155 from the side walls through the corners. Each deep well region 165 is connected to the body region 141 at the side walls of each source trench 155.

[0509] Each deep well region 165 has a bottom that is located on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of each gate trench 142. The bottom of each deep well region 165 may be formed parallel to the bottom wall of each source trench 155.

[0510] The p-type impurity concentration in each deep well region 165 may be approximately equal to the p-type impurity concentration in the body region 141. The p-type impurity concentration in each deep well region 165 may exceed the p-type impurity concentration in the body region 141. The p-type impurity concentration in each deep well region 165 may be less than the p-type impurity concentration in the body region 141.

[0511] The p-type impurity concentration in each deep well region 165 may be less than or equal to the p-type impurity concentration in the contact region 164. The p-type impurity concentration in each deep well region 165 may be less than the p-type impurity concentration in the contact region 164. The p-type impurity concentration in each deep well region 165 is 1.0 × 10⁻⁶ 17 cm -3 The above 1.0 × 10 19 cm -3 The following is also acceptable.

[0512] Each deep well region 165 forms a pn junction with the SiC semiconductor layer 102 (high-density region 108 of the SiC epitaxial layer 107). From this pn junction, a depletion layer extends toward the region between adjacent gate trenches 142. This depletion layer extends toward the region on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of each gate trench 142.

[0513] The depletion layer extending from each deep well region 165 may overlap the bottom wall of each gate trench 142. The depletion layer extending from the bottom of each deep well region 165 may overlap the bottom wall of each gate trench 142.

[0514] Referring to Figures 20 and 22, a p-type peripheral deep well region 166 is formed at the periphery of the active region 111. The peripheral deep well region 166 is formed in the SiC epitaxial layer 107. More specifically, the peripheral deep well region 166 is formed in the high-concentration region 108 of the SiC epitaxial layer 107.

[0515] The peripheral deep well region 166 is electrically connected to each deep well region 165. The peripheral deep well region 166 is at the same potential as each deep well region 165. In this configuration, the peripheral deep well region 166 is formed integrally with each deep well region 165.

[0516] More specifically, the peripheral deep well region 166 is formed in the peripheral portion of the active region 111, along the inner wall of the contact trench portion 144 of each gate trench 142.

[0517] The peripheral deep well region 166 covers the side walls of the contact trench portion 144 of each gate trench 142. The peripheral deep well region 166 also covers the corners connecting the side walls and bottom walls of each contact trench portion 144.

[0518] The peripheral deep well region 166 covers the bottom wall of each contact trench 144 from its side wall through its corner. Each deep well region 165 is connected to the body region 141 at the side wall of each contact trench 144. The bottom of the peripheral deep well region 166 is located on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of each contact trench 144.

[0519] The peripheral deep well region 166 overlaps the gate wiring layer 150 in a plan view. The peripheral deep well region 166 faces the gate wiring layer 150 across the gate insulating layer 148 (third region 148c).

[0520] The peripheral deep well region 166 includes extension portions 166a drawn out from each contact trench portion 144 to each active trench portion 143. The extension portions 166a are formed in the high-concentration region 108 of the SiC epitaxial layer 107. The extension portions 166a extend along the side walls of each active trench portion 143 and cover the bottom walls of the active trench portions 143 through the corners.

[0521] The pull-out section 166a covers the side wall of the active trench section 143 of each gate trench 142. The pull-out section 166a also covers the corners connecting the side walls and bottom walls of each active trench section 143.

[0522] The pull-out portion 166a covers the bottom wall of each active trench portion 143 from the side wall through the corner. The pull-out portion 166a is connected to the body region 141 at the side wall of each active trench portion 143. The bottom of the pull-out portion 166a is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each active trench portion 143.

[0523] The p-type impurity concentration in the peripheral deep well region 166 may be approximately equal to the p-type impurity concentration in the body region 141. The p-type impurity concentration in the peripheral deep well region 166 may exceed the p-type impurity concentration in the body region 141. The p-type impurity concentration in the peripheral deep well region 166 may be less than the p-type impurity concentration in the body region 141.

[0524] The p-type impurity concentration in the peripheral deep well region 166 may be approximately equal to the p-type impurity concentration in each deep well region 165. The p-type impurity concentration in the peripheral deep well region 166 may exceed the p-type impurity concentration in each deep well region 165. The p-type impurity concentration in the peripheral deep well region 166 may be less than the p-type impurity concentration in each deep well region 165.

[0525] The p-type impurity concentration in the peripheral deep well region 166 may be less than or equal to the p-type impurity concentration in the contact region 164. The p-type impurity concentration in the peripheral deep well region 166 may be less than the p-type impurity concentration in the contact region 164. The p-type impurity concentration in the peripheral deep well region 166 is 1.0 × 10⁻⁶. 17 cm -3 The above 1.0 × 10 19 cm -3 The following is also acceptable.

[0526] In a SiC semiconductor device equipped only with pn junction diodes, the problem of electric field concentration within the SiC semiconductor layer 102 is less pronounced due to the absence of trenches in the structure. Each deep well region 165 (peripheral deep well region 166) brings the trench-gate type MISFET closer to the structure of a pn junction diode.

[0527] This allows for the relaxation of the electric field within the SiC semiconductor layer 102 in a trench-gate type MISFET. Therefore, narrowing the pitch between multiple adjacent deep well regions 165 is effective in mitigating electric field concentration.

[0528] Furthermore, each deep well region 165, having its bottom on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of each gate trench 142, allows the depletion layer to appropriately mitigate electric field concentration in each gate trench 142.

[0529] It is preferable that the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102 is approximately constant. This suppresses variations in the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102.

[0530] Therefore, the breakdown voltage (e.g., fracture voltage) of the SiC semiconductor layer 102 can be suppressed from being limited by the shape of each deep well region 165, thus enabling an appropriate improvement in breakdown voltage.

[0531] In this configuration, a high-concentration region 108 of the SiC epitaxial layer 107 is interposed in the region between multiple adjacent deep well regions 165. This makes it possible to reduce the JFET (Junction Field Effect Transistor) resistance in the region between multiple adjacent deep well regions 165.

[0532] Furthermore, in this configuration, the bottom of each deep well region 165 is located within the high-density region 108 of the SiC epitaxial layer 107. This allows current paths to be extended laterally from the bottom of each deep well region 165, parallel to the first main surface 103 of the SiC semiconductor layer 102. This reduces current spreading resistance. The low-density region 109 of the SiC epitaxial layer 107 increases the breakdown voltage of the SiC semiconductor layer 102 in this structure.

[0533] By forming source trenches 155, p-type impurities can be introduced into the inner walls of the source trenches 155. This allows for the conformal formation of each deep well region 165 within the source trenches 155, thereby effectively suppressing variations in the depth of each deep well region 165. Furthermore, by utilizing each source trench 155, each deep well region 165 can be appropriately formed in relatively deep regions of the SiC semiconductor layer 102.

[0534] Referring to Figure 23, a low-resistance electrode layer 167 is formed on the gate electrode layer 149. The low-resistance electrode layer 167 covers the upper end of the gate electrode layer 149 within each gate trench 142.

[0535] The low-resistance electrode layer 167 includes a conductive material having a sheet resistance less than that of the gate electrode layer 149. The sheet resistance of the low-resistance electrode layer 167 may be between 0.01 Ω / □ and 10 Ω / □.

[0536] The low-resistance electrode layer 167 is formed in a film-like manner. The low-resistance electrode layer 167 has a connecting portion 167a that is in contact with the upper end of the gate electrode layer 149 and a non-connecting portion 167b on the opposite side. The connecting portion 167a and the non-connecting portion 167b of the low-resistance electrode layer 167 may be formed in a concave curved shape following the upper end of the gate electrode layer 149. The connecting portion 167a and the non-connecting portion 167b of the low-resistance electrode layer 167 can take various forms.

[0537] The entire connection portion 167a of the low-resistance electrode layer 167 may be located above the first main surface 103 of the SiC semiconductor layer 102. The entire connection portion 167a of the low-resistance electrode layer 167 may be located below the first main surface 103 of the SiC semiconductor layer 102.

[0538] The connection portion 167a of the low-resistance electrode layer 167 may include a portion located above the first main surface 103 of the SiC semiconductor layer 102. The connection portion 167a of the low-resistance electrode layer 167 may include a portion located below the first main surface 103 of the SiC semiconductor layer 102.

[0539] For example, the central part of the connection portion 167a of the low-resistance electrode layer 167 may be located below the first main surface 103 of the SiC semiconductor layer 102, and the peripheral part of the connection portion 167a of the low-resistance electrode layer 167 may be located above the first main surface 103 of the SiC semiconductor layer 102.

[0540] The entire unconnected portion 167b of the low-resistance electrode layer 167 may be located above the first main surface 103 of the SiC semiconductor layer 102. The entire unconnected portion 167b of the low-resistance electrode layer 167 may be located below the first main surface 103 of the SiC semiconductor layer 102.

[0541] The unconnected portion 167b of the low-resistance electrode layer 167 may include a portion located above the first main surface 103 of the SiC semiconductor layer 102. The unconnected portion 167b of the low-resistance electrode layer 167 may include a portion located below the first main surface 103 of the SiC semiconductor layer 102.

[0542] For example, the central part of the unconnected portion 167b of the low-resistance electrode layer 167 may be located below the first main surface 103 of the SiC semiconductor layer 102, and the peripheral part of the unconnected portion 167b of the low-resistance electrode layer 167 may be located above the first main surface 103 of the SiC semiconductor layer 102.

[0543] The low-resistance electrode layer 167 has an edge portion 167c that is in contact with the gate insulating layer 148. The edge portion 167c of the low-resistance electrode layer 167 is in contact with the corner portion of the gate insulating layer 148 that connects the first region 148a and the second region 148b.

[0544] The edge 167c of the low-resistance electrode layer 167 is in contact with the third region 148c of the gate insulating layer 148. More specifically, the edge 167c of the low-resistance electrode layer 167 is in contact with the bulging portion 148d of the gate insulating layer 148.

[0545] The edge 167c of the low-resistance electrode layer 167 is formed in a region on the first main surface 103 side of the SiC semiconductor layer 102 with respect to the bottom of the source region 163. The edge 167c of the low-resistance electrode layer 167 is formed in a region on the first main surface 103 side of the SiC semiconductor layer 102 rather than in the boundary region between the body region 141 and the source region 163.

[0546] Therefore, the edge 167c of the low-resistance electrode layer 167 faces the source region 163 with the gate insulating layer 148 interposed therebetween. The edge 167c of the low-resistance electrode layer 167 does not face the body region 141 with the gate insulating layer 148 interposed therebetween.

[0547] Thereby, it is possible to suppress the formation of a current path in the region between the low-resistance electrode layer 167 and the body region 141 in the gate insulating layer 148. The current path may be formed by an undesired diffusion of the electrode material of the low-resistance electrode layer 167 with respect to the gate insulating layer 148.

[0548] Particularly, a design in which the edge 167c of the low-resistance electrode layer 167 is connected to the third region 148c (the corner portion of the gate insulating layer 148) of the relatively thick gate insulating layer 148 is effective in reducing the risk of forming a current path.

[0549] In the normal direction Z, the thickness Tr of the low-resistance electrode layer 167 is not more than the thickness TG of the gate electrode layer 149 (Tr ≦ TG). Preferably, the thickness Tr of the low-resistance electrode layer 167 is less than the thickness TG of the gate electrode layer 149 (Tr < TG). More specifically, preferably, the thickness Tr of the low-resistance electrode layer 167 is not more than half of the thickness TG of the gate electrode layer 149 (Tr ≦ TG / 2).

[0550] The ratio Tr / TG of the thickness Tr of the low-resistance electrode layer 167 to the thickness TG of the gate electrode layer 149 is 0.01 or more and 1 or less. The thickness TG of the gate electrode layer 149 may be 0.5 μm or more and 3 μm or less. The thickness Tr of the low-resistance electrode layer 167 may be 0.01 μm or more and 3 μm or less.

[0551] The current supplied into each gate trench 142 flows through the low-resistance electrode layer 167, which has a relatively low sheet resistance, and is transmitted to the entire gate electrode layer 149. This allows the entire gate electrode layer 149 (the entire active region 111) to transition from the off state to the on state quickly, thereby suppressing the delay in the switching response.

[0552] In particular, in the case of gate trenches 142 having a length on the order of millimeters (1 mm or more), current transmission takes time, but the low-resistance electrode layer 167 can appropriately suppress the delay in the switching response. In other words, the low-resistance electrode layer 167 is formed as a current-diffusing electrode layer that diffuses current within each gate trench 142.

[0553] Furthermore, as the cell structure becomes more miniaturized, the width, depth, and cross-sectional area of ​​the gate electrode layer 149 decrease, raising concerns about delays in the switching response due to increased electrical resistance within each gate trench 142.

[0554] However, the low-resistance electrode layer 167 allows the entire gate electrode layer 149 to quickly transition from the off state to the on state, thus effectively suppressing the delay in the switching response caused by miniaturization.

[0555] Referring to Figure 22, in this embodiment, the low-resistance electrode layer 167 also covers the upper end of the gate wiring layer 150. The portion of the low-resistance electrode layer 167 that covers the upper end of the gate wiring layer 150 is integrally formed with the portion of the low-resistance electrode layer 167 that covers the upper end of the gate electrode layer 149. As a result, the low-resistance electrode layer 167 covers the entire area of ​​the gate electrode layer 149 and the entire area of ​​the gate wiring layer 150.

[0556] Therefore, the current supplied from the gate pads 116 and gate fingers 117, 118 to the gate wiring layer 150 is transmitted throughout the gate electrode layer 149 and the gate wiring layer 150 via the low-resistance electrode layer 167, which has a relatively low sheet resistance.

[0557] This allows the entire gate electrode layer 149 (the entire active region 111) to be quickly transitioned from the off state to the on state via the gate wiring layer 150, thereby suppressing the delay in the switching response.

[0558] In particular, in the case of a gate trench 142 having a length on the order of millimeters, the low-resistance electrode layer 167 covering the upper end of the gate wiring layer 150 can effectively suppress the delay in the switching response.

[0559] The low-resistance electrode layer 167 includes a polyside layer. The polyside layer is formed by silicideizing the portion of the gate electrode layer 149 that forms the surface layer with a metallic material. More specifically, the polyside layer consists of a p-type polyside layer containing p-type impurities added to the gate electrode layer 149 (p-type polysilicon). The polyside layer preferably has a resistivity of 10 μΩ·cm or more and 110 μΩ·cm or less.

[0560] The sheet resistance within the gate trench 142, in which the gate electrode layer 149 and the low-resistance electrode layer 167 are embedded, is less than or equal to the sheet resistance of the gate electrode layer 149 alone. Preferably, the sheet resistance within the gate trench 142 is less than or equal to the sheet resistance of n-type polysilicon doped with n-type impurities.

[0561] The sheet resistance within the gate trench 142 is approximated by the sheet resistance of the low-resistance electrode layer 167. That is, the sheet resistance within the gate trench 142 may be between 0.01 Ω / □ and 10 Ω / □. Preferably, the sheet resistance within the gate trench 142 is less than 10 Ω / □.

[0562] The low-resistance electrode layer 167 may contain at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, or WSi2. In particular, NiSi, CoSi2, and TiSi2 among these species are suitable as polyside layers for forming the low-resistance electrode layer 167 because their resistivity values ​​and temperature dependence are relatively small.

[0563] In the first main surface 103 of the SiC semiconductor layer 102, a source sub-trench 168 is formed in a region along the upper end of the source electrode layer 157, communicating with each source trench 155. The source sub-trench 168 forms part of the side wall of each source trench 155.

[0564] In this configuration, the source sub-trench 168 is formed in an endless shape (a rectangular ring shape in this configuration) that surrounds the upper end of the source electrode layer 157 in a plan view. The source sub-trench 168 borders the upper end of the source electrode layer 157.

[0565] The source sub-trench 168 is formed by excavating a portion of the source insulating layer 156. More specifically, the source sub-trench 168 is formed by excavating from the first main surface 103 of the SiC semiconductor layer 102 through the upper end of the source insulating layer 156 and the upper end of the source electrode layer 157.

[0566] The upper end of the source electrode layer 157 has a shape that is constricted inward relative to the lower end of the source electrode layer 157. The lower end of the source electrode layer 157 is the portion of the source electrode layer 157 located on the bottom wall side of each source trench 155. The first directional width of the upper end of the source electrode layer 157 may be less than the first directional width of the lower end of the source electrode layer 157.

[0567] The source sub-trench 168 is formed in a tapered shape, with a bottom area smaller than the opening area in cross-sectional view. The bottom wall of the source sub-trench 168 may be formed in a convex curve toward the second main surface 104 of the SiC semiconductor layer 102.

[0568] The source region 163, contact region 164, source insulating layer 156, and source electrode layer 157 are exposed from the inner wall of the source sub-trench 168. The first surface region 164a and the second surface region 164b of the contact region 164 are exposed from the inner wall of the source sub-trench 168.

[0569] At least the first region 156a of the source insulating layer 156 is exposed from the bottom wall of the source sub-trench 168. The upper end of the first region 156a in the source insulating layer 156 is located below the first main surface 103 of the SiC semiconductor layer 102.

[0570] Each source trench 155 has an opening edge 169 which includes an inclined portion 170 that slopes downward from the first main surface 103 of the SiC semiconductor layer 102 toward the inside of each source trench 155. The opening edge 169 of each source trench 155 is a corner that connects the first main surface 103 of the SiC semiconductor layer 102 with the side wall of each source trench 155. The inclined portion 170 of each source trench 155 is formed by a source sub-trench 168.

[0571] In this configuration, the inclined portion 170 is formed in a concave curve that curves inward toward the SiC semiconductor layer 102. The inclined portion 170 may also be formed in a convex curve that curves inward toward the source sub-trench 168. The inclined portion 170 mitigates electric field concentration at the opening edge portion 169 of each source trench 155.

[0572] Referring to Figures 24 and 25, the active region 111 has an active main surface 171 that forms part of the first main surface 103 of the SiC semiconductor layer 102. The outer region 112 has an outer main surface 172 that forms part of the first main surface 103 of the SiC semiconductor layer 102. In this embodiment, the outer main surface 172 is connected to the sides 105A to 105D of the SiC semiconductor layer 102.

[0573] The active main surface 171 and the outer main surface 172 face the c-plane of the SiC single crystal, respectively. Furthermore, the active main surface 171 and the outer main surface 172 each have an off-angle θ tilted in the [11-20] direction with respect to the c-plane of the SiC single crystal.

[0574] The outer main surface 172 is located on the second main surface 104 side of the SiC semiconductor layer 102 relative to the active main surface 171. In this embodiment, the outer region 112 is formed by excavating the first main surface 103 of the SiC semiconductor layer 102 toward the second main surface 104 side. Therefore, the outer main surface 172 is formed in a region that is recessed toward the second main surface 104 side of the SiC semiconductor layer 102 relative to the active main surface 171.

[0575] The outer main surface 172 may be located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142. The outer main surface 172 may be formed at a depth position approximately equal to the bottom wall of each source trench 155. The outer main surface 172 may be located substantially coplanar with the bottom wall of each source trench 155.

[0576] The distance between the outer main surface 172 and the second main surface 104 of the SiC semiconductor layer 102 may be approximately equal to the distance between the bottom wall of each source trench 155 and the second main surface 104 of the SiC semiconductor layer 102.

[0577] The outer main surface 172 may be located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each source trench 155. The outer main surface 172 may be located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each source trench 155, within a range of 0 μm to 1 μm.

[0578] The SiC epitaxial layer 107 is exposed from the outer main surface 172. More specifically, the high-concentration region 108 of the SiC epitaxial layer 107 is exposed from the outer main surface 172 of the outer region 112. The outer main surface 172 faces the low-concentration region 109 of the SiC epitaxial layer 107, with the high-concentration region 108 of the SiC epitaxial layer 107 in between.

[0579] In this configuration, the active region 111 is demarcated in a plateau-like manner by the outer region 112. The active region 111 is formed as a plateau-like active plateau 173 that protrudes upward from the outer region 112.

[0580] The active plateau 173 includes an active sidewall 174 connecting the active main surface 171 and the outer main surface 172. The active sidewall 174 demarcates the boundary region between the active region 111 and the outer region 112. The first main surface 103 of the SiC semiconductor layer 102 is formed by the active main surface 171, the outer main surface 172, and the active sidewall 174.

[0581] In this embodiment, the active sidewall 174 extends along the direction Z normal to the active principal surface 171 (outer principal surface 172). The active sidewall 174 is formed by the m-plane and a-plane of the SiC single crystal.

[0582] The active sidewall 174 may have an inclined surface that slopes downward from the active main surface 171 toward the outer main surface 172. The inclination angle of the active sidewall 174 is the angle formed between the active sidewall 174 and the active main surface 171 within the SiC semiconductor layer 102.

[0583] In this case, the inclination angle of the active side wall 174 may be greater than 90° and 135° or less. The inclination angle of the active side wall 174 may be greater than 90° and 95° or less, 95° or more and 100° or less, 100° or more and 110° or less, 110° or more and 120° or less, or 120° or more and 135° or less. Preferably, the inclination angle of the active side wall 174 is greater than 90° and 95° or less.

[0584] The SiC epitaxial layer 107 is exposed from the active sidewall 174. More specifically, the high-concentration region 108 of the SiC epitaxial layer 107 is exposed from the active sidewall 174.

[0585] At least the body region 141 is exposed from the active main surface 171 side of the active sidewall 174. Figures 24 and 25 show an example of a configuration in which the body region 141 and the source region 163 are exposed from the active sidewall 174.

[0586] In the outer region 112, the surface layer of the first main surface 103 (outer main surface 172) of the SiC semiconductor layer 102 contains p + A type diode region 181 (impurity region), a p-type outer deep well region 182, and a p-type field limit structure 183 are formed.

[0587] The diode region 181 is formed in the outer region 112 between the active sidewall 174 and the side surfaces 105A to 105D of the SiC semiconductor layer 102. The diode region 181 is formed with a gap between it and the active sidewall 174 and the side surfaces 105A to 105D.

[0588] The diode region 181 extends in a band-like shape along the active region 111 in a plan view. In this configuration, the diode region 181 is formed in an endless shape (a rectangular ring in this configuration) surrounding the active region 111 in a plan view.

[0589] The diode region 181 overlaps with the source wiring 123 in a plan view. The diode region 181 is electrically connected to the source wiring 123. The diode region 181 forms part of the avalanche current absorption structure.

[0590] The diode region 181 forms a pn junction with the SiC semiconductor layer 102. More specifically, the diode region 181 is located within the SiC epitaxial layer 107. Therefore, the diode region 181 forms a pn junction with the SiC epitaxial layer 107.

[0591] More specifically, the diode region 181 is located within the high-density region 108 of the SiC epitaxial layer 107. Therefore, the diode region 181 forms a pn junction with the high-density region 108. This forms a pn junction diode Dpn with the diode region 181 as the anode and the SiC semiconductor layer 102 as the cathode.

[0592] The entire diode region 181 is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142. The bottom of the diode region 181 is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each source trench 155.

[0593] The bottom of the diode region 181 may be formed at a depth approximately equal to that of the bottom of the contact region 164. The bottom of the diode region 181 may be located on approximately the same plane as the bottom of the contact region 164.

[0594] The p-type impurity concentration in diode region 181 is approximately equal to that in contact region 164. The p-type impurity concentration in diode region 181 is greater than that in body region 141. The p-type impurity concentration in diode region 181 is 1.0 × 10⁻⁶. 18 cm -3 The above 1.0 × 10 21 cm -3 The following is also acceptable.

[0595] The outer deep well region 182 is formed in the region between the active sidewall 174 and the diode region 181 in a plan view. In this configuration, the outer deep well region 182 is formed with a gap extending from the active sidewall 174 toward the diode region 181. The outer deep well region 182 is also referred to as the breakdown voltage adjustment region (breakdown voltage holding region) that adjusts the breakdown voltage of the SiC semiconductor layer 102 in the outer region 112.

[0596] The outer deep well region 182 extends in a band-like manner along the active region 111 in a plan view. In this configuration, the outer deep well region 182 is formed in an endless shape (a rectangular ring in this configuration) surrounding the active region 111 in a plan view.

[0597] The outer deep well region 182 is electrically connected to the source routing wiring 123 via the diode region 181. The outer deep well region 182 may form part of the pn junction diode Dpn. The outer deep well region 182 may form part of the avalanche current absorption structure.

[0598] The entire outer deep well region 182 is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142. The bottom of the outer deep well region 182 is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each source trench 155.

[0599] The bottom of the outer deep well region 182 is located on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom of the diode region 181. The bottom of the outer deep well region 182 may be formed at approximately the same depth as the bottom of each deep well region 165. The bottom of the outer deep well region 182 may be located on approximately the same plane as the bottom of each deep well region 165.

[0600] The distance between the bottom of the outer deep well region 182 and the outer main surface 172 may be approximately equal to the distance between the bottom of each deep well region 165 and the bottom wall of each source trench 155.

[0601] The distance between the bottom of the outer deep well region 182 and the second main surface 104 of the SiC semiconductor layer 102 may be approximately equal to the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102.

[0602] This makes it possible to suppress variations in the distance between the bottom of the outer deep well region 182 and the second main surface 104 of the SiC semiconductor layer 102, and the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102.

[0603] Therefore, the breakdown voltage (e.g., fracture voltage) of the SiC semiconductor layer 102 can be suppressed from being limited by the shape of the outer deep well region 182 and the shape of each deep well region 165, thus enabling an appropriate improvement in breakdown voltage.

[0604] The bottom of the outer deep well region 182 may be located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom of each deep well region 165. The bottom of the outer deep well region 182 may be located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom of each deep well region 165, within a range of 0 μm to 1 μm.

[0605] The inner periphery of the outer deep well region 182 may extend to the vicinity of the boundary region between the active region 111 and the outer region 112. The outer deep well region 182 may cross the boundary region between the active region 111 and the outer region 112.

[0606] The inner periphery of the outer deep well region 182 may cover the corner connecting the active side wall 174 and the outer main surface 172. The inner periphery of the outer deep well region 182 may further extend along the active side wall 174 and connect to the body region 141.

[0607] In this configuration, the outer edge of the outer deep well region 182 covers the diode region 181 from the second main surface 104 side of the SiC semiconductor layer 102. The outer deep well region 182 may overlap the source routing 123 in a plan view. The outer edge of the outer deep well region 182 may be formed with a gap between it and the diode region 181 on the active sidewall 174 side.

[0608] The p-type impurity concentration in the outer deep well region 182 may be less than or equal to the p-type impurity concentration in the diode region 181.

[0609] The p-type impurity concentration in the outer deep well region 182 may be approximately equal to the p-type impurity concentration in each deep well region 165. The p-type impurity concentration in the outer deep well region 182 may be approximately equal to the p-type impurity concentration in the body region 141.

[0610] The p-type impurity concentration in the outer deep well region 182 may exceed the p-type impurity concentration in the body region 141. The p-type impurity concentration in the outer deep well region 182 may be less than the p-type impurity concentration in the body region 141.

[0611] The p-type impurity concentration in the outer deep well region 182 may be less than or equal to the p-type impurity concentration in the contact region 164. The p-type impurity concentration in the outer deep well region 182 may be less than the p-type impurity concentration in the contact region 164. The p-type impurity concentration in the outer deep well region 182 is 1.0 × 10⁻⁶ 17 cm -3 The above 1.0 × 10 19 cm -3 The following is also acceptable.

[0612] The field limit structure 183 is formed in the region between the diode region 181 and the side surfaces 105A to 105D of the SiC semiconductor layer 102 in a plan view. In this embodiment, the field limit structure 183 is formed with a gap extending from the side surfaces 105A to 105D toward the diode region 181.

[0613] The field limit structure 183 includes one or more (for example, two to twenty) field limit regions 184. In this embodiment, the field limit structure 183 includes a group of field limit regions having multiple (five) field limit regions 184A, 184B, 184C, 184D, and 184E.

[0614] The field limit regions 184A to 184E are formed in this order, spaced apart along the direction away from the diode region 181. Each of the field limit regions 184A to 184E extends in a band-like shape along the periphery of the active region 111 in a plan view.

[0615] More specifically, the field limit regions 184A to 184E are formed in an endless shape (in this form, a rectangular ring) surrounding the active region 111 in a plan view. The field limit regions 184A to 184E are also referred to as FLR (Field Limiting Ring) regions.

[0616] In this configuration, the bottom of the field limit regions 184A to 184E is located on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom of the diode region 181.

[0617] In this configuration, the innermost field limit region 184A of the field limit regions 184A to 184E covers the diode region 181 from the second main surface 104 side of the SiC semiconductor layer 102. The field limit region 184A may overlap with the aforementioned source routing wiring 123 in a plan view.

[0618] The field limit region 184A is electrically connected to the source routing wiring 123 via the diode region 181. The field limit region 184A may form part of the pn junction diode Dpn. The field limit region 184A may form part of the avalanche current absorption structure.

[0619] The entire field limit regions 184A to 184E are located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142. The bottom of the field limit regions 184A to 184E are located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each source trench 155.

[0620] The field limit regions 184A to 184E may be formed at approximately the same depth as each deep well region 165 (outer deep well region 182). The bottoms of the field limit regions 184A to 184E may be located on approximately the same plane as the bottoms of each deep well region 165 (outer deep well region 182).

[0621] The bottoms of the field limit regions 184A to 184E may be located on the outer main surface 172 side with respect to the bottom of each deep well region 165 (outer deep well region 182). The bottoms of the field limit regions 184A to 184E may be located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom of each deep well region 165 (outer deep well region 182).

[0622] The widths between adjacent field limit regions 184A to 184E may be different. The widths between adjacent field limit regions 184A to 184E may increase in the direction away from the active region 111. The widths between adjacent field limit regions 184A to 184E may decrease in the direction away from the active region 111.

[0623] The depths of the field limit regions 184A to 184E may be different from each other. The depths of the field limit regions 184A to 184E may decrease in the direction away from the active region 111. The depths of the field limit regions 184A to 184E may increase in the direction away from the active region 111.

[0624] The p-type impurity concentration in field limit regions 184A to 184E may be less than or equal to the p-type impurity concentration in diode region 181. The p-type impurity concentration in field limit regions 184A to 184E may be less than the p-type impurity concentration in diode region 181.

[0625] The p-type impurity concentration in the field limit regions 184A to 184E may be less than or equal to the p-type impurity concentration in the outer deep well region 182. The p-type impurity concentration in the field limit regions 184A to 184E may be less than the p-type impurity concentration in the outer deep well region 182.

[0626] The p-type impurity concentration in the field limit regions 184A to 184E may be greater than or equal to the p-type impurity concentration in the outer deep well region 182.

[0627] The p-type impurity concentration in the field limit region 184A-184E is 1.0 × 10⁻⁶. 15 cm -3 The above 1.0 × 10 18 cm -3 The following conditions may also be met: Preferably, the p-type impurity concentration in the diode region 181 > the p-type impurity concentration in the outer deep well region 182 > the p-type impurity concentration in the field limit regions 184A to 184E.

[0628] The field limit structure 183 mitigates electric field concentration in the outer region 112. The number, width, depth, and p-type impurity concentration of the field limit regions 184 can take various values ​​depending on the electric field to be mitigated.

[0629] In this embodiment, an example was described in which the field limit structure 183 includes one or more field limit regions 184 formed in the region between the diode region 181 and the side surfaces 105A to 105D of the SiC semiconductor layer 102 in a plan view.

[0630] However, the field limit structure 183 may include one or more field limit regions 184 formed in the region between the active sidewall 174 and the diode region 181 in a plan view, instead of the region between the diode region 181 and the side surfaces 105A to 105D of the SiC semiconductor layer 102.

[0631] Furthermore, the field limit structure 183 may include one or more field limit regions 184 formed in the region between the diode region 181 and the side surfaces 105A to 105D of the SiC semiconductor layer 102 in a plan view, and one or more field limit regions 184 formed in the region between the active side wall 174 and the diode region 181 in a plan view.

[0632] In the outer region 112, an outer insulating layer 191 is formed on the first main surface 103 of the SiC semiconductor layer 102. The outer insulating layer 191 forms a part of the main surface insulating layer 113. The outer insulating layer 191 forms a part of the insulating side surfaces 114A to 114D of the main surface insulating layer 113.

[0633] The outer insulating layer 191 selectively covers the diode region 181, the outer deep well region 182, and the field limit structure 183 in the outer region 112. The outer insulating layer 191 is formed in a film-like manner along the active sidewall 174 and the outer main surface 172. On the active main surface 171, the outer insulating layer 191 is connected to the gate insulating layer 148. More specifically, the outer insulating layer 191 is connected to the third region 148c of the gate insulating layer 148.

[0634] The outer insulating layer 191 may contain silicon oxide. The outer insulating layer 191 may contain other insulating films such as silicon nitride. In this embodiment, the outer insulating layer 191 is formed of the same insulating material as the gate insulating layer 148.

[0635] The outer insulating layer 191 includes a first region 191a and a second region 191b. The first region 191a of the outer insulating layer 191 covers the active sidewall 174. The second region 191b of the outer insulating layer 191 covers the outer main surface 172.

[0636] The thickness of the second region 191b of the outer insulating layer 191 may be less than or equal to the thickness of the first region 191a of the outer insulating layer 191.

[0637] The thickness of the first region 191a of the outer insulating layer 191 may be approximately equal to the thickness of the first region 191a of the gate insulating layer 148. The thickness of the second region 191b of the outer insulating layer 191 may be approximately equal to the thickness of the third region 148c of the gate insulating layer 148. Of course, an outer insulating layer 191 with a uniform thickness may be formed.

[0638] Referring to Figures 24 and 25, the SiC semiconductor device 101 further includes a sidewall 192 covering the active sidewall 174. The sidewall 192 protects and reinforces the active plateau 173 from the outer region 112 side.

[0639] Furthermore, the sidewall 192 forms a step-relieving structure that mitigates the step formed between the active main surface 171 and the outer main surface 172. When an upper structure (covering layer) is formed that covers the boundary region between the active region 111 and the outer region 112, the upper structure covers the sidewall 192. The sidewall 192 enhances the flatness of the upper structure.

[0640] The sidewall 192 may have an inclined portion 193 that slopes downward from the active main surface 171 toward the outer main surface 172. The inclined portion 193 can effectively mitigate the step difference.

[0641] The inclined portion 193 of the sidewall 192 may be formed in a concave curve toward the SiC semiconductor layer 102 side. The inclined portion 193 of the sidewall 192 may be formed in a convex curve toward the opposite side of the SiC semiconductor layer 102.

[0642] The inclined portion 193 of the sidewall 192 may extend planarly from the active main surface 171 side to the outer main surface 172 side. The inclined portion 193 of the sidewall 192 may extend linearly from the active main surface 171 side to the outer main surface 172 side.

[0643] The inclined portion 193 of the sidewall 192 may be formed in a downward step shape from the active main surface 171 toward the outer main surface 172. In other words, the inclined portion 193 of the sidewall 192 may have one or more recessed steps toward the outer main surface 172. Multiple steps increase the surface area of ​​the inclined portion 193 of the sidewall 192 and enhance the adhesion force to the upper structure.

[0644] The inclined portion 193 of the sidewall 192 may include a plurality of raised portions that protrude outward from the sidewall 192. The plurality of raised portions increase the surface area of ​​the inclined portion 193 of the sidewall 192 and enhance the adhesion force to the upper structure.

[0645] The inclined portion 193 of the sidewall 192 may include a plurality of recesses that are recessed toward the inside of the sidewall 192. The plurality of recesses increase the surface area of ​​the inclined portion 193 of the sidewall 192 and enhance the adhesion force to the upper structure.

[0646] The sidewall 192 is formed in a self-aligned manner with respect to the active main surface 171. More specifically, the sidewall 192 is formed along the active sidewall 174. In this embodiment, the sidewall 192 is formed in an endless shape (a rectangular ring in this embodiment) surrounding the active region 111 in a plan view.

[0647] The sidewall 192 preferably contains p-type polysilicon with p-type impurities added. In this case, the sidewall 192 can be formed simultaneously with the gate electrode layer 149 and the source electrode layer 157.

[0648] The p-type impurity concentration in the sidewall 192 is greater than or equal to the p-type impurity concentration in the body region 141. More specifically, the p-type impurity concentration in the sidewall 192 is greater than the p-type impurity concentration in the body region 141. The p-type impurities in the sidewall 192 may contain at least one of boron (B), aluminum (Al), indium (In), or gallium (Ga).

[0649] The p-type impurity concentration in sidewall 192 is 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 22 cm -3 The following is also acceptable: The sheet resistance of the sidewall 192 may be between 10Ω / □ and 500Ω / □ (approximately 200Ω / □ in this configuration).

[0650] The p-type impurity concentration of the sidewall 192 may be approximately equal to that of the gate electrode layer 149. The sheet resistance of the sidewall 192 may be approximately equal to that of the gate electrode layer 149.

[0651] The sidewall 192 may contain n-type polysilicon in place of or in addition to p-type polysilicon. The sidewall 192 may contain at least one of tungsten, aluminum, copper, aluminum alloy, or copper alloy in place of or in addition to p-type polysilicon.

[0652] The sidewall 192 may contain insulating material. In this case, the sidewall 192 can improve the insulation of the active region 111 from the outer region 112.

[0653] Referring to Figures 21 to 25, an interlayer insulating layer 201 is formed on the first main surface 103 of the SiC semiconductor layer 102. The interlayer insulating layer 201 forms part of the main surface insulating layer 113. The interlayer insulating layer 201 forms part of the insulating side surfaces 114A to 114D of the main surface insulating layer 113. The main surface insulating layer 113 has a laminated structure including a gate insulating layer 148 (outer insulating layer 191) and the interlayer insulating layer 201.

[0654] The interlayer insulating layer 201 selectively covers the active region 111 and the outer region 112. More specifically, the interlayer insulating layer 201 selectively covers the third region 148c of the gate insulating layer 148 and the outer insulating layer 191.

[0655] The interlayer insulating layer 201 is formed in a film-like manner along the active main surface 171 and the outer main surface 172. The interlayer insulating layer 201 selectively covers the trench gate structure 161, the gate wiring layer 150, and the trench source structure 162 in the active region 111. The interlayer insulating layer 201 selectively covers the diode region 181, the outer deep well region 182, and the field limit structure 183 in the outer region 112.

[0656] The interlayer insulating layer 201 is formed along the outer surface (inclined portion 193) of the sidewall 192 in the boundary region between the active region 111 and the outer region 112. The interlayer insulating layer 201 forms part of the upper structure that covers the sidewall 192.

[0657] The interlayer insulating layer 201 may contain silicon oxide or silicon nitride. The interlayer insulating layer 201 may also contain PSG (Phosphor Silicate Glass) and / or BPSG (Boron Phosphor Silicate Glass) as examples of silicon oxide.

[0658] The interlayer insulating layer 201 may have a laminated structure including a PSG layer and a BPSG layer stacked in this order from the first main surface 103 side of the SiC semiconductor layer 102.

[0659] The interlayer insulating layer 201 has gate contact holes 202, source contact holes 203, and diode contact holes 204. Additionally, the interlayer insulating layer 201 has anchor holes 205.

[0660] The gate contact hole 202 exposes the gate wiring layer 150 in the active region 111. The gate contact hole 202 may be formed in a strip shape along the gate wiring layer 150. The opening edge of the gate contact hole 202 is formed in a convex curve shape toward the inside of the gate contact hole 202.

[0661] The source contact hole 203 exposes the source region 163, contact region 164, and trench source structure 162 in the active region 111. The source contact hole 203 may be formed in a strip shape along the trench source structure 162, etc. The opening edge of the source contact hole 203 is formed in a convex curved shape toward the inside of the source contact hole 203.

[0662] The diode contact hole 204 exposes the diode region 181 in the outer region 112. The diode contact hole 204 may be formed in a strip shape (more specifically, an endless shape) that extends along the diode region 181.

[0663] The diode contact hole 204 may expose the outer deep well region 182 and / or the field limit structure 183. The opening edge of the diode contact hole 204 is formed in a convex curve toward the inside of the diode contact hole 204.

[0664] The anchor holes 205 are formed in the outer region 112 by excavating the interlayer insulating layer 201. In a plan view, the anchor holes 205 are formed in the region between the diode region 181 and the side surfaces 105A to 105D of the SiC semiconductor layer 102. More specifically, in a plan view, the anchor holes 205 are formed in the region between the field limit structure 183 and the side surfaces 105A to 105D of the SiC semiconductor layer 102.

[0665] The anchor hole 205 exposes the first main surface 103 (outer main surface 172) of the SiC semiconductor layer 102. The opening edge of the anchor hole 205 is formed in a convex curved shape that curves inward towards the anchor hole 205.

[0666] Referring to Figure 19, the anchor hole 205 extends in a band shape along the active region 111 in a plan view. In this embodiment, the anchor hole 205 is formed in an endless shape (a rectangular ring in this embodiment) surrounding the active region 111 in a plan view.

[0667] In this configuration, one anchor hole 205 is formed in the portion of the interlayer insulating layer 201 that covers the outer region 112. However, multiple anchor holes 205 may be formed in the portion of the interlayer insulating layer 201 that covers the outer region 112.

[0668] A main surface gate electrode layer 115 and a main surface source electrode layer 121 are formed on the interlayer insulating layer 201. The main surface gate electrode layer 115 and the main surface source electrode layer 121 have a laminated structure that includes a barrier electrode layer 206 and a main electrode layer 207, respectively, which are stacked in this order from the first main surface 103 side of the SiC semiconductor layer 102.

[0669] The barrier electrode layer 206 may have a single-layer structure including a titanium layer or a titanium nitride layer. The barrier electrode layer 206 may have a multilayer structure including a titanium layer and a titanium nitride layer stacked in this order from the first main surface 103 side of the SiC semiconductor layer 102.

[0670] The thickness of the main electrode layer 207 is greater than the thickness of the barrier electrode layer 206. The main electrode layer 207 contains a conductive material having a resistance value smaller than that of the barrier electrode layer 206. The main electrode layer 207 may contain at least one of aluminum, copper, an aluminum alloy, or a copper alloy.

[0671] The main electrode layer 207 may contain at least one of an aluminum-silicon alloy, an aluminum-silicon-copper alloy, or an aluminum-copper alloy. In this embodiment, the main electrode layer 207 contains an aluminum-silicon-copper alloy.

[0672] The outer gate finger 117 of the main surface gate electrode layer 115 penetrates the gate contact hole 202 from above the interlayer insulating layer 201. Within the gate contact hole 202, the outer gate finger 117 is electrically connected to the gate wiring layer 150. As a result, electrical signals from the gate pad 116 are transmitted to the gate electrode layer 149 via the outer gate finger 117.

[0673] The source pad 122 of the main surface source electrode layer 121 extends from above the interlayer insulating layer 201 into the source contact hole 203 and the source sub-trench 168. Within the source contact hole 203 and the source sub-trench 168, the source pad 122 is electrically connected to the source region 163, the contact region 164, and the source electrode layer 157.

[0674] The source electrode layer 157 may be formed using a portion of the source pad 122. The source electrode layer 157 may also be formed by the portion of the source pad 122 that has entered each source trench 155.

[0675] The source routing wiring 123 of the main surface source electrode layer 121 enters the diode contact hole 204 from above the interlayer insulating layer 201. The source routing wiring 123 is electrically connected to the diode region 181 within the diode contact hole 204.

[0676] The source connection portion 124 of the main surface source electrode layer 121 is drawn out from the active region 111 across the sidewall 192 to the outer region 112. The source connection portion 124 forms part of the upper structure that covers the sidewall 192.

[0677] The aforementioned passivation layer 125 is formed on the interlayer insulating layer 201. The passivation layer 125 is formed in a film-like manner along the interlayer insulating layer 201. The passivation layer 125 selectively covers the active region 111 and the outer region 112 through the interlayer insulating layer 201.

[0678] The passivation layer 125 is drawn out from the active region 111 across the sidewall 192 to the outer region 112. The passivation layer 125 forms part of the upper structure that covers the sidewall 192.

[0679] Referring to Figure 24, the passivation layer 125 penetrates the anchor hole 205 from above the interlayer insulating layer 201 in the outer region 112. Within the anchor hole 205, the passivation layer 125 is connected to the first main surface 103 (outer main surface 172) of the SiC semiconductor layer 102. On the outer surface of the passivation layer 125, a recess 211 is formed in the region located above the anchor hole 205, following the shape of the anchor hole 205.

[0680] The aforementioned resin layer 129 is formed on the passivation layer 125. The resin layer 129 is formed in a film-like manner along the passivation layer 125. The resin layer 129 selectively covers the active region 111 and the outer region 112, with the passivation layer 125 and the interlayer insulating layer 201 in between.

[0681] The resin layer 129 is drawn out from the active region 111 across the sidewall 192 to the outer region 112. The resin layer 129 forms part of the upper structure that covers the sidewall 192.

[0682] Referring to Figure 24, the resin layer 129 has an anchor portion that fits into the recess 211 of the passivation layer 125 in the outer region 112. In this way, an anchor structure is formed in the outer region 112 to increase the connection strength of the resin layer 129.

[0683] The anchor structure includes an uneven structure (uneven structure) formed on the first main surface 103 of the SiC semiconductor layer 102 in the outer region 112. More specifically, the uneven structure (anchor structure) includes irregularities formed using the interlayer insulating layer 201 covering the outer main surface 172. Even more specifically, the uneven structure (anchor structure) includes anchor holes 205 formed in the interlayer insulating layer 201.

[0684] The resin layer 129 engages with the anchor hole 205. In this configuration, the resin layer 129 engages with the anchor hole 205 via the passivation layer 125. This increases the connection strength of the resin layer 129 to the first main surface 103 of the SiC semiconductor layer 102, thereby suppressing delamination of the resin layer 129.

[0685] As described above, the SiC semiconductor device 101 can achieve the same effects as those described for the SiC semiconductor device 1. Furthermore, with the SiC semiconductor device 101, the depletion layer can be extended from the boundary region (pn junction) between the SiC semiconductor layer 102 and the deep well region 165 toward the region on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of the gate trench 142.

[0686] This narrows the current path of the short-circuit current flowing between the main surface source electrode layer 121 and the drain electrode layer 133. Furthermore, the depletion layer extending from the boundary region between the SiC semiconductor layer 102 and the deep well region 165 reduces the feedback capacitance Crss inversely. Thus, a SiC semiconductor device 101 can be provided that has improved short-circuit withstand capability and reduced feedback capacitance Crss.

[0687] The depletion layer extending from the boundary region (pn junction) between the SiC semiconductor layer 102 and the deep well region 165 may overlap the bottom wall of the gate trench 142. In this case, the depletion layer extending from the bottom of the deep well region 165 may overlap the bottom wall of the gate trench 142.

[0688] Furthermore, the SiC semiconductor device 101 allows for an increase in the area occupied by the depletion layer in the SiC semiconductor layer 102, thereby reducing the feedback capacitance Crss inversely. The feedback capacitance Crss is the capacitance between the gate electrode layer 149 and the drain electrode layer 133.

[0689] Furthermore, in the SiC semiconductor device 101, the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102 is approximately constant. This suppresses variations in the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102.

[0690] Therefore, the breakdown voltage (e.g., fracture voltage) of the SiC semiconductor layer 102 can be suppressed from being limited by the shape of the deep well region 165, thus enabling an appropriate improvement in breakdown voltage.

[0691] Furthermore, in the SiC semiconductor device 101, a diode region 181 is formed in the outer region 112. This diode region 181 is electrically connected to the main surface source electrode layer 121. This allows the avalanche current generated in the outer region 112 to flow into the main surface source electrode layer 121 via the diode region 181.

[0692] In other words, the avalanche current generated in the outer region 112 can be absorbed by the diode region 181 and the main surface source electrode layer 121. As a result, the operational stability of the MISFET can be improved.

[0693] Furthermore, in the SiC semiconductor device 101, an outer deep well region 182 is formed in the outer region 112. This allows the breakdown voltage of the SiC semiconductor layer 102 to be adjusted in the outer region 112.

[0694] In particular, according to the SiC semiconductor device 101, the outer deep well region 182 is formed at approximately the same depth as the deep well region 165. More specifically, the bottom of the outer deep well region 182 lies on approximately the same plane as the bottom of the deep well region 165.

[0695] The distance between the bottom of the outer deep well region 182 and the second main surface 104 of the SiC semiconductor layer 102 is approximately equal to the distance between the bottom of the deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102.

[0696] This makes it possible to suppress variations in the distance between the bottom of the outer deep well region 182 and the second main surface 104 of the SiC semiconductor layer 102, and the distance between the bottom of the deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102.

[0697] Therefore, the breakdown voltage (e.g., fracture voltage) of the SiC semiconductor layer 102 can be suppressed from being limited by the shape of the outer deep well region 182 and the shape of the deep well region 165. As a result, the breakdown voltage can be appropriately improved.

[0698] In particular, in the SiC semiconductor device 101, the outer region 112 is formed in the region on the second main surface 104 side of the SiC semiconductor layer 102 relative to the active region 111. This allows the position of the bottom of the outer deep well region 182 to be appropriately brought closer to the position of the bottom of the deep well region 165.

[0699] In other words, when forming the outer deep well region 182, it becomes unnecessary to introduce p-type impurities at a relatively deep position in the surface layer of the first main surface 103 of the SiC semiconductor layer 102. Therefore, it is possible to appropriately suppress a large displacement between the position of the bottom of the outer deep well region 182 and the position of the bottom of the deep well region 165.

[0700] Furthermore, in the SiC semiconductor device 101, the outer main surface 172 of the outer region 112 is located on almost the same plane as the bottom wall of the source trench 155. As a result, when p-type impurities are introduced into the bottom wall of the source trench 155 and the outer main surface 172 of the outer region 112 with equal energy, the deep well region 165 and the outer deep well region 182 can be formed at approximately equal depths.

[0701] As a result, the large displacement of the bottom position of the outer deep well region 182 relative to the bottom position of the deep well region 165 can be suppressed more effectively.

[0702] Furthermore, in the SiC semiconductor device 101, a field limit structure 183 is formed in the outer region 112. This allows for an electric field relaxation effect in the outer region 112 due to the field limit structure 183. Therefore, the fracture resistance of the SiC semiconductor layer 102 can be appropriately improved.

[0703] Furthermore, according to the SiC semiconductor device 101, the active region 111 is formed as a plateau-shaped active plateau 173. The active plateau 173 includes an active side wall 174 that connects the active main surface 171 of the active region 111 and the outer main surface 172 of the outer region 112.

[0704] A step-relieving structure is formed in the region between the active main surface 171 and the outer main surface 172 to mitigate the step difference between the active main surface 171 and the outer main surface 172. The step-relieving structure includes a side wall 192.

[0705] This allows for a proper reduction in the step difference between the active main surface 171 and the outer main surface 172. Thus, the flatness of the upper layer structure formed on the sidewall 192 can be appropriately improved. In the SiC semiconductor device 101, an example of the upper layer structure includes an interlayer insulating layer 201, a main surface source electrode layer 121, a passivation layer 125, and a resin layer 129.

[0706] Furthermore, in the SiC semiconductor device 101, an anchor structure is formed in the outer region 112 to increase the connection strength of the resin layer 129. The anchor structure includes an uneven structure (Uneven Structure) formed on the first main surface 103 of the SiC semiconductor layer 102 in the outer region 112.

[0707] More specifically, the uneven structure (anchor structure) includes irregularities formed using the interlayer insulating layer 201 formed on the first main surface 103 of the SiC semiconductor layer 102 in the outer region 112. Even more specifically, the uneven structure (anchor structure) includes anchor holes 205 formed in the interlayer insulating layer 201.

[0708] The resin layer 129 engages with the anchor hole 205. In this configuration, the resin layer 129 engages with the anchor hole 205 via the passivation layer 125. This increases the connection strength of the resin layer 129 to the first main surface 103 of the SiC semiconductor layer 102, thereby effectively suppressing delamination of the resin layer 129.

[0709] Furthermore, in the SiC semiconductor device 101, a trench gate structure 161 is formed in which a gate electrode layer 149 is embedded in a gate trench 142 with a gate insulating layer 148 in between. In this trench gate structure 161, the gate electrode layer 149 is covered by a low-resistance electrode layer 167 in the limited space of the gate trench 142. With such a structure, the effects explained with reference to Figure 26 can be achieved.

[0710] Figure 26 is a graph illustrating the sheet resistance within the gate trench 142. In Figure 26, the vertical axis represents sheet resistance [Ω / □], and the horizontal axis represents the item. Figure 26 shows the first bar graph BL1, the second bar graph BL2, and the third bar graph BL3.

[0711] The first bar graph BL1 represents the sheet resistance within the gate trench 142 embedded with n-type polysilicon. The second bar graph BL2 represents the sheet resistance within the gate trench 142 embedded with p-type polysilicon.

[0712] The third bar graph, BL3, represents the sheet resistance within the gate trench 142 into which the gate electrode layer 149 (p-type polysilicon) and the low-resistance electrode layer 167 are embedded. Here, we will describe the case where the low-resistance electrode layer 167 is made of TiSi2 (p-type titanium silicide) as an example of polyside (silicide).

[0713] Referring to the first bar graph BL1, the sheet resistance in the gate trench 142 embedded with n-type polysilicon was 10Ω / □. Referring to the second bar graph BL2, the sheet resistance in the gate trench 142 embedded with p-type polysilicon was 200Ω / □. Referring to the third bar graph BL3, the sheet resistance in the gate trench 142 embedded with gate electrode layer 149 (p-type polysilicon) and low-resistance electrode layer 167 was 2Ω / □.

[0714] p-type polysilicon has a different work function than n-type polysilicon. In a structure where p-type polysilicon is embedded in the gate trench 142, the gate threshold voltage Vth can be increased by approximately 1V.

[0715] However, p-type polysilicon has a sheet resistance that is tens of times (20 times in this case) higher than that of n-type polysilicon. Therefore, when p-type polysilicon is used as the material for the gate electrode layer 149, energy loss increases significantly with increasing parasitic resistance in the gate trench 142 (hereinafter simply referred to as "gate resistance").

[0716] In contrast, a structure having a low-resistance electrode layer 167 on top of a gate electrode layer 149 (p-type polysilicon) can reduce the sheet resistance to less than 1 / 100th compared to a structure without the low-resistance electrode layer 167. In other words, a structure with a low-resistance electrode layer 167 can reduce the sheet resistance to less than 1 / 5th compared to a gate electrode layer 149 containing n-type polysilicon.

[0717] Thus, with a structure having a low-resistance electrode layer 167, the sheet resistance in the gate trench 142 can be reduced while increasing the gate threshold voltage Vth (for example, by about 1V). As a result, the gate resistance can be reduced, allowing the current to be efficiently diffused along the trench gate structure 161. Consequently, the switching delay can be shortened.

[0718] Furthermore, the structure having a low-resistance electrode layer 167 eliminates the need to increase the p-type impurity concentration in the body region 141 and the contact region 164. Therefore, the gate threshold voltage Vth can be appropriately increased while suppressing an increase in channel resistance.

[0719] The low-resistance electrode layer 167 may include at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, or WSi2. In particular, NiSi, CoSi2, and TiSi2 among these species are suitable as polyside layers for forming the low-resistance electrode layer 167 because their resistivity values ​​and temperature dependence are relatively small.

[0720] Further verification by the inventors revealed that when TiSi2 was used as the material for the low-resistance electrode layer 167, an increase in gate-source leakage current was observed when a low electric field was applied. In contrast, when CoSi2 was used, no increase in gate-source leakage current was observed when a low electric field was applied. Considering this point, CoSi2 is considered the most preferable material for the polyside layer forming the low-resistance electrode layer 167.

[0721] Furthermore, in the SiC semiconductor device 101, the gate wiring layer 150 is covered with a low-resistance electrode layer 167. This also helps to reduce the gate resistance in the gate wiring layer 150.

[0722] In particular, in a structure in which the gate electrode layer 149 and the gate wiring layer 150 are covered by a low-resistance electrode layer 167, current can be efficiently diffused along the trench gate structure 161. Therefore, the switching delay can be appropriately reduced.

[0723] Figure 27 is an enlarged view of the region corresponding to Figure 20, and shows an enlarged view of the SiC semiconductor device 221 according to the fourth embodiment of this disclosure. Figure 28 is a cross-sectional view along the line XXVIII-XXVIII shown in Figure 27. Hereinafter, structures corresponding to the structures described for the SiC semiconductor device 101 are given the same reference numerals and their descriptions are omitted.

[0724] Referring to Figures 27 and 28, the SiC semiconductor device 221 includes an outer gate trench 222 formed on the first main surface 103 of the SiC semiconductor layer 102 in the active region 111. The outer gate trench 222 extends in a band shape along the periphery of the active region 111.

[0725] The outer gate trench 222 is formed in the region directly beneath the outer gate finger 117 on the first main surface 103 of the SiC semiconductor layer 102. The outer gate trench 222 extends along the outer gate finger 117.

[0726] More specifically, the outer gate trench 222 is formed along three sides 105A, 105B, and 105D of the SiC semiconductor layer 102 so as to partition the inner region of the active region 111 from three directions. The outer gate trench 222 may be formed in an endless shape (e.g., a quadrilateral ring) surrounding the inner region of the active region 111.

[0727] The outer gate trench 222 communicates with the contact trench portion 144 of each gate trench 142. As a result, the outer gate trench 222 and the gate trenches 142 are formed by a single trench.

[0728] A gate wiring layer 150 is embedded in the outer gate trench 222. The gate wiring layer 150 is connected to the gate electrode layer 149 at the communication point between the gate trench 142 and the outer gate trench 222.

[0729] A low-resistance electrode layer 167 covering the gate wiring layer 150 is formed in the outer gate trench 222. In this case, the low-resistance electrode layer 167 covering the gate electrode layer 149 and the low-resistance electrode layer 167 covering the gate wiring layer 150 are located within a single trench.

[0730] As described above, the SiC semiconductor device 221 can achieve the same effects as those described for the SiC semiconductor device 101. Furthermore, with the SiC semiconductor device 221, it is not necessary to draw the gate wiring layer 150 onto the first main surface 103 of the SiC semiconductor layer 102.

[0731] This prevents the gate wiring layer 150 from facing the SiC semiconductor layer 102 across the gate insulating layer 148 at the opening edge portion 146 of the gate trench 142 (outer gate trench 222). As a result, the concentration of the electric field at the opening edge portion 146 of the gate trench 142 (outer gate trench 222) can be suppressed.

[0732] Figure 29 is an enlarged view of the region corresponding to Figure 23, and shows an enlarged view of the SiC semiconductor device 231 according to the fifth embodiment of this disclosure. In the following, structures corresponding to the structure described for the SiC semiconductor device 101 are given the same reference numerals and their descriptions are omitted.

[0733] Referring to Figure 29, in this embodiment, the SiC epitaxial layer 107 includes a high-concentration region 108, a low-concentration region 109, and a concentration gradient region 232 interposed between the high-concentration region 108 and the low-concentration region 109.

[0734] The concentration gradient region 232 is formed in the SiC epitaxial layer 107 not only in the active region 111 but also in the outer region 112. The concentration gradient region 232 is formed throughout the entire SiC epitaxial layer 107.

[0735] The concentration gradient region 232 has a concentration gradient in which the n-type impurity concentration gradually decreases from the high-concentration region 108 to the low-concentration region 109. In other words, the concentration gradient region 232 has a concentration gradient in which the n-type impurity concentration gradually increases from the low-concentration region 109 to the high-concentration region 108. The concentration gradient region 232 suppresses abrupt fluctuations in the n-type impurity concentration in the region between the high-concentration region 108 and the low-concentration region 109.

[0736] When the SiC epitaxial layer 107 includes a concentration gradient region 232, it is preferable that the n-type impurity concentration in the high-concentration region 108 is 1.5 times or more and 5 times or less than the n-type impurity concentration in the low-concentration region 109. The n-type impurity concentration in the high-concentration region 108 may also be 3 times or more and 5 times or less than the n-type impurity concentration in the low-concentration region 109.

[0737] The thickness of the concentration gradient region 232 may be 0.5 μm or more and 2.0 μm or less. The thickness of the concentration gradient region 232 may be 0.5 μm or more and 1.0 μm or less, 1.0 μm or more and 1.5 μm or less, or 1.5 μm or more and 2.0 μm or less.

[0738] Although a detailed explanation is omitted, the aforementioned gate trench 142, source trench 155, deep well region 165, outer deep well region 182, etc., are formed in the high-concentration region 108.

[0739] In other words, the aforementioned gate trench 142, source trench 155, deep well region 165, outer deep well region 182, etc., are formed in the SiC semiconductor layer 102 in the region on the first main surface 103 side relative to the boundary region of the high-concentration region 108 and the concentration gradient region 232.

[0740] As described above, the SiC semiconductor device 231 can achieve the same effects as those described for the SiC semiconductor device 101.

[0741] Figure 30 is an enlarged view of the region corresponding to Figure 20, and shows an enlarged view of the SiC semiconductor device 241 according to the sixth embodiment of this disclosure. In the following, structures corresponding to the structure described for the SiC semiconductor device 101 are given the same reference numerals and their descriptions are omitted.

[0742] Referring to Figure 30, in this embodiment, the gate trench 142 is formed in a grid shape in plan view. More specifically, the gate trench 142 includes a plurality of first gate trenches 242 and a plurality of second gate trenches 243. The plurality of first gate trenches 242 and the plurality of second gate trenches 243 form an active trench section 143.

[0743] Multiple first gate trenches 242 are formed at intervals in the second direction Y and are each formed in a strip-like shape extending along the first direction X. In a plan view, the multiple first gate trenches 242 form a striped pattern as a whole.

[0744] In each first gate trench 242, the sidewalls forming the longer sides are formed by the a-plane of the SiC single crystal. In each first gate trench 242, the sidewalls forming the shorter sides are formed by the m-plane of the SiC single crystal.

[0745] Multiple second gate trenches 243 are formed at intervals in the first direction X and are each formed in a strip-like shape extending along the second direction Y. In a plan view, the multiple second gate trenches 243 are formed in a striped pattern as a whole.

[0746] In each second gate trench 243, the sidewalls forming the longer sides are formed by the m-plane of the SiC single crystal. In each second gate trench 243, the sidewalls forming the shorter sides are formed by the a-plane of the SiC single crystal.

[0747] Multiple first gate trenches 242 and multiple second gate trenches 243 intersect with each other. This forms a single gate trench 142 in a grid shape in plan view. Multiple cell regions 244 are partitioned within the area surrounded by the gate trench 142.

[0748] Multiple cell regions 244 are arranged in a matrix with spacing in the first direction X and the second direction Y in a plan view. Multiple cell regions 244 are formed in a rectangular shape in a plan view. In each cell region 244, the body region 141 is exposed from the side wall of the gate trench 142. The body region 141 is exposed in the gate trench 142 from the side wall formed by the m-plane and a-plane of the SiC single crystal.

[0749] Of course, the gate trench 142 may be formed in a honeycomb shape as one aspect of a grid shape in plan view. In this case, the multiple cell regions 244 may be arranged in a staggered pattern with spacing in the first direction X and the second direction Y. Also, in this case, the multiple cell regions 244 may be formed in a hexagonal shape in plan view.

[0750] Each source trench 155 is formed in the center of each cell region 244 in a plan view. Each source trench 155 is formed as a pattern that appears once on the cross-section when each cell region 244 is cut along the first direction X. Furthermore, each source trench 155 is formed as a pattern that appears once on the cross-section when each cell region 244 is cut along the second direction Y.

[0751] Each source trench 155 is more specifically formed in a square shape in plan view. The four side walls of each source trench 155 are formed by the m-plane and a-plane of the SiC single crystal.

[0752] The planar shape of each source trench 155 is arbitrary. Each source trench 155 may be formed in a polygonal shape such as a triangle, pentagon, or hexagon, or in a circular or elliptical shape when viewed from above.

[0753] The cross-sectional view along the line XXI-XXI in Figure 30 corresponds to the cross-sectional view shown in Figure 21. The cross-sectional view along the line XXII-XXII in Figure 30 corresponds to the cross-sectional view shown in Figure 22.

[0754] As described above, the SiC semiconductor device 241 can achieve the same effects as those described for the SiC semiconductor device 101.

[0755] While embodiments of this disclosure have been described, embodiments of this disclosure can be implemented in other forms as well.

[0756] In the embodiments described above, a configuration was described in which the sides 5A, 105A and 5C, 105C of the SiC semiconductor layer 2,102 face the a-plane of the SiC single crystal, and the sides 5B, 105B and 5D, 105D face the m-plane of the SiC single crystal. However, a configuration in which the sides 5A, 105A and 5C, 105C face the m-plane of the SiC single crystal, and the sides 5B, 105B and 5D, 105D face the a-plane of the SiC single crystal may also be adopted.

[0757] In the embodiments described above, examples were given in which continuously extending, strip-shaped modification lines 22A to 22D were formed. However, in the embodiments described above, the modification lines 22A to 22D may be formed in a dashed strip shape. In other words, the modification lines 22A to 22D may be formed in an intermittently extending strip shape. In this case, one, two, or three of the modification lines 22A to 22D may be formed in a dashed strip shape, and the rest may be formed in a strip shape.

[0758] In the third to sixth embodiments described above, an example was described in which a plurality of gate trenches 142 (first gate trench 242) extending along the m-axis direction ([1-100] direction) of the SiC single crystal were formed.

[0759] However, multiple gate trenches 142 (first gate trench 242) extending along the a-axis direction ([11-20] direction) of the SiC single crystal may be formed. In this case, multiple source trenches 155 extending along the a-axis direction ([11-20] direction) of the SiC single crystal are formed.

[0760] In the third to sixth embodiments described above, an example was described in which the source electrode layer 157 is embedded in the source trench 155 with the source insulating layer 156 in between. However, the source electrode layer 157 may also be embedded directly in the source trench 155 without the source insulating layer 156.

[0761] In the third to sixth embodiments described above, examples were given in which the source insulating layer 156 was formed along the side walls and bottom walls of the source trench 155.

[0762] However, the source insulating layer 156 may be formed along the side walls of the source trench 155 so as to expose the bottom wall of the source trench 155. The source insulating layer 156 may be formed along the side walls and bottom wall of the source trench 155 so as to expose a portion of the bottom wall of the source trench 155.

[0763] Furthermore, the source insulating layer 156 may be formed along the bottom wall of the source trench 155 so as to expose the side wall of the source trench 155. The source insulating layer 156 may also be formed along the side wall and bottom wall of the source trench 155 so as to expose a portion of the side wall of the source trench 155.

[0764] In the third to sixth embodiments described above, examples were given in which a gate electrode layer 149 and a gate wiring layer 150 containing p-type polysilicon doped with p-type impurities were formed. However, if the increase in gate threshold voltage Vth is not a concern, the gate electrode layer 149 and the gate wiring layer 150 may contain n-type polysilicon doped with n-type impurities instead of or in addition to p-type polysilicon.

[0765] In this case, the low-resistance electrode layer 167 may be formed by silicideizing the portion of the gate electrode layer 149 (n-type polysilicon) that forms the surface layer with a metallic material. In other words, the low-resistance electrode layer 167 may contain n-type polysilicon. With such a structure, the gate resistance can be reduced.

[0766] In the aforementioned third to sixth embodiments, n + Instead of the type SiC semiconductor substrate 106, p + A SiC semiconductor substrate (106) of type 106 may be used. This structure allows for the provision of an IGBT (Insulated Gate Bipolar Transistor) instead of a MISFET. In this case, in each of the embodiments described above, the "source" of the MISFET is replaced with the "emitter" of the IGBT, and the "drain" of the MISFET is replaced with the "collector" of the IGBT.

[0767] In each of the embodiments described above, a structure in which the conductivity type of each semiconductor portion is reversed may be adopted. That is, the p-type portion may be made n-type, and the n-type portion may be made p-type.

[0768] The embodiments described above can also be applied to semiconductor devices using semiconductor materials other than SiC. The semiconductor material other than SiC may be a compound semiconductor material. The compound semiconductor material may be either gallium nitride (GaN) or gallium oxide (Ga2O3), or both.

[0769] For example, the third to sixth embodiments described above may be compound semiconductor devices equipped with vertical compound semiconductor MISFETs in which a compound semiconductor material is used instead of SiC. In the compound semiconductor, magnesium may be used as the p-type impurity (acceptor). Also, germanium (Ge), oxygen (O), or silicon (Si) may be used as the n-type impurity (donor).

[0770] Examples of features extracted from this specification and drawings are shown below.

[0771] [A1] A SiC semiconductor device comprising a SiC semiconductor layer having a stacked structure including a SiC semiconductor substrate that forms part of the second main surface and the side surface, and a SiC epitaxial layer that forms part of the first main surface and the side surface, the SiC semiconductor layer having a stacked structure including a first main surface as an element forming surface having an off-angle tilted in the a-axis direction with respect to the c-plane of the SiC single crystal, a second main surface opposite to the first main surface, and a side surface that faces the a-plane of the SiC single crystal and has an angle less than the off-angle with respect to the normal when the normal to the first main surface is set to 0°, and a plurality of modified layers that are modified to have different properties from the SiC single crystal, formed at intervals in the thickness direction in the portion of the SiC semiconductor substrate that is spaced apart from the SiC epitaxial layer toward the second main surface on the side surface.

[0772] [A2] A SiC semiconductor layer comprising a SiC semiconductor layer having a stacked structure including a SiC semiconductor substrate that forms the second main surface and a part of the side surface, and a SiC epitaxial layer that forms the first main surface and a part of the side surface, and a plurality of modified layers that are formed on the side surface at a distance from the SiC epitaxial layer toward the second main surface toward the second main surface and a portion of the side surface, and are spaced apart in the thickness direction in the portion made up of the SiC semiconductor substrate at a distance from the SiC epitaxial layer toward the second main surface toward the side surface, and which have properties different from those of the SiC single crystal.

[0773] [A3] The SiC semiconductor device according to A1 or A2, wherein the second main surface of the SiC semiconductor layer is a ground surface.

[0774] [A4] The SiC semiconductor device according to any one of A1 to A3, wherein the SiC semiconductor layer has a thickness of 40 μm or more and 200 μm or less.

[0775] [A5] A SiC semiconductor device according to any one of A1 to A4, wherein the plurality of modified layers are each formed in a strip shape extending along the m-axis direction of the SiC single crystal.

[0776] [A6] A SiC semiconductor device according to any one of A1 to A5, wherein the plurality of modified layers are formed offset from each other in the a-axis direction of the SiC single crystal in a cross-sectional view.

[0777] [A7] The SiC semiconductor device according to A6, wherein, with respect to the a-axis direction of the SiC single crystal, the distance between the outermost and innermost modified layer among the plurality of modified layers is less than the value obtained by multiplying the thickness of the SiC semiconductor layer by tanθ (θ: the off-angle).

[0778] [A8] The SiC semiconductor device according to any one of A1 to A7, wherein the side surface of the SiC semiconductor layer has a raised portion with a plurality of modified layers as the top or base.

[0779] [A9] A SiC semiconductor device according to any one of A1 to A8, wherein the plurality of modified layers are formed with a gap between them from the second main surface to the first main surface of the SiC semiconductor layer.

[0780] [A10] A SiC semiconductor device according to any one of A1 to A9, comprising two to six of the modified layers.

[0781] [A11] The SiC semiconductor device according to any one of A1 to A10, wherein the SiC semiconductor layer has a second surface which is a cleavage plane facing the m-plane of the SiC single crystal.

[0782] [A12] The SiC semiconductor device according to A11, further comprising one or more second modified layers formed on the second side surface at a distance from the SiC epitaxial layer toward the second main surface side, wherein the second modified layer is modified to have properties different from those of the SiC single crystal.

[0783] [A13] The SiC semiconductor device according to A11 or A12, wherein the second side surface extends planarly along the normal to the first main surface.

[0784] [A14] The SiC semiconductor device according to any one of A1 to A13, wherein the SiC single crystal is a 2H (Hexagonal)-SiC single crystal, a 4H-SiC single crystal, or a 6H-SiC single crystal.

[0785] [A15] The SiC semiconductor device described in any one of A1 to A14, wherein the off-angle is greater than 0° and less than or equal to 10°, greater than 0° and less than or equal to 5°, or greater than 0° and less than 4°.

[0786] [A16] A SiC semiconductor device according to any one of A1 to A15, further comprising: an insulating layer covering the SiC epitaxial layer on the first main surface and having insulating sidewalls connected to the side surface; and a first electrode formed on the insulating layer at a distance inward from the side surface.

[0787] [A17] The SiC semiconductor device according to A16, further comprising a resin layer formed on the insulating layer at a distance from the side surface inward and having an opening for exposing the first electrode.

[0788] [A18] The SiC semiconductor device according to any one of A1 to A17, further comprising a second electrode covering the second main surface.

[0789] [B1] A SiC semiconductor device comprising a stacked structure including a SiC semiconductor substrate and a SiC epitaxial layer, the SiC semiconductor layer having an element formation surface made of the SiC epitaxial layer and having an off-angle introduced which is inclined in the off-direction with respect to the c-plane of a SiC single crystal, and a SiC semiconductor layer having a side surface that extends in a direction orthogonal to the off-direction and which is inclined at an angle less than the off-angle with respect to the normal to the element formation surface when the normal to the normal is set to 0°, and a plurality of modified layers formed at intervals in the thickness direction on the portion made of the SiC semiconductor substrate on the side surface so as to expose the SiC epitaxial layer, and which are modified to have properties different from the SiC semiconductor substrate.

[0790] [B2] The SiC semiconductor device according to B1, wherein the plurality of modified layers are formed offset from each other in the off direction in a cross-sectional view.

[0791] [B3] The SiC semiconductor device according to B1 or B2, wherein the side surface of the SiC semiconductor layer has a raised portion with a plurality of modified layers as the top or base.

[0792] [B4] The SiC semiconductor device according to any one of B1 to B3, wherein the SiC semiconductor substrate contains a first conductivity type impurity, and the SiC epitaxial layer contains a first conductivity type impurity and has an impurity concentration less than the impurity concentration of the SiC semiconductor substrate.

[0793] [B5] The SiC semiconductor device according to any one of B1 to B4, wherein the SiC epitaxial layer has a thickness less than the thickness of the SiC semiconductor substrate.

[0794] [B6] The SiC semiconductor device according to any one of B1 to B5, wherein the side surface of the SiC semiconductor layer is a cleavage plane.

[0795] [B7] A SiC semiconductor device according to any one of B1 to B6, wherein the plurality of modified layers extend in a strip shape along the boundary between the SiC semiconductor substrate and the SiC epitaxial layer.

[0796] [B8] The off-direction is set to the direction of the arrangement of nearest-neighbor Si atoms in a plan view of the silicon plane of the SiC single crystal viewed from the c-axis, according to any one of B1 to B7, SiC semiconductor device.

[0797] [B9] The SiC semiconductor device according to any one of B1 to B8, wherein the SiC semiconductor layer includes a second side surface extending in the off direction.

[0798] [B10] The SiC semiconductor device according to B9, further comprising a second modified layer formed in the thickness direction on the second side surface at a distance from the SiC epitaxial layer on the portion made of the SiC semiconductor substrate, and modified to have different properties from the SiC semiconductor substrate.

[0799] [B11] The SiC semiconductor device according to B9 or B10, wherein the second side surface is a cleavage plane.

[0800] [B12] A SiC semiconductor device according to any one of B1 to B11, further comprising an insulating layer covering the SiC epitaxial layer, and a first electrode formed on the insulating layer and electrically connected to the SiC epitaxial layer.

[0801] [B13] The SiC semiconductor device according to B12, wherein the insulating layer has an insulating side surface that is continuous with the side surface of the SiC semiconductor layer.

[0802] [B14] The SiC semiconductor device according to B13, wherein the insulating side surface is a cleavage surface.

[0803] [B15] The SiC semiconductor device according to any one of B12 to B14, wherein the first electrode is formed on the insulating layer at a distance from the side surface of the SiC semiconductor layer.

[0804] [B16] A SiC semiconductor device according to any one of B12 to B15, further comprising a passivation layer that partially covers the first electrode on the insulating layer, and a resin layer that covers the passivation layer.

[0805] [B17] A SiC semiconductor device according to any one of B1 to B16, further comprising a second electrode electrically connected to the SiC semiconductor substrate and covering the SiC semiconductor substrate on the opposite side of the SiC epitaxial layer.

[0806] [B18] The SiC semiconductor device according to any one of B1 to B17, wherein the SiC semiconductor layer consists of a 2H (Hexagonal)-SiC single crystal, a 4H-SiC single crystal, or a 6H-SiC single crystal.

[0807] [B19] The SiC semiconductor device according to any one of B1 to B18, further comprising a diode or a field-effect transistor formed on the element formation surface.

[0808] [C1] A SiC chip having a first main surface on one side, a second main surface and a side surface on the other side, A semiconductor region of a first conductivity type formed on the surface layer of the first main surface so as to be exposed from the first main surface and the side surface, At the peripheral edge of the first main surface, a pn connection region formed on the surface layer of the first main surface, A second conductivity type impurity region is formed in the surface layer of the semiconductor region at the periphery of the first main surface, and forms the semiconductor region and the pn connection region. It includes a plurality of modified lines formed on the side surface at intervals from the depth position of the pn connection region toward the second main surface within the thickness range between the pn connection region and the second main surface, which are modified to have properties different from SiC, A SiC semiconductor device wherein multiple modification lines are formed on the side surface of the semiconductor region at intervals from each other, extending from a depth position at the bottom of the semiconductor region toward the second main surface.

[0809] [C2] The SiC semiconductor device according to C1, wherein the pn connection region is formed with a gap inward from the side surface to the first main surface.

[0810] [C3] An active region provided in the inner part of the first main surface, The outer region provided on the periphery of the first main surface further includes, The pn connection region is formed in the outer region, as described in C1 or C2, for the SiC semiconductor device.

[0811] [C4] The SiC semiconductor device according to C3, further comprising a diode structure formed on the first main surface of the active region.

[0812] [C5] The diode structure is A diode region formed on the surface layer of the first main surface of the active region, A SiC semiconductor device according to C4, comprising an electrode electrically connected to the diode region on the first main surface.

[0813] [C6] The SiC semiconductor device according to any one of C3 to C6, further comprising a field-effect type transistor structure formed on the first main surface of the active region.

[0814] [C7] The aforementioned transistor structure is A body region formed on the surface layer of the first main surface of the active region, A trench gate structure formed on the first main surface so as to penetrate the body region, The SiC semiconductor device according to C6, comprising a source region formed in a region along the trench gate structure in the surface layer of the body region.

[0815] [C8] The SiC semiconductor device according to C7, wherein the plurality of modification lines are formed on the side surface of the trench gate structure at intervals from each other, from the depth position of the bottom wall toward the second main surface.

[0816] [C9] The active region has an active main surface which is a part of the first main surface, The outer region has an outer main surface that is recessed toward the second main surface with respect to the active main surface, so as to divide the active region in a plateau-like manner. The SiC semiconductor device according to C7 or C8, wherein the pn connection region is formed on the surface layer of the outer main surface.

[0817] [C10] The SiC semiconductor device described in C9, wherein the outer main surface is connected to the side surface.

[0818] [C11] The SiC semiconductor device according to any one of claims 1 to 10, further comprising an insulating film covering the pn connection region on the first main surface.

[0819] [C12] The SiC semiconductor device according to C11, further comprising a resin layer covering the insulating film.

[0820] [C13] A SiC chip having a first main surface on one side, a second main surface and a side surface on the other side, A plateau is defined on the first main surface by a first surface portion located in the inner part of the first main surface, a second surface portion formed on the periphery of the first main surface so as to be recessed from the first surface portion toward the second main surface, and a connecting side wall connecting the first surface portion and the second surface portion. A semiconductor region of a first conductivity type formed on the surface layer of the second surface so as to be exposed from the second surface and the side surface, The pn connection region formed on the surface layer of the second surface, A second conductivity type impurity region is formed on the surface of the semiconductor region and forms the semiconductor region and the pn connection region, It includes a plurality of modified lines formed on the side surface at intervals from the depth position of the pn connection region toward the second main surface within the thickness range between the pn connection region and the second main surface, which are modified to have properties different from SiC, A SiC semiconductor device wherein multiple modification lines are formed on the side surface of the semiconductor region at intervals from each other, extending from a depth position at the bottom of the semiconductor region toward the second main surface.

[0821] [C14] The second surface is connected to the side surface, The SiC semiconductor device according to C13, wherein the pn connection region is formed with a gap between the side surface and the first surface.

[0822] [C15] A body region formed on the surface of the first surface, A trench gate structure formed on the first surface so as to penetrate the body region, A SiC semiconductor device according to C13 or C14, further comprising a source region formed in the surface layer of the body region in a region along the trench gate structure.

[0823] [C16] The SiC semiconductor device according to C15, wherein the second surface is located on the second main surface side than the depth position of the bottom wall of the trench gate structure.

[0824] [D1] A SiC chip having a first main surface on one side, a second main surface and a side surface on the other side, A semiconductor region of a first conductivity type formed on the surface layer of the first main surface so as to be exposed from the first main surface and the side surface, At the peripheral edge of the first main surface, a pn connection region formed on the surface layer of the first main surface, A second conductivity type impurity region is formed in the surface layer of the semiconductor region at the periphery of the first main surface, and forms the semiconductor region and the pn connection region. It includes a plurality of modified lines formed on the side surface at intervals from the depth position of the pn connection region toward the second main surface, which are modified to have properties different from those of the SiC single crystal, The plurality of modification lines have different thicknesses with respect to the direction normal to the first main surface. The plurality of modification lines are formed on the side surface at intervals from the depth position at the bottom of the semiconductor region toward the second main surface, in a SiC semiconductor device.

[0825] [D2] The SiC semiconductor device according to D1, wherein the pn connection region is formed with a gap inward from the side surface to the first main surface.

[0826] [D3] An active region provided in the inner part of the first main surface, The outer region provided on the periphery of the first main surface further includes, The SiC semiconductor device according to D1 or D2, wherein the pn connection region is formed in the outer region.

[0827] [D4] The SiC semiconductor device according to D3, further comprising a diode structure formed on the first main surface of the active region.

[0828] [D5] The diode structure is A diode region formed on the surface layer of the first main surface of the active region, The SiC semiconductor device according to D4, comprising an electrode electrically connected to the diode region on the first main surface.

[0829] [D6] The SiC semiconductor device according to D3, further comprising a field-effect transistor structure formed on the first main surface of the active region.

[0830] [D7] T...

Claims

1. A SiC semiconductor layer comprising a hexagonal SiC single crystal, having a first main surface as a device surface, a second main surface opposite to the first main surface, a first side surface facing the a-plane of the SiC single crystal, and a second side surface facing the m-plane of the SiC single crystal, A first modified layer formed on the first side surface of the SiC semiconductor layer in a first proportion and modified to have different properties from the SiC single crystal, A SiC semiconductor device comprising: a second modified layer formed on the second side surface of the SiC semiconductor layer with a second occupancy ratio less than the first occupancy ratio, and modified to have properties different from the SiC single crystal.

2. A SiC semiconductor layer comprising a hexagonal SiC single crystal, having a first main surface as a device surface, a second main surface opposite to the first main surface, a first side surface facing the a-plane of the SiC single crystal, and a second side surface facing the m-plane of the SiC single crystal, A plurality of first modified layers are formed on the first side surface of the SiC semiconductor layer at intervals along the direction normal to the first main surface, and are modified to have properties different from those of the SiC single crystal, A SiC semiconductor device comprising: one or more second modifying layers formed on the second side surface of the SiC semiconductor layer in a number less than the number of the first modifying layers, and modified to have properties different from those of the SiC single crystal.

3. Multiple first modified layers are formed on the first side surface of the SiC semiconductor layer at intervals along the direction normal to the first main surface. The SiC semiconductor device according to claim 1, wherein one or more of the second modifying layers, less than the number of the first modifying layers, are formed on the second side surface of the SiC semiconductor layer at intervals along the direction normal to the first main surface.

4. The first modified layer has a first thickness with respect to the direction normal to the first main surface, The SiC semiconductor device according to any one of claims 1 to 3, wherein the second modified layer has a second thickness less than or equal to the first thickness with respect to the direction normal to the first main surface.

5. The SiC semiconductor device according to any one of claims 1 to 4, wherein the first modified layer is formed with a gap between the first main surface and the second main surface of the SiC semiconductor layer.

6. The SiC semiconductor device according to any one of claims 1 to 5, wherein the second modified layer is formed with a gap between the first main surface and the second main surface of the SiC semiconductor layer.

7. The SiC semiconductor device according to any one of claims 1 to 6, wherein the first modified layer is formed with a gap between the second main surface and the first main surface of the SiC semiconductor layer.

8. The SiC semiconductor device according to any one of claims 1 to 7, wherein the second modified layer is formed with a gap between the second main surface and the first main surface of the SiC semiconductor layer.

9. The first modified layer extends linearly, curvedly, or in a dashed line shape along the m-axis direction of the SiC single crystal. The SiC semiconductor device according to any one of claims 1 to 8, wherein the second modified layer extends linearly, curvedly, or in a dashed line shape along the a-axis direction of the SiC single crystal.

10. The SiC semiconductor device according to any one of claims 1 to 9, wherein the first main surface of the SiC semiconductor layer faces the c-plane of the SiC single crystal.

11. The SiC semiconductor device according to any one of claims 1 to 10, wherein the first main surface of the SiC semiconductor layer has an off-angle that is inclined at an angle of 0° or more and 10° or less with respect to the c-plane of the SiC single crystal.

12. The SiC semiconductor device according to claim 11, wherein the off-angle is an angle of 5° or less.

13. The SiC semiconductor device according to claim 11 or 12, wherein the off-angle is an angle greater than 0° and less than 4°.

14. The SiC semiconductor device according to any one of claims 1 to 13, wherein the SiC single crystal is a 2H (Hexagonal)-SiC single crystal, a 4H-SiC single crystal, or a 6H-SiC single crystal.

15. The SiC semiconductor device according to any one of claims 1 to 14, wherein the second main surface of the SiC semiconductor layer is a ground surface.

16. The first side surface of the SiC semiconductor layer is a cleavage plane, The SiC semiconductor device according to any one of claims 1 to 15, wherein the second side surface of the SiC semiconductor layer is a cleavage plane.

17. The SiC semiconductor device according to any one of claims 1 to 16, wherein the SiC semiconductor layer has a thickness of 40 μm or more and 200 μm or less.

18. The SiC semiconductor layer has a laminated structure comprising a SiC semiconductor substrate and a SiC epitaxial layer, wherein the first main surface is formed by the SiC epitaxial layer. The first modified layer is formed on the SiC semiconductor substrate, The SiC semiconductor device according to any one of claims 1 to 17, wherein the second modified layer is formed on the SiC semiconductor substrate.

19. The SiC semiconductor device according to claim 18, wherein the SiC epitaxial layer has a thickness less than or equal to the thickness of the SiC semiconductor substrate.

20. The SiC semiconductor substrate has a thickness of 40 μm or more and 150 μm or less. The SiC semiconductor device according to claim 18 or 19, wherein the SiC epitaxial layer has a thickness of 1 μm or more and 50 μm or less.

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