Semiconductor equipment

Abstract

The present invention provides a semiconductor device that can suppress common-mode noise superimposed on the signal transmitted between the first coil and the second coil. [Solution] The semiconductor device comprises a semiconductor substrate having an upper surface, and a plurality of wiring layers and a plurality of insulating layers alternately stacked on the upper surface of the semiconductor substrate. The plurality of insulating layers include a first insulating layer located between the semiconductor substrate and a first wiring layer, which is the lowest layer among the plurality of wiring layers in a cross-sectional view, and a second insulating layer located above the first wiring layer and one of the first wiring layers in a cross-sectional view. The first wiring layer includes a first coil, a first lead wire electrically connected to the outermost circumference of the first coil, and a second lead wire electrically connected to the innermost circumference of the first coil. In a cross-sectional view, the wiring layers located above the first wiring layer among the plurality of wiring layers have a second coil that overlaps the first coil.

Description

Technical Field

[0004] , , , ,

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[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] The semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2024-44675 (Patent Document 1) includes a semiconductor substrate, a first insulating layer formed on the semiconductor substrate, a first coil formed on the first insulating layer, a second insulating layer formed so as to cover the first coil, and a second coil formed on the second insulating layer so as to overlap the first coil in a plan view. In the semiconductor device disclosed in Patent Document 1, signal transmission is performed between the first coil and the second coil.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the semiconductor device disclosed in Patent Document 1, there is room for improvement in suppressing common-mode noise superimposed on the signal transmitted between the first coil and the second coil. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0006] The semiconductor device of this disclosure can suppress common-mode noise superimposed on the signal transmitted between the first coil and the second coil. [Brief explanation of the drawing]

[0007] [Figure 1] This is a block diagram of the semiconductor device DEV1 according to the first embodiment. [Figure 2] This is an explanatory diagram showing an example of signal transmission from semiconductor chip CHP1 to semiconductor chip CHP2. [Figure 3] This is a first plan view of the semiconductor chip CHP3 according to the first embodiment. [Figure 4] This is a second plan view of the semiconductor chip CHP3 according to the first embodiment. [Figure 5]This is a third plan view of the semiconductor chip CHP3 according to the first embodiment. [Figure 6] Figure 5 shows a cross-sectional view of semiconductor chip CHP3 at VI-VI. [Figure 7] This is a cross-sectional view of the semiconductor chip CHP3 at VII-VII in Figure 5. [Figure 8] This is a manufacturing process diagram for the semiconductor chip CHP3 according to the first embodiment. [Figure 9] This is a cross-sectional view illustrating the impurity diffusion layer formation process S2. [Figure 10] This is a cross-sectional view illustrating the interlayer insulating film formation process S3. [Figure 11] This is a cross-sectional view illustrating the wiring layer formation process S4. [Figure 12] This is a cross-sectional view illustrating the interlayer insulating film formation process S5. [Figure 13] This is a cross-sectional view illustrating the via plug formation process S6. [Figure 14] This is a cross-sectional view illustrating the wiring layer formation process S7. [Figure 15] This is a cross-sectional view of the semiconductor chip CHP4 related to the comparative example. [Figure 16] This is a cross-sectional view of the semiconductor chip CHP3 in the semiconductor device DEV2 according to the second embodiment. [Figure 17] This is a first plan view of the semiconductor chip CHP3 in the semiconductor device DEV3 according to the third embodiment. [Figure 18] This is a second plan view of the semiconductor chip CHP3 in the semiconductor device DEV3 according to the third embodiment. [Figure 19] This is a third plan view of the semiconductor chip CHP3 in the semiconductor device DEV3 according to the third embodiment. [Figure 20] This is a fourth plan view of the semiconductor chip CHP3 in the semiconductor device DEV3 according to the third embodiment. [Figure 21] This is a fifth plan view of the semiconductor chip CHP3 in the semiconductor device DEV3 according to the third embodiment. [Figure 22]It is a plan view of the semiconductor device CH3 in the semiconductor device DEV4 according to the fourth embodiment. [Figure 23A] It is a first cross-sectional view of the semiconductor chip CHP3 in the semiconductor device DEV4 according to the fourth embodiment taken along XXIIIA-XXIIIA in FIG. 22. [Figure 23B] It is a second cross-sectional view of the semiconductor chip CHP3 in the semiconductor device DEV4 according to the fourth embodiment taken along XXIIIB-XXIIIB in FIG. 22. [Figure 24A] It is a third cross-sectional view of the semiconductor chip CHP3 in the semiconductor device DEV4 according to the fourth embodiment taken along XXIVA-XXIVA in FIG. 22. [Figure 24B] It is a fourth cross-sectional view of the semiconductor chip CHP3 in the semiconductor device DEV4 according to the fourth embodiment taken along XXIVB-XXIVB in FIG. 22. [Figure 25] It is a plan view of the semiconductor chip CHP3 in the semiconductor device DEV1 according to Modification 1. [Figure 26] It is a cross-sectional view of the semiconductor chip CHP3 in the semiconductor device DEV1 according to Modification 1. [Figure 27] It is a plan view of the semiconductor chip CHP3 in the semiconductor device DEV1 according to Modification 2.

Embodiments for Carrying Out the Invention

[0008] Details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and redundant descriptions will not be repeated.

[0009] (First Embodiment) The semiconductor device DEV1 according to the first embodiment will be described.

[0010] <Schematic Configuration of Semiconductor Device DEV1> As shown in Figure 1, the semiconductor device DEV1 has a semiconductor chip CHP1 and a semiconductor chip CHP2. The semiconductor chip CHP1 has a receiving circuit RX and a control circuit CC1. The semiconductor chip CHP2 has a transmitting circuit TX and a control circuit CC2. The semiconductor device DEV1 further has a semiconductor chip CHP3. The semiconductor chip CHP3 has a coil CL1, a coil CL2 and a lead wire PL1.

[0011] Coil CL1 comprises coil CL11 and coil CL12. One end of coil CL11 is electrically connected to the receiving circuit RX, and the other end of coil CL11 is connected to one end of coil CL12. The other end of coil CL12 is electrically connected to the receiving circuit RX. Coil CL2 comprises coil CL21 and coil CL22. One end of coil CL21 is electrically connected to the transmitting circuit TX, and the other end of coil CL21 is connected to one end of coil CL22. The other end of coil CL22 is electrically connected to the transmitting circuit TX.

[0012] The lead wire PL1 is connected to the other end of coil CL11 and one end of coil CL12. The control circuit CC1 is electrically connected to the receiving circuit RX. The control circuit CC2 is electrically connected to the transmitting circuit TX.

[0013] As shown in Figure 2, the control circuit CC2 outputs signal SG1 to the transmitting circuit TX. Signal SG1 is a square wave. The transmitting circuit TX modulates signal SG1 into signal SG2 and sends signal SG2 to coil CL2. When signal SG2 flows through coil CL2, signal SG3, corresponding to signal SG2, flows through coil CL1 due to induced electromotive force. The receiving circuit RX amplifies signal SG3 and demodulates the amplified signal SG3 into signal SG4. The receiving circuit RX outputs signal SG4 to the control circuit CC1.

[0014] <Configuration of the CHP3 semiconductor chip> As shown in Figures 3, 4, 5, 6, and 7, the semiconductor chip CHP3 comprises a semiconductor substrate SUB, a plurality of wiring layers WL, and a plurality of interlayer insulating films ILD.

[0015] The semiconductor substrate SUB has an upper surface F1 and a lower surface F2 located on the opposite side of the upper surface F1. The semiconductor substrate SUB is formed of, for example, single-crystal silicon. The conductivity type of the semiconductor substrate SUB is, for example, p-type. The semiconductor substrate SUB may have an impurity diffusion layer IDL. The conductivity type of the impurity diffusion layer IDL is, for example, p-type. The impurity concentration in the impurity diffusion layer IDL is higher than the impurity concentration in the semiconductor substrate SUB outside of the impurity diffusion layer IDL. The impurity diffusion layer IDL is formed on the upper surface F1 within the semiconductor substrate SUB.

[0016] Each of the multiple wiring layers WL is formed of, for example, aluminum or an aluminum alloy. The multiple wiring layers WL are stacked on the upper surface F1. Each of the multiple interlayer insulating films ILD is formed of, for example, silicon oxide. Each of the multiple interlayer insulating films ILD is formed between the bottommost of the multiple wiring layers WL (wiring layer WL1) and the upper surface F1, and between two adjacent wiring layers WL. In other words, with the exception of the topmost of the multiple wiring layers WL, each of the multiple wiring layers WL is formed on one interlayer insulating film ILD and covered by another interlayer insulating film ILD. The bottommost interlayer insulating film ILD among the multiple interlayer insulating films ILD is referred to as interlayer insulating film ILD1. Interlayer insulating film ILD1 is located between the semiconductor substrate SUB and wiring layer WL1. Furthermore, the interlayer insulating film ILD located above wiring layer WL1 among the multiple interlayer insulating films ILD is referred to as interlayer insulating film ILD2.

[0017] Furthermore, one of the multiple wiring layers WL, for example, the one located at the bottom of the multiple wiring layers WL (wiring layer WL1), has a coil CL1, a lead wire PL1, a lead wire PL2, and a lead wire PL3. Coil CL1 has coils CL11 and CL12. Coils CL11 and CL12 are aligned in the first direction DR1 in a plan view.

[0018] Coil CL11 is wound in a spiral pattern when viewed from above. More specifically, coil CL11 is wound counterclockwise from one end located at the innermost circumference to the other end located at the outermost circumference when viewed from above. Coil CL12 is wound in a spiral pattern when viewed from above. More specifically, coil CL12 is wound clockwise from one end located at the outermost circumference to the other end located at the innermost circumference when viewed from above.

[0019] Each of the lead wires PL1, PL2, and PL3 extends in a second direction DR2 perpendicular to the first direction DR1 in a plan view. One end of lead wire PL1 is connected to the other end of coil CL11 and one end of coil CL12, and one end of lead wire PL2 is located next to coil CL11. One end of lead wire PL3 is located next to coil CL12. Lead wire PL1 is a center-tapped wire that supplies ground potential to the other end of coil CL11 and one end of coil CL12. Lead wires PL2 and PL3 are signal wires through which signals transmitted and received between semiconductor chip CHP1 and semiconductor chip CHP2 flow.

[0020] One of the multiple wiring layers WL, specifically wiring layer WL2 located on wiring layer WL1, has wiring WL2a and wiring WL2b. Each of wiring WL2a extends in the first direction DR1. In a plan view, one end and the other end of wiring WL2a coincide with one end of coil CL11 and one end of lead wiring PL2, respectively. In a plan view, one end and the other end of wiring WL2b coincide with the other end of coil CL12 and one end of lead wiring PL3, respectively.

[0021] The semiconductor chip CHP3 has via plugs VP1a, VP1b, VP1c, and VP1d. Via plugs VP1a through VP1d are formed within the interlayer insulating film ILD covering the wiring layer WL1. Each of via plugs VP1a through VP1d is made of, for example, tungsten. Via plug VP1a connects one end of wiring WL2a to one end of coil CL11, and via plug VP1b connects the other end of wiring WL2a to one end of lead wiring PL2. Via plug VP1c connects one end of wiring WL2b to the other end of coil CL12, and via plug VP1d connects the other end of wiring WL2b to one end of lead wiring PL3.

[0022] One of the multiple wiring layers WL, specifically wiring layer WL3, is located at the top and contains coil CL2, pads PD1, PD2, PD3, and a guard ring GR. Coil CL2 contains coils CL21 and CL22. Coils CL21 and CL22 are aligned in the first direction DR1. In a plan view, coil CL2 overlaps with coil CL1. More specifically, in a plan view, coil CL21 overlaps with coil CL11, and coil CL22 overlaps with coil CL12.

[0023] Coil CL21 is wound in a spiral pattern in a plan view. More specifically, coil CL21 is wound counterclockwise from one end located at the innermost circumference to the other end located at the outermost circumference in a plan view. Coil CL22 is wound in a spiral pattern in a plan view. More specifically, coil CL22 is wound clockwise from one end located at the outermost circumference to the other end located at the innermost circumference in a plan view. Pad PD1 is connected to one end of coil CL21. Pad PD2 is connected to the other end of coil CL22. Pad PD3 connects the other end of coil CL21 to one end of coil CL22. Guard ring GR surrounds coil CL2 (coils CL21 and CL22) in a plan view. The guard ring GR has openings OP1 and OP2. Coil CL2 is located inside opening OP1 in a plan view. The semiconductor chip CHP3 is electrically connected to the semiconductor chip CHP2 (receiving circuit RX) at pads PD1 and PD2.

[0024] Each of the multiple wiring layers WL has electrodes EL1, EL2, and EL3. Although not shown, a passivation film is formed on one of the uppermost interlayer insulating films ILD, covering the wiring layer WL3. The portions of electrodes EL1, EL2, and EL3 of the wiring layer WL3 exposed through the openings in the passivation film (see dotted lines in Figure 5) form pads PD4, PD5, and PD6, respectively. Pads PD4, PD5, and PD6 are located inside the opening OP2 in a plan view. Pads PD4, PD5, and PD6 are arranged such that in the first direction DR1, pad PD4 is positioned between pads PD5 and PD6. Ground potential is applied to pad PD4. The semiconductor chip CHP3 is electrically connected to the semiconductor chip CHP1 (transmitting circuit TX) at pads PD5 and PD6.

[0025] In a plan view, two adjacent electrodes EL1 of one set of wiring layers WL and two adjacent electrodes EL2 of the other set of wiring layers WL overlap each other. In the example shown in Figures 3 to 7, in a plan view, in the region located between pads PD4 and PD5, two adjacent electrodes EL1 of one set of wiring layers WL and two adjacent electrodes EL2 of the other set of wiring layers WL overlap each other. Also in this example, in a plan view, in the region located between pads PD4 and PD6, two adjacent electrodes EL1 of one set of wiring layers WL and two adjacent electrodes EL3 of the other set of wiring layers WL overlap each other. In the following, the region located between pads PD4 and PD5 and the region located between pads PD4 and PD6 in a plan view may be referred to as the first region.

[0026] Furthermore, the semiconductor chip CHP3 has multiple via plugs VP2a, multiple via plugs VP2b, and multiple via plugs VP2c. Via plugs VP2a, VP2b, and VP2c are formed inside each of the multiple interlayer insulating films ILD located other than the bottom layer. Via plugs VP2a, VP2b, and VP2c are made of, for example, tungsten. Two adjacent electrodes EL1 in multiple wiring layers WL are connected to each other by via plugs VP2a. Two adjacent electrodes EL2 in multiple wiring layers WL are connected to each other by via plugs VP2b. Two adjacent electrodes EL3 in multiple wiring layers WL are connected to each other by via plugs VP2c.

[0027] Electrode EL1 of wiring layer WL1 is connected to the other end of lead wiring PL1. Electrodes EL2 and EL3 of wiring layer WL1 are connected to the other end of lead wiring PL2 and the other end of lead wiring PL3, respectively.

[0028] <Manufacturing method for semiconductor chip CHP3> As shown in Figure 8, the method for manufacturing the semiconductor chip CHP3 includes a preparation step S1, an impurity diffusion layer formation step S2, an interlayer insulating film formation step S3, a wiring layer formation step S4, an interlayer insulating film formation step S5, a via plug formation step S6, and a wiring layer formation step S7.

[0029] In preparation step S1, the semiconductor substrate SUB is prepared. As shown in Figure 9, in impurity diffusion layer formation step S2, an impurity diffusion layer IDL is formed on the upper surface F1 of the semiconductor substrate SUB by, for example, ion implantation onto the upper surface F1. As shown in Figure 10, in interlayer insulating film formation step S3, one of the multiple interlayer insulating films ILDs, the lowest layer (interlayer insulating film ILD1), is formed on the upper surface F1 by, for example, CVD (Chemical Vapor Deposition).

[0030] As shown in Figure 11, in the wiring layer formation step S4, a wiring layer WL (wiring layer WL1) is formed on one of the multiple interlayer insulating films ILDs located at the bottom. In the wiring layer formation step S4, firstly, the constituent material of the wiring layer WL is deposited on one of the multiple interlayer insulating films ILDs located at the bottom, for example, by sputtering. Secondly, a resist pattern having openings is formed on the constituent material of the wiring layer WL. The resist pattern is formed by patterning the photoresist coated on the constituent material of the wiring layer WL using photolithography. Thirdly, the constituent material of the wiring layer WL is patterned by dry etching through the openings in the resist pattern, and the wiring layer WL is formed.

[0031] As shown in Figure 12, in the interlayer insulating film formation step S5, an interlayer insulating film ILD (interlayer insulating film ILD2) is formed so as to cover the wiring layer WL (wiring layer WL1). In the interlayer insulating film formation step S5, firstly, the constituent material of the interlayer insulating film ILD is formed so as to cover the wiring layer WL by, for example, CVD. Secondly, the upper surface of the constituent material of the interlayer insulating film ILD is flattened by, for example, CMP (Chemical Mechanical Polishing), and the interlayer insulating film ILD is formed.

[0032] As shown in Figure 13, in the via plug formation process S6, via plugs VP2a, VP2b, and VP2c are formed within the interlayer insulating film ILD. In the via plug formation process S6, a resist pattern having openings is formed on the interlayer insulating film ILD. Secondly, via holes are formed within the interlayer insulating film ILD by dry etching of the interlayer insulating film ILD through the openings in the resist pattern. Thirdly, constituent materials such as via plug VP2a are formed inside the via holes and on the interlayer insulating film ILD by, for example, CVD. Fourthly, constituent materials such as via plug VP1a formed outside the via holes are removed by, for example, CMP, forming via plugs VP2a, VP2b, and VP2c. Although not shown, via plugs VP1d are also formed from via plug VP1a in the same process.

[0033] As shown in Figure 14, in the wiring layer formation step S7, a wiring layer WL (wiring layer WL2) is formed on the interlayer insulating film ILD (interlayer insulating film ILD2) by the same process as in the wiring layer formation step S4. Subsequently, the interlayer insulating film formation step S5, the via plug formation step S6, and the wiring layer formation step S7 are repeated in sequence to form upper layers of interlayer insulating film ILD, via plugs VP2a, VP2b, VP2c, and wiring layer WL, resulting in the semiconductor chip CHP3 structure shown in Figures 3 to 7.

[0034] <Effects of Semiconductor Device DEV1> When a signal is transmitted between coil CL1 and coil CL2, common-mode noise may be superimposed on the signal. As shown in Figure 15, in the comparative example semiconductor chip CHP4, one electrode EL1 of two adjacent wiring layers WL and the other electrode EL2 (electrode EL3) of two adjacent wiring layers WL do not overlap each other in a plan view. Therefore, in the semiconductor chip CHP4, although a capacitor is formed between adjacent electrodes EL1 and EL2 (electrode EL3) within the same wiring layer WL, the capacitance of this capacitor is small and does not contribute much to the suppression of common-mode noise.

[0035] In contrast, as shown in Figure 7, in the semiconductor chip CHP3 according to the first embodiment, two adjacent electrodes EL1 and two adjacent electrodes EL2 (electrode EL3) of the multiple wiring layers WL overlap each other in a plan view. Therefore, in the semiconductor chip CHP3, the capacitance of the capacitor formed between electrodes EL1 and EL2 (electrode EL3) becomes large. Thus, the semiconductor device DEV1 having the semiconductor chip CHP3 can suppress the superposition of common-mode noise on the signal transmitted between coil CL1 and coil CL2. Furthermore, since the capacitor described above can be formed in the semiconductor chip CHP3 by utilizing dead space, it does not result in an increase in chip area.

[0036] (Second Embodiment) The semiconductor device DEV2 according to the second embodiment will be described. Here, we will mainly explain the differences from the semiconductor device DEV1, and will avoid repeating redundant explanations.

[0037] Figure 16 shows a cross-section of the semiconductor chip CHP3 of semiconductor device DEV2 at the position corresponding to VII-VII in Figure 5. As shown in Figure 16, in the semiconductor chip CHP3 of semiconductor device DEV2, one electrode EL1 of two adjacent wiring layers WL and the other two adjacent electrodes EL2 (electrode EL3) of the same wiring layer WL overlap with each other in a second region located inside the opening OP2 and outside the first region in a plan view, in addition to the first region. Therefore, in the semiconductor chip CHP3 of semiconductor device DEV2, the overlap between electrodes EL1 and EL2 (electrode EL3) in a plan view is larger compared to the semiconductor chip CHP3 of semiconductor device DEV1, and consequently the capacitance of the capacitor formed between electrodes EL1 and EL2 (electrode EL3) is larger, which further suppresses the superposition of common-mode noise on the signal transmitted between coil CL1 and coil CL2.

[0038] (Third embodiment) The semiconductor device DEV3 according to the third embodiment will be described. Here, the differences from the semiconductor device DEV2 will be mainly explained, and redundant explanations will not be repeated.

[0039] As shown in Figures 17, 18, 19, 20, and 21, in the semiconductor chip CHP3 of semiconductor device DEV3, two adjacent electrodes EL1 of one of the multiple wiring layers WL and the other two adjacent electrodes EL2 (electrode EL3) of the multiple wiring layers WL overlap each other in a region (third region) that overlaps with the guard ring GR in a plan view, in addition to the first and second regions.

[0040] As shown in Figure 17, the electrode EL1 of the wiring layer WL1 overlaps the guard ring GR in a plan view. The electrode EL1 of the wiring layer WL1 has openings OP3, OP4, OP5, slits SLT1 and SLT2 formed therein.

[0041] Opening OP3 overlaps opening OP1 in a plan view. Coil CL1 is located inside opening OP3 in a plan view. Openings OP4 and OP5 overlap pads PD5 and PD6, respectively, in a plan view. Electrodes EL2 and EL3 of wiring layer WL1 are located inside openings OP4 and OP5, respectively, in a plan view. Slits SLT1 and SLT2 extend in the second direction DR2. Lead wire PL1 extends from electrode EL2 through slit SLT1 to next to coil CL11, and lead wire PL2 extends from electrode EL3 through slit SLT2 to next to coil CL12.

[0042] As shown in Figure 18, electrodes EL2 and EL3 of wiring layer WL2 overlap the guard ring GR in a plan view. Electrodes EL2 and EL3 of wiring layer WL2 are separated from each other. Electrode EL1 of wiring layer WL2 overlaps the pad PD4 in a plan view. As shown in Figure 19, electrode EL1 of wiring layer WL3, i.e., pad PD4, is connected to the guard ring GR.

[0043] As shown in Figure 20, one electrode EL1 and one electrode EL2 located in an odd-numbered position from the bottom layer of the multiple wiring layers WL have the same shape as electrodes EL1 and EL2 of wiring layer WL1. However, slits SLT1 and SLT2 are not formed on one electrode EL1 located in an odd-numbered position from the bottom layer of the multiple wiring layers WL. As shown in Figure 21, one electrode EL1 and one electrode EL2 located in an even-numbered position from the bottom layer of the multiple wiring layers WL have the same shape as electrodes EL1 and EL2 of wiring layer WL2. In this way, in the semiconductor chip CHP3 of semiconductor device DEV3, one electrode EL1 of two adjacent wiring layers WL and the other two adjacent electrodes EL2 (electrode EL3) of the multiple wiring layers WL overlap each other in the first and second regions, as well as in the region that overlaps with the guard ring GR in a plan view (third region).

[0044] Thus, in the semiconductor chip CHP3 of semiconductor device DEV3, one electrode EL1 of two adjacent wiring layers WL and the other electrode EL2 (electrode EL3) of two adjacent wiring layers WL overlap not only in the first and second regions, but also in a third region that overlaps with the guard ring GR in a plan view. Therefore, in the semiconductor chip CHP3 of semiconductor device DEV3, compared with the semiconductor chip CHP3 of semiconductor device DEV2, the overlap between electrodes EL1 and EL2 (electrode EL3) in a plan view is larger, and consequently the capacitance of the capacitor formed between electrodes EL1 and EL2 (electrode EL3) is larger, which further suppresses the superposition of common-mode noise on the signal transmitted between coils CL1 and CL2. If the chip size is 1.2 mm x 1 mm, the spacing between pads PD4 and PD5 is 100 μm, the spacing between coil CL2 and aperture OP1 is 150 μm, and the distance between the outer edge of guard ring GR and the outer edge of semiconductor chip CHP3 is 80 μm, a capacitance of approximately 240 pF can be obtained.

[0045] (Fourth Embodiment) The semiconductor device DEV3 according to the fourth embodiment will be described. Here, we will mainly explain the differences from the semiconductor device DEV3, and will avoid repeating redundant explanations.

[0046] As shown in Figures 22, 23A, and 23B, in the semiconductor chip CHP3 of semiconductor device DEV4, each of the multiple wiring layers WL4 located in even-numbered positions from the top layer has a connecting electrode EL4. However, if wiring layer WL1 is located in an even-numbered position from the top layer, wiring layer WL1 does not have a connecting electrode EL4. In each of the multiple wiring layers WL4, an opening OP6 is formed in electrode EL2 (electrode EL3). In each of the multiple wiring layers WL4, the connecting electrode EL4 is located inside the opening OP6. In other words, the connecting electrode EL4 is electrically isolated from electrode EL2 (electrode EL3).

[0047] The connection electrodes EL4 of each of the multiple wiring layers WL4 overlap each other in a plan view. The semiconductor chip CHP3 of the semiconductor device DEV4 further has multiple via plugs VP3a. In two adjacent wiring layers WL, the connection electrode EL4 is connected to electrode EL1 by via plugs VP3a.

[0048] As shown in Figures 22, 24A, and 24B, in the semiconductor chip CHP3 of semiconductor device DEV4, each of the multiple wiring layers WL5 located in odd-numbered positions from the top layer has a connecting electrode EL5. However, wiring layer WL3 does not have a connecting electrode EL5. Also, if wiring layer WL1 is located in an odd-numbered position from the top layer, wiring layer WL1 does not have a connecting electrode EL5. In each of the multiple wiring layers WL5, an opening OP7 is formed in electrode EL1. In each of the multiple wiring layers WL5, the connecting electrode EL5 is located inside the opening OP7. In other words, the connecting electrode EL5 is electrically isolated from electrode EL1.

[0049] The connection electrodes EL5 of each of the multiple wiring layers WL5 overlap each other in a plan view. The semiconductor chip CHP3 of the semiconductor device DEV4 further has multiple via plugs VP3b. In two adjacent wiring layers WL, the connection electrode EL5 is connected to electrode EL2 (electrode EL3) by via plugs VP3b.

[0050] In the semiconductor chip CHP3 of semiconductor device DEV4, electrodes EL1 (electrodes EL2 and EL3) that are subjected to the same potential are connected by connecting electrode EL4 and via plug VP3a (connecting electrode EL5 and via plug VP3b). Therefore, the semiconductor chip CHP3 of semiconductor device DEV4 increases chip strength and consequently suppresses warping. Note that in Figure 22, only some of the multiple via plugs VP3a and some of the via plugs VP3b are shown by dotted lines.

[0051] (Variation 1) As shown in Figures 25 and 26, the semiconductor chip CHP3 of semiconductor device DEV1 may further have a seal ring SR. The semiconductor chip CHP3 of semiconductor devices DEV2 to DEV4 may similarly have a seal ring SR. The seal ring SR is formed on the outer edge of the semiconductor substrate SUB in a plan view. The guard ring GR is located inside the seal ring SR in a plan view. The seal ring SR has a plurality of seal ring wirings SWL, a plurality of via plugs VP4, and contact plugs CP.

[0052] Each of the multiple wiring layers WL has a sealing ring wiring SWL. Furthermore, the semiconductor chip CHP3 of semiconductor devices DEV1 to DEV3 has a contact plug CP and multiple via plugs VP4. In a plan view, the sealing ring wiring SWLs of each of the multiple wiring layers WL overlap each other. The via plugs VP4 are formed inside each of the multiple interlayer insulating films ILD. However, a contact plug CP is formed inside one of the bottommost interlayer insulating films ILD. The via plugs VP4 connect two adjacent sealing ring wirings SWLs of the multiple wiring layers WL. The contact plugs CP connect the sealing ring wiring SWL of wiring layer WL1 to the semiconductor substrate SUB.

[0053] (Modification 2) As shown in Figure 27, in the semiconductor chip CHP3 of semiconductor device DEV1, the wiring layer WL2 may further have coil wiring CWL. In plan view, coil wiring CWL overlaps coil CL1. Although not shown, coil wiring CWL is connected to coil CL1 by via plugs. This reduces the electrical resistance of coil CL1.

[0054] Although the present invention has been specifically described above based on embodiments, it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence. [Explanation of Symbols]

[0055] CC1, CC2 control circuits, CHP1 semiconductor chip, CHP2 semiconductor chip, CHP3 semiconductor chip, CHP4 semiconductor chip, CL1, CL11, CL12 coils, CL2, CL21, CL22 coils, CP contact plug, CWL coil wiring, DEV1, DEV2, DEV3, DEV4 semiconductor devices, DR1 first direction, DR2 second direction, EL1, EL2, EL3 electrodes, EL4, EL5 connecting electrodes, F1 top surface, F2 bottom surface, GR guard ring, IDL impurity diffusion layer, ILD interlayer insulating film, OP1, OP2, OP3, OP4, OP5, OP6, OP7 openings, PD1, PD2, PD3, PD4, PD5, PD6 pads, PL1, PL2, PL3 lead-out wiring, RX receiving circuit, S1 preparation process, S2 impurity diffusion layer formation process, S3, S5 interlayer insulating film formation process, S4, S7 Wiring layer formation process, S6 via plug formation process, SG1, SG2, SG3, SG4 signals, SLT1 slit, SLT2 slit, SR seal ring, SUB semiconductor substrate, SWL seal ring wiring, TX transmit circuit, VP1a, VP1b, VP1c, VP1d, VP2a, VP2b, VP2c, VP3a, VP3b, VP4 via plugs, WL, WL1, WL2, WL3, WL4, WL5 wiring layers, WL2a, WL2b wiring.

Claims

1. A semiconductor substrate having an upper surface, The semiconductor substrate comprises a plurality of wiring layers and a plurality of insulating layers alternately stacked on the upper surface of the semiconductor substrate, The plurality of insulating layers are In a cross-sectional view, a first insulating layer is located between the first wiring layer, which is the lowest of the plurality of wiring layers, and the semiconductor substrate. In a cross-sectional view, the first wiring layer and a second insulating layer located above the first wiring layer among the plurality of wiring layers, It has, The first wiring layer is, The first coil and A first lead wire electrically connected to the outermost part of the first coil, A second lead wire electrically connected to the innermost circumference of the first coil, It has, In a cross-sectional view, the wiring layer located above the first wiring layer among the plurality of wiring layers has a second coil that overlaps the first coil. Each of the plurality of wiring layers has a first electrode electrically connected to the first lead wire and a second electrode electrically connected to the second lead wire. In a cross-sectional view, the first electrode and the second electrode, which are located in the second wiring layer that is the uppermost of the plurality of wiring layers, form the first pad and the second pad, respectively. A semiconductor device in which the first electrode provided on one of two adjacent wiring layers and the second electrode provided on the other of the two adjacent wiring layers overlap each other.

2. The semiconductor device according to claim 1, wherein the first electrode provided on one of the two adjacent wiring layers and the second electrode provided on the other of the two adjacent wiring layers overlap each other in a first region located between the first pad and the second pad.

3. In a cross-sectional view, the second wiring layer, which is located at the uppermost of the plurality of wiring layers, further has a guard ring that surrounds the second coil in a plan view. The guard ring has an opening, The semiconductor device according to claim 2, wherein the first pad and the second pad are located inside the opening in a plan view.

4. In a cross-sectional view, the second wiring layer, which is located at the uppermost of the plurality of wiring layers, further has a guard ring that surrounds the second coil in a plan view. The guard ring has an opening, The first pad and the second pad are located inside the opening in a plan view. The semiconductor device according to claim 1, wherein the first electrode provided on one of the two adjacent wiring layers and the second electrode provided on the other of the two adjacent wiring layers overlap each other in a first region located between the first pad and the second pad and a second region located inside the opening and outside the first region.

5. In a cross-sectional view, the second wiring layer, which is located at the uppermost of the plurality of wiring layers, further has a guard ring that surrounds the second coil in a plan view. The guard ring has an opening, The semiconductor device according to claim 1, wherein the first electrode provided on one of the two adjacent wiring layers and the second electrode provided on the other of the two adjacent wiring layers overlap each other in a first region located between the first pad and the second pad, a second region located inside the opening and outside the first region, and a third region overlapping the guard ring.

6. It also has multiple first via plugs, Each of the multiple first wiring layers located in an even-numbered position from the top layer among the multiple wiring layers has a first connecting electrode. The semiconductor device according to claim 5, wherein in two adjacent of the plurality of wiring layers, one of the plurality of first via plugs connects the first connecting electrode and the first electrode.

7. The semiconductor substrate is further provided with a sealing ring located on the outer edge of the semiconductor substrate in a plan view. In a cross-sectional view, the second wiring layer, which is located at the uppermost of the plurality of wiring layers, further has a guard ring that surrounds the second coil in a plan view. The semiconductor device according to claim 1, wherein the guard ring is located inside the seal ring in a plan view.

8. The semiconductor device according to claim 1, wherein the second coil is provided on the second wiring layer, which is located in the uppermost layer of the plurality of wiring layers in a cross-sectional view.

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