Semiconductor memory device and its control method

Abstract

It provides highly reliable memory. [Solution] The first wire is connected to cells arranged in the first direction. The second wire is connected to cells arranged in the second direction. The third wire is provided on the second wire arranged in the third direction. The first drive line is common to the first wire arranged in the third direction. The first transistor is connected between the first wire and the first drive line. The fourth wire is connected to the gate of the first transistor arranged in the second direction. The second drive line is provided on the first wire arranged in the second direction. The second transistor is connected between the first wire and the second drive line. The fifth wire is commonly connected to the gate of the second transistor arranged in the second direction. The driver circuit drives the voltages of the fourth and fifth wires. The driver applies a first voltage to the fifth wire corresponding to the unselected first wire in the selected bank, and applies a second voltage to the fifth wire in the unselected bank having an absolute value smaller than the absolute value of the first voltage.

Description

Technical Field

[0004] , , , , , , , , , , , ,

[0005] ,

[0001] This embodiment relates to a semiconductor memory device and a control method thereof.

Background Art

[0002] Semiconductor memory devices such as DRAM (Dynamic Random Access Memory) in which memory cells are three-dimensionally arrayed have been developed. In a three-dimensional memory portion, switches are provided at both ends of a word line, and the voltage of the word line may be selected or deselected by controlling these switches.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

[0006] [Figure 1A] A block diagram showing an example configuration of a semiconductor memory device according to the first embodiment. [Figure 1B] A block diagram showing an example configuration of one bank. [Figure 1C] A block diagram showing an example configuration of a single cell array. [Figure 2] A diagram showing an example configuration of a single cell array. [Figure 3] A circuit diagram showing an example configuration of a single memory cell. [Figure 4]A block diagram showing an example configuration of a row decoder, main word line driver, and bank according to the first embodiment. [Figure 5] A timing diagram showing an example of operation of a semiconductor memory device according to the first embodiment. [Figure 6] A block diagram showing an example configuration of a semiconductor memory device according to the second embodiment. [Figure 7] A timing diagram showing an example of operation of a semiconductor memory device according to the second embodiment. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will be described below with reference to the drawings. These embodiments are not limiting to the present invention. The drawings are schematic or conceptual. The same elements are denoted by the same reference numerals in the specification and the drawings.

[0008] (First Embodiment) Figure 1A is a block diagram showing an example configuration of the semiconductor memory device 1 according to the first embodiment. The semiconductor memory device 1 of this embodiment is a DRAM equipped with a memory cell array MCA in which memory cells MC are arranged in two dimensions (planar) or three dimensions (three-dimensionally). In this embodiment, a three-dimensional memory cell array MCA will be described. The memory cells MC are used as memory cells that store 1-bit data or multi-bit data.

[0009] The memory cell array (MCA) is divided into multiple banks BK0 to BK7. Banks BK0 to BK7 are units of multiple memory cells (MCs) that are selectively accessed during data read or write operations. The number of banks BKs contained within the memory cell array (MCA) is not limited.

[0010] The peripheral circuit PRI is a logic circuit that controls access to banks BK0 to BK7 and is composed of CMOS (Complementary Metal Oxide Semiconductor) circuits. The memory cell array MCA and the peripheral circuit PRI can be configured as a single semiconductor chip. Alternatively, the array chip having the memory cell array MCA and the CMOS chip having the peripheral circuit PRI may be manufactured separately and then bonded together to form a single chip.

[0011] Figure 1B is a block diagram showing an example configuration of a single bank (BK). A single bank (BK) is divided into multiple cell arrays (ARRs). The number of cell arrays (ARRs) contained within a bank (BK) is not limited.

[0012] Figure 1C is a block diagram showing an example configuration of a single cell array ARR. A single cell array ARR is divided into multiple subarrays (SUBARRs). The number of subarrays (SUBARRs) contained within a cell array ARR is not limited.

[0013] Figure 2 shows an example configuration of a cell array ARR within a single bank BK. According to this embodiment, multiple memory cells MC are arranged three-dimensionally in the X, Y, and Z directions, for example, to form a three-dimensional memory cell array MCA (bank BK, cell array ARR). Note that the X, Y, and Z directions are directions that intersect each other, for example, orthogonal coordinate axes.

[0014] The semiconductor memory device 1 according to this embodiment includes a memory cell array MCA, a plurality of word lines WL, a plurality of bit lines VBL, a plurality of main word lines MWL, bMWL, a plurality of global bit lines GBL, a bit selection line VBLSEL, word drive lines WDRV, VUX, a row decoder RD, a main word line driver DRV, and a sense amplifier circuit SA.

[0015] A plurality of word lines WL as the first wiring extend in the X direction in the bank BK or the cell array ARR and are commonly connected to a plurality of memory cells MC arranged in the X direction. In the memory cell array MCA, the plurality of word lines WL are arranged in the Z and Y directions. One end of each of the plurality of word lines WL is connected to a plurality of word drive lines WDRV via a plurality of transistors TRw. The other end of each of the plurality of word lines WL is connected to a plurality of word drive lines VUX via a plurality of transistors bTRw.

[0016] A plurality of bit lines VBL as the second wiring extend in the Z direction in the bank BK or the cell array ARR and are commonly connected to a plurality of memory cells MC arranged in the Z direction. In the bank BK or the cell array ARR, the plurality of bit lines VBL are arranged in the X and Y directions. One end of each of the plurality of bit lines VBL is connected to one of a plurality of global bit lines GBL via a plurality of transistors TRb.

[0017] A plurality of global bit lines GBL as the third wiring extend in the Y direction and are commonly provided for a plurality of bit lines VBL arranged in the Y direction.

[0018] A plurality of transistors TRb are respectively connected between a plurality of bit lines VBL and a plurality of global bit lines GBL. One of the source or drain of the transistor TRb is connected to the bit line VBL, and the other is connected to the global bit line GBL. The gate of the transistor TRb is connected to the bit selection line VBLSEL.

[0019] The bit selection line VBLSEL is commonly connected to the gates of a plurality of transistors TRb arranged in the X direction. The bit selection line VBLSEL can connect a plurality of bit lines VBL arranged in the X direction to the corresponding global bit lines GBL. Thereby, the bit line VBL can be connected to the sense amplifier circuit SA via the corresponding global bit line GBL.

[0020] Multiple word drive lines WDRV, acting as the first drive lines, extend in the Y direction and are provided in common for multiple word lines WL arranged in the Y direction. The word drive lines WDRV transmit a voltage (e.g., +1.5V) applied to the selected word line WL of the selected bank BK (first bank) that is selectively accessed during data read or write operations, or a voltage (e.g., -1.0V) applied to the unselected word line WL of the selected bank BK.

[0021] One of the sources and drains of multiple transistors TRw, which act as the first transistor, are connected to multiple word lines WL, respectively. The other of the multiple transistors TRw is connected to multiple word drive lines WDRV, respectively.

[0022] Multiple main word lines MWL, acting as the fourth wiring, are commonly connected to the gates of multiple transistors TRw arranged in the Z direction. These multiple main word lines MWL are connected to the row decoder RD and the main word line driver DRV. The voltages of the multiple main word lines MWL are selectively driven by the row decoder RD and the main word line driver DRV. The voltages of the word drive lines WDRV and VUX, which transmit voltage to the word lines WL, are driven by other word line drivers (not shown).

[0023] Multiple word drive lines VUX, acting as second drive lines, extend in the Z direction and are provided in common for multiple word lines WL arranged in the Z direction. The word drive lines VUX transmit a voltage (e.g., -1.0V) applied to the unselected word lines WL of the selected bank BK and unselected bank BK during data read or write operations.

[0024] One of the sources and drains of the multiple transistors bTRw acting as the second transistor is connected to multiple word lines WL, respectively. The other of the multiple transistors bTRw is connected to multiple word drive lines VUX, respectively.

[0025] Multiple main word lines bMWL, acting as a fifth wiring, are commonly connected to the gates of multiple transistors bTRw arranged in the Z direction. These multiple main word lines bMWL are connected to the row decoder RD and the main word line driver DRV. The voltages of the multiple main word lines bMWL are selectively driven by the row decoder RD and the main word line driver DRV.

[0026] The row decoder RD is connected to multiple main word lines MWL and bMWL, and selectively controls the voltage of the main word lines MWL and bMWL according to the bank address and word line address. The main word line driver DRV selectively applies voltage to the main word lines MWL and bMWL from the row decoder RD according to the bank address and word line address. For example, the main word line driver DRV applies a first voltage (e.g., 2V) to the main word line MWL corresponding to the selected word line WL selected by the row decoder RD, turning the transistor TRw into a conducting state (on). The main word line driver DRV applies a third voltage (e.g., -1.5V) to the main word line MWL corresponding to the unselected word line WL, turning the transistor TRw into a non-conducting state (off).

[0027] Furthermore, the main word line driver DRV applies a third voltage (e.g., -1.5V) to the main word line bMWL corresponding to the selected word line WL, turning off the transistor bTRw. The main word line driver DRV applies a first voltage (e.g., 2V) to the main word line bMWL corresponding to the unselected word line WL in the selected bank BK, turning the transistor bTRw into a conduction state (on). In addition, the main word line driver DRV according to this embodiment applies a second voltage (e.g., 0.5V) to the main word line bMWL corresponding to all word lines WL (unselected word lines) in the unselected bank BK (second bank).

[0028] The absolute value of the second voltage applied to the main word line bMWL in the unselected bank BK is smaller than the absolute value of the first voltage applied to the main word line bMWL corresponding to the unselected word line WL in the selected bank BK. When there are many banks BK in the memory cell array MCA, the period during which a bank BK is idle as an unselected bank is considerably longer than the period during which it is accessed as a selected bank BK in read or write operations. Therefore, by making the absolute value of the second voltage applied to the main word line bMWL in the unselected bank BK smaller than the absolute value of the first voltage, degradation of the transistor bTRw due to PBTI (Positive Bias Temperature Instability) or NBTI (Negative Bias Temperature Instability) can be suppressed.

[0029] For example, suppose we set the voltage of the main word line bMWL in the unselected bank BK to be equal to the first voltage (e.g., 2V) applied to the main word line bMWL corresponding to the unselected word line WL in the selected bank BK. In this case, the transistor bTRw in the standby unselected bank BK will remain on for a long period of time at a relatively high first voltage. Therefore, transistor bTRw is prone to degradation by PBTI.

[0030] In contrast, according to this embodiment, the transistor bTRw in the unselected bank BK in standby mode remains on at a second voltage (e.g., 0.5V) having an absolute value smaller than the absolute value of the first voltage. Therefore, the transistor bTRw is less likely to degrade. The second voltage may be less than 0.5V.

[0031] Note that transistors TRw, bTRw, and TRb can be either n-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) or p-type MOSFETs. Here, we will explain assuming that transistors TRw, bTRw, and TRb are n-type MOSFETs.

[0032] In a read operation, the sense amplifier circuit SA detects data stored in the selected memory cell MC connected to the selected word line WL via the bit line VBL. Alternatively, in a write operation, the sense amplifier circuit SA writes data to the selected memory cell MC connected to the selected word line WL by applying a write voltage.

[0033] Figure 3 is a circuit diagram showing an example configuration of a single memory cell MC. The memory cell MC has one cell transistor CT and one cell capacitor CC.

[0034] One of the sources and drains of the cell transistor CT is connected to one of several bit lines VBL, and the other is connected to one end of the cell capacitor CC. The gate of the cell transistor CT is connected to one of several word lines WL.

[0035] The cell capacitor CC is connected between the cell transistor CT and a reference voltage source (e.g., ground).

[0036] Multiple memory cells (MCs) each have the same configuration.

[0037] A memory cell (MC) can store logical data by accumulating charge in a cell capacitor (CC) via a cell transistor (CT), or by releasing charge from the cell capacitor (CC).

[0038] Figure 4 is a block diagram showing an example configuration of the row decoder RD, main word line driver DRV, and bank BK according to the first embodiment.

[0039] Each bank BK includes multiple cell arrays ARR, and each cell array ARR includes multiple subarrays SUBARR. Each subarray SUBARR consists of multiple memory cells MC corresponding to a pair of main word lines MWL and bMWL. For example, a subarray SUBARR consists of multiple memory cells MC arranged two-dimensionally in the XZ plane of Figure 2. Note that bank BK, cell array ARR, and subarray SUBARR are convenient classification concepts for memory cell arrays MCA, and their units can be changed arbitrarily.

[0040] The row decoder RD comprises a bank address decoder BAD and a word line address decoder WAD. A row decoder RD is provided for each memory cell array MCA. The bank address decoder BAD decodes the bank address BA, which selects the bank BK within the memory cell array MCA that will be used for read or write operations. The word line address decoder WAD decodes the word line address WA, which selects the word line WL within the selected bank BK that will be used for read or write operations.

[0041] The main word line driver DRV connects one of the power terminals PS1 to PS3 to the main word line MWL or bMWL based on the decoded bank address BA and word line address WA. This allows the main word line driver DRV to apply the voltage from one of the power terminals PS1 to PS3 to the main word line MWL or bMWL.

[0042] The power terminal PS1 is a power terminal that supplies a high-level voltage (e.g., 2V) as the first voltage, which is the voltage that turns on transistors TRw and bTRw in Figure 2. In other words, the power terminal PS1 supplies the first voltage to the main word lines MWL and bMWL, which electrically connects the word drive line WDRV or VUX to the word line WL.

[0043] Power terminal PS2 is a power terminal that supplies an intermediate level voltage (e.g., 0.5V) as a second voltage. The second voltage at power terminal PS2 is lower than the first voltage at power terminal PS1 and higher than the third voltage at power terminal PS3. The second voltage is the voltage that turns on transistor bTRw in Figure 2, but it is lower than the first voltage. Therefore, transistor bTRw, which receives the second voltage at its gate, turns on in a relatively high resistance state. That is, the second voltage electrically connects the word drive line VUX to the word line WL, but it increases the resistance of transistor bTRw between the word drive line VUX and the word line WL compared to when the first voltage is supplied.

[0044] The power terminal PS3 is a power terminal that supplies a low-level voltage (e.g., -1.5V) as a third voltage, which is the voltage that turns off transistors TRw and bTRw in Figure 2. In other words, the power terminal PS3 supplies a third voltage to the main word lines MWL and bMWL that electrically disconnects the word drive lines WDRV and VUX from the word line WL.

[0045] The main word line driver DRV includes switching circuits SWC1 to SWC3.

[0046] Switching circuit SWC1 is connected between the bank address decoder BAD and switching circuit SWC3. Based on the bank address BA, which identifies the selected bank BK to be read or written, switching circuit SWC1 connects either power terminal PS1 or PS2 to the main word line bMWL via switching circuit SWC3. Since switching circuit SWC1 operates based on the bank address BA, it is provided to correspond to each of the multiple banks BK.

[0047] The switching circuit SWC1 comprises a transistor Tp1 as a first switching element, a transistor Tp2 as a second switching element, an inverter circuit IN1, and a power line PSL1.

[0048] One of the sources and drains of transistor Tp1 is connected to the power supply terminal PS1, and the other is connected to the power supply line PSL1. The gate of transistor Tp1 receives a first signal corresponding to the bank address BA. The first signal is, for example, a signal VD corresponding to bank address BA, inverted by the inverter circuit IN1. Transistor Tp1 is, for example, a p-type MOSFET. Transistor Tp1 turns on, for example when bank address BA is rising to a high level, and connects the power supply terminal PS1 to the power supply line PSL1, supplying a first voltage (for example, 2V) to the power supply line PSL1.

[0049] One of the sources and drains of transistor Tp2 is connected to the power terminal PS2, and the other is connected to the power line PSL1. The gate of transistor Tp2 receives a second signal, which is the inverse logic of the first signal, depending on the bank address BA. The second signal is, for example, the non-inverted signal VD corresponding to bank address BA. Transistor Tp2 is, for example, a p-type MOSFET. Transistor Tp2 turns on, for example when bank address BA is falling to a low level, and supplies a second voltage (for example, 0.5V) to the power line PSL1 by connecting the power terminal PS2 to the power line PSL1.

[0050] The power line PSL1 is provided in common for multiple subarrays SUBARR of a single bank BK and is connected to the main word line bMWL via the switching circuit SWC3. Therefore, when the switching circuit SWC3 connects the power line PSL1 to the main word line bMWL, the other end of transistor Tp1 or Tp2 is electrically connected to the main word line bMWL. In this case, a first or second voltage from the power terminal PS1 or PS2 can be applied to the main word line bMWL.

[0051] For example, in the selected bank BK, transistor Tp1 connects its power supply terminal PS1 to the main word line bMWL corresponding to the unselected word line WL. This allows a first voltage (e.g., 2V) from the power supply terminal PS1 to be applied to the main word line bMWL of the unselected subarray SUBARR. In the unselected bank BK, transistor Tp2 connects its power supply terminal PS2 to the main word line bMWL in the unselected bank BK. This allows a second voltage (e.g., 0.5V) from the power supply terminal PS2 to be applied to the main word line bMWL of the unselected bank BK.

[0052] Thus, the switching circuit SWC1 can switch the power supply terminals to supply either a first voltage from power supply terminal PS1 or a second voltage from power supply terminal PS2 to the main word line bMWL for each bank BK based on the bank address BA.

[0053] Switching circuit SWC2 is connected between the word line address decoder WAD and switching circuit SWC3. Based on the word line address WA, which identifies the selected word line WL to be read or written, switching circuit SWC2 connects either power terminal PS1 or PS3 to each of the main word lines MWL. Also, based on the word line address WA, switching circuit SWC2 connects either power terminal PS1 or PS3 to each of the main word lines bMWL via switching circuit SWC3. Since switching circuit SWC2 operates based on the word line address WA, it is provided to correspond to each of the multiple main word lines MWL.

[0054] The switching circuit SWC2 includes inverter circuits IN2 and IN3. Inverter circuit IN2 is connected to power terminals PS1 and PS3 and outputs to either power terminal PS1 or PS3 based on the word line address WA. Inverter circuit IN3 is also connected to power terminals PS1 and PS3 and outputs to either power terminal PS1 or PS3 based on the output of inverter circuit IN2. Since inverter circuits IN2 and IN3 are connected in series, the switching circuit SWC2 supplies a voltage to the main word line MWL or the switching circuit SWC3 according to the logic of word line address WA.

[0055] For example, in the selection bank BK, the switching circuit SWC2 connects power terminal PS1 to the main word line MWL corresponding to the selected word line WL according to the word line address WA, and applies a first voltage (e.g., 2V). Also, in the selection bank, the switching circuit SWC2 connects power terminal PS3 to the main word line MWL corresponding to the unselected word line WL according to the word line address WA, and applies a third voltage (e.g., -1.5V).

[0056] Similarly, in the selection bank BK, the switching circuit SWC2 connects its power terminal PS3 to the switching circuit SWC3 corresponding to the selected word line WL. A third voltage (e.g., -1.5V) is applied to the main word line bMWL corresponding to the selected word line WL. Also, in the selection bank, the switching circuit SWC2 connects its power terminal PS1 to the switching circuit SWC3 corresponding to the unselected word line WL. A first voltage (e.g., 2V) is applied to the main word line bMWL corresponding to the unselected word line WL.

[0057] Thus, the switching circuit SWC2 can switch, based on the word line address WA, to supply either a first voltage from the power terminal PS1 or a third voltage from the power terminal PS3 to the main word line MWL and the switching circuit SWC3 for each word line WL. The switching circuit SWC2 is provided for each subarray SUBARR within a single cell array ARR, but it is common to multiple subarrays SUBARR located in different cell array ARRs that are adjacent laterally in Figure 4.

[0058] The switching circuit SWC2 includes two inverter circuits IN2 and IN3 connected in series, but it may also be configured by connecting four or more even-numbered inverters in series.

[0059] Switching circuit SWC3 is connected between switching circuit SWC2 and the main word line bMWL. Based on the output of switching circuit SWC2, switching circuit SWC3 connects either power terminal PS1 or PS2 from switching circuit SWC1 and power terminal PS3 to each of the multiple main word lines bMWL. Switching circuit SWC3 consists of inverter circuit IN4. Switching circuit SWC3 may be configured by connecting three or more odd-numbered inverter circuits in series.

[0060] Since the output of the switching circuit SWC2 is driven based on the word line address WA, the switching circuit SWC3 consequently applies either power terminal PS1 or PS2 and power terminal PS3 to the main word line bMWL based on the word line address WA. Therefore, the input of the switching circuit SWC3 may be connected to the output of the word line address decoder WAD, and a signal corresponding to the word line address WA may be input. Since the switching circuit SWC3 operates based on the word line address WA, it is provided for each of the multiple main word lines bMWL. Since a pair of main word lines MWL and bMWL is provided for each sub-array SUBARR, it can be said that the switching circuit SWC3 is provided for each sub-array SUBARR.

[0061] For example, if the output of switching circuit SWC2 is the first voltage at power terminal PS1, then word line address WA specifies the selected word line WL. Therefore, switching circuit SWC3 connects power terminal PS3 to the main word line bMWL corresponding to the selected word line WL and applies a third voltage (e.g., -1.5V). This disconnects the word drive line VUX from the word line WL of the selected subarray SUBARR.

[0062] When the output of switching circuit SWC2 is the third voltage of power terminal PS3, the word line address WA indicates the unselected word line WL. Therefore, switching circuit SWC3 connects power line PSL1 to the main word line bMWL corresponding to the unselected word line WL and applies the first or second voltage (e.g., 2V or 0.5V) of power terminal PS1 or PS2 to the main word line bMWL. In this case, in selection bank BK, which includes the selected word line WL, power line PSL1 transmits the first voltage of power terminal PS1. Therefore, switching circuit SWC3 applies the first voltage of power terminal PS1 to the main word line bMWL. Note that selection bank BK includes the selected main word lines MWL and bMWL connected to the selected sub-arrays SUBARR (multiple sub-arrays SUBARR adjacent laterally in Figure 4 and each contained in a different cell array ARR), and other unselected main word lines MWL and bMWL connected to the sub-arrays SUBARR.

[0063] In the selection bank BK, the selected word line WL may be adjacent to a non-selected word line WL. In this case, the voltage of the non-selected word line WL may be affected by the selected word line WL due to capacitive coupling between adjacent word lines WL (coupling noise). In this embodiment, the main word line bMWL applies the first voltage from the power supply terminal PS1 to the transistor bTRw, turning the transistor bTRw into a low-resistance ON state. As a result, the non-selected word line WL is connected to the word drive line VUX with low resistance. Therefore, the voltage of the non-selected word line WL is maintained at the voltage of the word drive line VUX (e.g., -1V), and the coupling noise can be suppressed.

[0064] Furthermore, it is preferable that the non-selected word line WL, which shares the selected word line WL and the word drive line WDRV, is connected to the word drive line VUX with low resistance so that the voltage does not change due to leakage current from the word drive line WDRV.

[0065] On the other hand, in the non-selected bank BK, which does not include the selected word line WL, the power line PSL1 transmits the second voltage of the power terminal PS2. Therefore, the switching circuit SWC3 applies the second voltage of the power terminal PS2 to the main word line bMWL. As a result, in the non-selected bank BK in standby mode, the switching circuit SWC3 applies the second voltage of the power terminal PS2 to the main word line bMWL. Consequently, the degradation of transistor bTRw can be suppressed.

[0066] In this case, although the word drive line VUX and the word line WL are electrically connected, they are in a relatively high-resistance state. However, in the non-selection bank BK, all word lines WL are non-selection word lines. Therefore, there is no need to consider coupling noise, so it is not a problem even if the resistance between the word drive line VUX and the word line WL is somewhat high.

[0067] Next, the operation of the semiconductor memory device according to this embodiment will be described.

[0068] Figure 5 is a timing diagram showing an example of operation of a semiconductor memory device according to the first embodiment. MWL(WLsel) indicates the voltage of the main word line MWL corresponding to the selected word line WL. MWL(WLnonsel) indicates the voltage of the main word line MWL corresponding to the unselected word line WL. Similarly, bMWL(WLsel) indicates the voltage of the main word line bMWL corresponding to the selected word line WL. bMWL(WLnonsel) indicates the voltage of the main word line bMWL corresponding to the unselected word line WL. The bank address BA and signal VD are assumed to be of the same logic. Furthermore, the first voltage at power terminal PS1 is H1, the second voltage at power terminal PS2 is H2, and the third voltage at power terminal PS3 is L.

[0069] (Non-selected bank) Between t0 and t1, the bank address BA, i.e., the signal VD, is inactive at a low level. In this case, bank BK is in an unselected state. In an unselected bank BK, all word lines WL are unselected word lines, so all main word lines MWL and bMWL become main word line MWL(WLnonsel) and bMWL(WLnonsel).

[0070] In the non-selected bank BK, the switching circuit SWC2 in Figure 4 outputs the third voltage L (e.g., -1.5V) at the power supply terminal PS3. Therefore, the main word line MWL (WLnonsel) is maintained at the third voltage L. As a result, in the non-selected bank BK, the word line WL is electrically disconnected from the word drive line WDRV.

[0071] On the other hand, in the non-selected bank BK, the switching circuit SWC1 in Figure 4 selectively outputs the second voltage H2 (e.g., 0.5V) from the power supply terminal PS2. Furthermore, the switching circuit SWC3 receives the third voltage L from the switching circuit SWC2 and outputs a high-level voltage with the inverse logic of the third voltage L, i.e., the second voltage H2 from the switching circuit SWC1. Therefore, the voltage of the main word line bMWL (WLnonsel) becomes the second voltage H2 (e.g., 0.5V) from the power supply terminal PS2. In this case, the transistor bTRw turns on, but its channel resistance is relatively high. Therefore, in the non-selected bank BK, the word line WL is connected to the word drive line VUX in an electrically higher resistance state compared to the case of the first voltage H1. However, in the standby state of the non-selected bank BK, coupling noise does not need to be considered. Also, since there is no non-selected word line WL that shares the selected word line WL and the word drive line WDRV in the non-selected bank BK, leakage current from the word drive line WDRV does not need to be considered. Therefore, in the non-selected bank BK, it is not a problem if the word line WL is connected to the word drive line VUX with a relatively high resistance.

[0072] Thus, in standby mode, the voltage of the main word line bMWL (WLnonsel) is maintained at the second voltage H2 of the power terminal PS2, making the transistor bTRw less susceptible to the effects of PBTI and other factors, and thus less prone to degradation.

[0073] (Selection Bank) At t1, when bank address BA and signal VD are activated to a high level, bank BK becomes selected. In selected bank BK, the main word lines MWL and bMWL are divided into main word line MWL(WLsel) and bMWL(WLsel) corresponding to the selected word line WL, and main word line MWL(WLnonsel) and bMWL(WLnonsel) corresponding to the unselected word line WL.

[0074] The switching circuit SWC1 in Figure 4 selectively outputs the first voltage H1 (for example, 2V) from the power supply terminal PS1.

[0075] During t1 to t2, the word line addresses WA are still inactive at a low level. Therefore, the voltages of the main word lines MWL (WLsel) and MWL (WLnonsel) are still at the third voltage L. The voltages of the main word lines bMWL (WLsel) and bMWL (WLnonsel) become the first voltage H1 (e.g., 2V) according to the output of the switching circuit SWC1.

[0076] During t2 to t3, access operations, either read or write, are performed on bank BK.

[0077] At t2, when the word line address WA is selectively activated, the switching circuit SWC2 corresponding to the selected word line WL outputs a first voltage H1 at the power terminal PS1. As a result, the switching circuit SWC2 selectively applies the first voltage H1 to the main word line MWL (WLsel). In addition, the switching circuit SWC3 receives the first voltage H1 from the switching circuit SWC2 and outputs a third voltage L, which is a low level with the inverse logic of the first voltage H1. Therefore, the voltage of the main word line bMWL (WLsel) becomes the third voltage L. As a result, the selected word line WL is connected to the word drive line WDRV and electrically disconnected from the word drive line VUX. Consequently, the voltage of the selected word line WL becomes the voltage according to the word drive line WDRV.

[0078] On the other hand, the switching circuit SWC2 corresponding to the unselected word line WL outputs a third voltage L at the power supply terminal PS3. As a result, the switching circuit SWC2 selectively applies the third voltage L to the main word line MWL (WLnonsel). Also, the switching circuit SWC3 receives the third voltage L from the switching circuit SWC2 and outputs a high-level voltage with the inverse logic of the third voltage L, i.e., the first voltage H1 of the switching circuit SWC1. Therefore, the voltage of the main word line bMWL (WLnonsel) becomes the first voltage H1. As a result, the unselected word line WL is connected to the word drive line VUX and electrically disconnected from the word drive line WDRV. As a result, the voltage of the unselected word line WL becomes the voltage according to the word drive line VUX. At this time, the first voltage H1, a high-level voltage, is applied to the gate of the transistor bTRw between the unselected word line WL and the word drive line VUX. However, the period during which one of the multiple banks BK is accessed as the selected bank is very short and limited compared to the standby state period. Therefore, the influence of PBTI on transistor bTRw in the selected bank BK is relatively small.

[0079] At time t3, when a read or write operation is completed, the word line address WA is deactivated. Consequently, the switching circuit SWC2 corresponding to the selected word line WL outputs a third voltage L at the power terminal PS3. As a result, the switching circuit SWC2 applies the third voltage L to the main word line MWL (WLsel). In addition, the switching circuit SWC3 receives the third voltage L from the switching circuit SWC2 and outputs a first voltage H1, which is a high level with the inverse logic of the third voltage L. Therefore, the voltage of the main word line bMWL (WLsel) becomes the first voltage H1. As a result, the selected word line WL is electrically connected to the word drive line VUX and electrically disconnected from the word drive line WDRV. Consequently, the voltage of the selected word line WL becomes the voltage according to the word drive line VUX.

[0080] On the other hand, the switching circuit SWC2 corresponding to the unselected word line WL maintains the output of the third voltage L at the power terminal PS3. As a result, the switching circuit SWC2 selectively applies the third voltage L to the main word line MWL (WLnonsel). Also, the switching circuit SWC3 receives the third voltage L from the switching circuit SWC2 and maintains the output of the first voltage H1. Therefore, the voltage of the main word line bMWL (WLnonsel) becomes the first voltage H1. As a result, the unselected word line WL is connected to the word drive line VUX and electrically disconnected from the word drive line WDRV. The unselected word line WL maintains the voltage according to the word drive line VUX. That is, at t3~t4, both the main word lines MWL (WLsel) and MWL (WLnonsel) of the selected bank BK become the third voltage L. Both the main word lines bMWL (WLsel) and bMWL (WLnonsel) become the first voltage H1.

[0081] At t4, when bank address BA and signal VD are deactivated to a low level, bank BK becomes unselected. In the unselected bank BK, as in the state of t0~t1, all main word lines MWL and bMWL become main word line MWL(WLnonsel) and bMWL(WLnonsel). The voltage of main word line MWL(WLnonsel) is maintained at the third voltage L. The voltage of main word line bMWL(WLnonsel) becomes the second voltage H2 (e.g., 0.5V) of the power supply terminal PS2. Therefore, in the standby state, since the voltage of main word line bMWL(WLnonsel) is maintained at the second voltage H2 of the power supply terminal PS2, transistor bTRw becomes less susceptible to the effects of PBTI, etc., and is less prone to degradation.

[0082] (Second Embodiment) Figure 6 is a block diagram showing an example configuration of a semiconductor memory device according to the second embodiment. In the second embodiment, the main word line driver DRV further comprises a plurality of switching circuits SWC4. The plurality of switching circuits SWC4 are provided between the plurality of main word lines MWL and the plurality of switching circuits SWC2. The switching circuits SWC4 are provided corresponding to each of the plurality of main word lines MWL.

[0083] The switching circuit SWC4 comprises transistor Tp3, transistor Tp4, and inverter circuit IN5.

[0084] One of the sources and drains of transistor Tp3, which acts as a third switching element, is connected to the output of switching circuit SWC2, and the other is connected to the main word line MWL. The gate of transistor Tp3 receives a first signal corresponding to the bank address BA. The first signal is, for example, a signal VD corresponding to bank address BA, inverted by inverter circuit IN5. Transistor Tp3 is, for example, a p-type MOSFET. Transistor Tp3 turns on, for example when bank address BA rises to a high level, and connects the output of switching circuit SWC2 to the main word line MWL, supplying a first voltage (e.g., 2V) or a third voltage (e.g., -1.5V) to the main word line MWL. The p-type transistor Tp3 and inverter circuit IN5 may be replaced with n-type transistors. This allows the switching circuit SWC4 to consist of a single CMOS, simplifying the circuit configuration.

[0085] One of the sources and drains of transistor Tp4, which acts as a fourth switching element, is connected to the power supply terminal PS4, and the other is connected to the main word line MWL. The gate of transistor Tp4 receives a second signal corresponding to the bank address BA. The second signal is, for example, the non-inverted signal VD corresponding to the bank address BA. Transistor Tp4 is, for example, a p-type MOSFET. Transistor Tp4 turns on, for example when the bank address BA is falling to a low level, and supplies a fourth voltage (for example, 0.5V) to the main word line MWL by connecting the power supply terminal PS4 to the main word line MWL.

[0086] The inverter circuit IN5 is connected to the output of the bank address decoder BAD and outputs an inverted signal VD.

[0087] The fourth voltage is lower than the first voltage of power terminal PS1 (e.g., 2V) and higher than the third voltage of power terminal PS3 (e.g., -1.5V). The fourth voltage may also be different from the second voltage (e.g., 0.3V), for example, 0.5V. However, to reduce the number of power terminals, it is preferable that the fourth voltage is equal to the second voltage of power terminal PS2 (e.g., 0.3V). Hereafter, the fourth voltage will be described as being equal to the second voltage, for example, 0.3V.

[0088] For example, in selection bank BK, in switching circuit SWC4, transistor Tp3 is turned on, and the output of switching circuit SWC2 is connected to the main word line MWL. At this time, transistor Tp4 is in the off state.

[0089] Furthermore, within the selection bank BK, the switching circuit SWC2 corresponding to the selected word line WL outputs a first voltage (e.g., 2V) at the power supply terminal PS1 according to the word line address WA. Therefore, the switching circuit SWC4 connects the power supply terminal PS1 to the main word line MWL corresponding to the selected word line WL and applies the first voltage (e.g., 2V).

[0090] Furthermore, within the selection bank BK, the switching circuit SWC2 corresponding to the unselected word line WL outputs a third voltage (e.g., -1.5VV) at the power terminal PS3 according to the word line address WA. Therefore, the switching circuit SWC4 connects the power terminal PS3 to the main word line MWL corresponding to the unselected word line WL and applies the third voltage (e.g., -1.5V).

[0091] On the other hand, in the non-selected bank BK, the switching circuit SWC4 turns on transistor Tp4, connects the power supply terminal PS4 to the main word line MWL, and applies a fourth voltage (for example, 0.3V) to the main word line MWL. At this time, transistor Tp3 is in the off state.

[0092] Within the non-selected bank BK, all word lines WL are non-selected. Therefore, the switching circuit SWC4 applies the fourth voltage (e.g., 0.3V) from the power supply terminal PS4 to all main word lines MWL within the non-selected bank BK.

[0093] In this way, the switching circuit SWC4 applies one of the power terminals PS1, PS3, and PS4 to each of the multiple main word lines MWL based on the bank address BA and word line address WA.

[0094] Other configurations and functions of the second embodiment may be the same as those of the first embodiment.

[0095] Next, the operation of the semiconductor memory device according to the second embodiment will be described.

[0096] Figure 7 is a timing diagram showing an example of operation of a semiconductor memory device according to the second embodiment. The first voltage at power terminal PS1 is set to H1 (for example, 2V), the second and fourth voltages at power terminals PS2 and PS4 are both set to H3 (for example, 0.3V), and the third voltage at power terminal PS3 is set to L (for example, -1.5V). Note that H3 may be a voltage less than 0.3V.

[0097] (Non-selected bank) Between t0 and t1, the bank address BA, i.e., the signal VD, is inactive at a low level. In this case, bank BK is in an unselected state. In the unselected bank BK, all main word lines MWL and bMWL become main word line MWL(WLnonsel) and bMWL(WLnonsel).

[0098] In the non-selected bank BK, the switching circuit SWC4 in Figure 6 outputs the fourth voltage H3 (e.g., 0.3V) at the power supply terminal PS4. Therefore, the main word line MWL (WLnonsel) is maintained at the fourth voltage H3. In this case, although the transistor TRw is turned on, its channel resistance is relatively high. Therefore, in the non-selected bank BK, the word line WL is electrically connected to the word drive line WDRV with higher resistance compared to the case of the first voltage H1. However, in the standby state of the non-selected bank BK, the word line WL is not driven at high speed, so the voltage of the word line WL can be maintained at the word drive line WDRV (e.g., -1V).

[0099] As a result, in the non-selected bank BK, the word line WL is electrically connected to the word drive line WDRV, but in a high-resistance state.

[0100] On the other hand, the switching circuit SWC1 in Figure 6 selectively outputs the second voltage H2 (e.g., 0.3V) from the power supply terminal PS2. Also, in the non-selected bank BK, all word line addresses WA are inactive at a low level, so the switching circuit SWC2 outputs the third voltage L (e.g., -1.5V) from the power supply terminal PS3. Therefore, the switching circuit SWC3 receives the third voltage L from the switching circuit SWC2 and outputs a voltage on the high-level side of the inverse logic of the third voltage L, i.e., the second voltage H2 from the switching circuit SWC1. Thus, the voltage of the main word line bMWL (WLnonsel) becomes the second voltage H2 (e.g., 0.3V) from the power supply terminal PS2. In this case, the transistor bTRw turns on, but the channel resistance is relatively high. Therefore, in the non-selected bank BK, the word line WL is electrically connected to the word drive line VUX with a higher resistance compared to the case of the first voltage H1. However, in the standby state of the unselected bank BK, the word line WL is not driven at high speed, so the voltage of the word line WL can be maintained at the word drive line VUX (e.g., -1V).

[0101] Thus, in the standby state, the voltages of both the main word line MWL (WLnonsel) and bMWL (WLnonsel) are maintained at the second or fourth voltage H2 or H3 (e.g., both 0.3V) of the power terminals PS2 and PS4. In the second embodiment, both VUX and the word drive line WDRV, maintained at a low level voltage (e.g., -1V) in the standby state, apply the second and fourth voltages H2 and H3 to the word line WL via transistors bTRw and TRw, respectively. As a result, in the second embodiment, the second and fourth voltages H2 and H3 can be made smaller than the second voltage H2 (e.g., 0.5V) in the first embodiment. This further reduces the effects of PBTI etc. on transistor bTRw and further suppresses the degradation of transistor bTRw.

[0102] Other operations of the unselected bank BK in the second embodiment are the same as those of the unselected bank BK in the first embodiment.

[0103] (Selection Bank) At t1, when bank address BA and signal VD are activated to a high level, bank BK becomes selected. In the selected bank BK, the main word lines MWL and bMWL are divided into main word line MWL(WLsel) and bMWL(WLsel) corresponding to the selected word line WL, and main word line MWL(WLnonsel) and bMWL(WLnonsel) corresponding to the unselected word line WL.

[0104] The switching circuit SWC1 in Figure 6 selectively outputs the first voltage H1 (for example, 2V) from the power supply terminal PS1.

[0105] During t1 to t2, the word line addresses WA are still inactive at a low level. Therefore, the voltages of the main word lines MWL (WLsel) and MWL (WLnonsel) are still at the third voltage L. The voltages of the main word lines bMWL (WLsel) and bMWL (WLnonsel) become the first voltage H1 (e.g., 2V) according to the output of the switching circuit SWC1.

[0106] During t2 to t3, access operations, either read or write, are performed on bank BK.

[0107] At time t2, when the word line address WA is selectively activated, the switching circuit SWC2 corresponding to the selected word line WL outputs the first voltage H1 at the power supply terminal PS1. As a result, the switching circuit SWC2 selectively applies the first voltage H1 to the switching circuit SWC4.

[0108] In the switching circuit SWC4, the inverter circuit IN5 receives the bank address BA and outputs a low-level voltage with the inverse logic of the signal VD. Therefore, transistor Tp3 turns on and applies the first voltage H1 from the switching circuit SWC2 to the main word line MWL(WLsel) corresponding to the selected word line WL. Also, transistor Tp4 turns off upon receiving the bank address BA. As a result, the voltage across the main word line MWL(WLsel) becomes the first voltage H1.

[0109] Furthermore, the switching circuit SWC3 receives the first voltage H1 from the switching circuit SWC2 and outputs a third voltage L, which is a low level voltage with the inverse logic of the first voltage H1. Therefore, the voltage of the main word line bMWL (WLsel) becomes the third voltage L. As a result, the selection word line WL is electrically connected to the word drive line WDRV and electrically disconnected from the word drive line VUX. Consequently, the voltage of the selection word line WL becomes the same as that of the word drive line WDRV.

[0110] On the other hand, the switching circuit SWC2, which corresponds to the unselected word line WL, outputs a third voltage L at the power supply terminal PS3. As a result, the switching circuit SWC2 selectively applies the third voltage L to the switching circuit SWC4.

[0111] In the switching circuit SWC4, the inverter circuit IN5 receives the bank address BA and outputs a low-level voltage with the inverse logic of the signal VD. Therefore, transistor Tp3 turns on and applies the third voltage L from the switching circuit SWC2 to the main word line MWL (WLnonsel), which corresponds to the unselected word line WL. Also, transistor Tp4 turns off upon receiving the bank address BA. As a result, the voltage across the main word line MWL (WLnonsel) becomes the third voltage L.

[0112] Furthermore, the switching circuit SWC3 receives a third voltage L from the switching circuit SWC2 and outputs a high-level voltage with the inverse logic of the third voltage L, i.e., the first voltage H1 of the switching circuit SWC1. Therefore, the voltage of the main word line bMWL (WLnonsel) becomes the first voltage H1. As a result, the non-selected word line WL is connected to the word drive line VUX and electrically disconnected from the word drive line WDRV. Consequently, the voltage of the non-selected word line WL becomes the same as that of the word drive line VUX. At this time, the first voltage H1, a high-level voltage, is applied to the gate of the transistor bTRw between the non-selected word line WL and the word drive line VUX. As a result, the voltage states of the main word lines MWL and bMWL in the selection bank BK of the second embodiment become the same as those of the selection bank BK of the first embodiment.

[0113] At time t3, when a read or write operation is completed, the word line address WA is deactivated. Consequently, the switching circuit SWC2 corresponding to the selected word line WL outputs a third voltage L at the power terminal PS3. Therefore, the switching circuit SWC4 applies the third voltage L to the main word line MWL (WLsel) corresponding to the selected word line WL. The switching circuit SWC3 receives the third voltage L from the switching circuit SWC2 and outputs a first voltage H1, which is a high level with the inverse logic of the third voltage L. Therefore, the voltage of the main word line bMWL (WLsel) becomes the first voltage H1. As a result, the selected word line WL is electrically connected to the word drive line VUX and electrically disconnected from the word drive line WDRV. Consequently, the voltage of the selected word line WL becomes the voltage according to the word drive line VUX.

[0114] On the other hand, the switching circuit SWC2 corresponding to the unselected word line WL maintains the output of the third voltage L at the power terminal PS3. As a result, the switching circuit SWC4 still applies the third voltage L from the switching circuit SWC2 to the main word line MWL (WLnonsel). Also, the switching circuit SWC3 receives the third voltage L from the switching circuit SWC2 and maintains the output of the first voltage H1. Therefore, the voltage of the main word line bMWL (WLnonsel) becomes the first voltage H1. As a result, the unselected word line WL is connected to the word drive line VUX and electrically disconnected from the word drive line WDRV, maintaining the voltage according to the word drive line VUX. That is, at t3~t4, both the main word lines MWL (WLsel) and MWL (WLnonsel) of the selected bank BK become the third voltage L. Both the main word lines bMWL (WLsel) and bMWL (WLnonsel) become the first voltage H1.

[0115] At t4, when bank address BA and signal VD are deactivated to a low level, bank BK becomes unselected. In the unselected bank BK, as in the state at t0-t1, all main word lines MWL and bMWL become main word line MWL(WLnonsel) and bMWL(WLnonsel). The voltages of main word line MWL(WLnonsel) and bMWL(WLnonsel) are maintained at the fourth and second voltages H3 and H2 (for example, both 0.3V), respectively.

[0116] Thus, in the standby state, the voltages of both the main word line MWL (WLnonsel) and bMWL (WLnonsel) are maintained at the second or fourth voltage H2 or H3 (e.g., both 0.3V) of the power terminals PS2 and PS4. In the second embodiment, both the word drive lines WDRV and VUX, maintained at a low voltage (e.g., -1V) in the standby state, apply the fourth and second voltages H3 and H2 to the word line WL via transistors TRw and bTRw, respectively. As a result, in the second embodiment, the second and fourth voltages H2 and H3 can be made smaller than the second voltage H2 (e.g., 0.5V) in the first embodiment. This further reduces the effects of PBTI and other factors on transistor bTRw and further suppresses the degradation of transistor bTRw.

[0117] Other operations of the second embodiment are the same as those of the first embodiment. Therefore, the second embodiment can achieve the same effects as the first embodiment.

[0118] (modified version) The transistors constituting the cell transistor CT, transistors TRw, bTRw, TRb, Tp1 to Tp4, and inverter circuits IN1 to IN5 may be MOSFETs using oxide semiconductors in at least the channel region.

[0119] The above transistor is constructed using an oxide semiconductor. The channel material of the cell transistor CT is composed of an oxide semiconductor material including, for example, an n-type or p-type material system. The channel material may contain, for example, indium, gallium, zinc, and oxygen (for example, in the form of indium gallium zinc oxide (IGZO)), and such a channel material may have n-type conductivity. The channel material may include, for example, tin and oxygen (for example, in the form of tin oxide), antimony and oxygen (for example, in the form of antimony oxide), indium and oxygen (for example, in the form of indium oxide), indium, tin, and oxygen (for example, in the form of indium tin oxide), titanium and oxygen (for example, in the form of titanium oxide), zinc and oxygen (for example, in the form of zinc oxide), indium, zinc, and oxygen (for example, in the form of indium zinc oxide), gallium and oxygen (for example, in the form of gallium oxide), titanium, oxygen, and nitrogen (for example, in the form of titanium oxynitride), ruthenium and oxygen (for example, in the form of ruthenium oxide), or tungsten and oxygen (for example, in the form of tungsten oxide).

[0120] The material constituting the channel region of the above transistor is preferably a crystalline oxide semiconductor, but may also be an amorphous oxide semiconductor. Specific examples of oxide semiconductors include zinc tin oxide (ZTO), IGZO (also called gallium indium zinc oxide (GIZO)), indium zinc oxide (IZO), ZnOx, InOx, In2O3, SnO2, TiOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaxSiyOz, and other similar materials.

[0121] This leads to lower power consumption in the semiconductor memory device according to this embodiment.

[0122] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of symbols]

[0123] MCA Memory Cell Array Banks BK0 to BK7 SUBARR subarray PRI peripheral circuits WL Word Line VBL bit line MWL, bMWL Main Word Line GBL Global Bit Line VBLSEL bit selection line WDRV, VUX word drive line RD Raw Decoder DRV Main Word Line Driver SA Sense Amplifier Circuit TRw, bTRw, TRb transistor PS1~PS4 power terminal SWC1~SWC4 Switching Circuits

Claims

1. A memory unit comprising multiple banks, each containing multiple memory cells, wherein each bank is a memory unit that is selectively accessed during a read or write operation. In the memory section, a plurality of first wirings are connected in common to the plurality of memory cells arranged in a first direction, In the memory section, a plurality of second wirings are connected in common to the plurality of memory cells arranged in a second direction intersecting the first direction, A plurality of third wirings are provided in common to a plurality of second wirings arranged in a third direction intersecting the first and second directions, A plurality of first drive lines are provided in common to the plurality of first wirings arranged in the third direction, A plurality of first transistors, one of which is connected to the plurality of first wirings and the other to the plurality of first drive lines, A plurality of fourth wires, which are commonly connected to the gates of the plurality of first transistors arranged in the second direction, A plurality of second drive lines are provided in common to the plurality of first wirings arranged in the second direction, A plurality of second transistors, one of which is connected to the plurality of first wirings and the other to the plurality of second drive lines, A plurality of fifth wires, which are commonly connected to the gates of the plurality of second transistors arranged in the second direction, The system comprises a driver circuit that drives the voltages of the fourth and fifth wirings, The driver circuit applies a first voltage to a fifth wire corresponding to a non-selected first wire in a first bank selected from among the plurality of banks, and applies a second voltage having an absolute value smaller than the absolute value of the first voltage to a plurality of fifth wires in a second bank that are not selected.

2. A first power supply terminal that supplies the first voltage, The second power supply terminal that supplies the second voltage, The device further comprises a third power supply terminal that supplies a third voltage to be applied to the fifth wiring corresponding to the first wiring selected as the target for reading or writing in the first bank, The semiconductor memory device according to claim 1, wherein the second voltage is higher than the third voltage.

3. The aforementioned driver circuit is The first voltage is applied to the fourth wiring corresponding to the first wiring selected in the first bank. The semiconductor memory device according to claim 2, wherein the third voltage is applied to the plurality of fourth wirings in the second bank.

4. The aforementioned driver circuit is The semiconductor memory device according to claim 2, further comprising a plurality of first switching circuits provided corresponding to each of the plurality of banks, which connect either the first or second power supply terminal to the fifth wiring based on a first address for selecting the first bank.

5. The first switching circuit is, A first switching element whose source and drain are connected to the first power supply terminal and whose other is connected to one of the plurality of fifth wirings, and whose gate receives a first signal corresponding to the first address, The semiconductor memory device according to claim 4, comprising a second switching element whose source and drain are connected to the second power supply terminal and whose other is connected to one of the plurality of fifth wirings, and whose gate receives a second signal which is inverse logic of the first signal.

6. The first switching element connects the first power supply terminal to the fifth wiring corresponding to the unselected first wiring in the first bank. The semiconductor memory device according to claim 5, wherein the second switching element connects the second power supply terminal to a plurality of the fifth wirings in the second bank.

7. The aforementioned driver circuit is The semiconductor memory device according to any one of claims 2 to 5, further comprising a plurality of second switching circuits provided corresponding to each of the plurality of fourth wirings, and connecting either the first and third power supply terminals to each of the plurality of fourth wirings based on a second address for selecting the first wiring to be read or written in the first bank.

8. The second switching circuit described above is: The semiconductor memory device according to claim 7, comprising a first inverter circuit connected to the first and third power terminals, which applies the first voltage to the fourth wiring corresponding to the first wiring selected in the first bank based on the second address, and applies the third voltage to the fourth wiring corresponding to the first wiring not selected in the first bank.

9. The aforementioned driver circuit is The semiconductor memory device according to any one of claims 4 to 6, further comprising a plurality of third switching circuits provided corresponding to each of the plurality of fifth wirings, which apply either the first or second power supply terminal and the third power supply terminal from the first switching circuit to each of the plurality of fifth wirings based on a second address for selecting the first wiring to be read or written in the first bank.

10. The semiconductor memory device according to any one of claims 2 to 6, wherein the driver circuit applies a fourth voltage lower than the first voltage and higher than the third voltage to a plurality of the fourth wirings in the second bank.

11. The semiconductor memory device according to claim 10, wherein the fourth voltage is equal to the second voltage.

12. The aforementioned driver circuit is The fourth power supply terminal that supplies the fourth voltage, A plurality of second switching circuits are provided corresponding to each of the plurality of fourth wirings, and based on a second address that selects the first wiring to be read or written in the first bank, either the first or third power supply terminal is connected to each of the plurality of fourth wirings, The semiconductor memory device according to claim 10, further comprising a plurality of fourth switching circuits, each provided between the plurality of fourth wirings and the plurality of second switching circuits, which connect either the first or third power supply terminal and the fourth power supply terminal to each of the plurality of fourth wirings based on a first address for selecting the first bank.

13. The fourth switching circuit is, A third switching element whose source and drain are connected to the first or third power supply terminal via the second switching circuit, and whose other is connected to one of the plurality of fourth wirings, and whose gate receives a first signal corresponding to the first address, The semiconductor memory device according to claim 12, further comprising a fourth switching element, one of which is connected to the fourth power terminal and the other to one of the plurality of fourth wirings, the gate of which receives a second signal having the inverse logic of the first signal.

14. Each of the aforementioned plurality of memory cells is, A cell transistor having at least one source and drain connected to one of the plurality of second wirings and a gate connected to one of the plurality of first wirings, The semiconductor memory device according to claim 1, further comprising at least one cell capacitor, one end of which is connected to the other end of the source and drain of the cell transistor.

15. The semiconductor memory device according to claim 14, wherein the cell transistor includes an oxide semiconductor in the channel region.

16. A memory unit comprising multiple banks, each containing multiple memory cells, wherein each bank is a memory unit selectively accessed in a read or write operation, and includes a plurality of first wirings commonly connected to the plurality of memory cells arranged in a first direction, a plurality of second wirings commonly connected to the plurality of memory cells arranged in a second direction intersecting the first direction, a plurality of third wirings commonly provided to the plurality of second wirings arranged in a third direction intersecting the first and second directions, a plurality of first drive lines commonly provided to the plurality of first wirings arranged in the third direction, and a source and a drain. A control method for a semiconductor memory device comprising: a plurality of first transistors, one of which is connected to the plurality of first wirings and the other to the plurality of first drive lines; a plurality of fourth wirings, commonly connected to the gates of the plurality of first transistors arranged in the second direction; a plurality of second drive lines, commonly provided for the plurality of first wirings arranged in the second direction; a plurality of second transistors, one of which is connected to the plurality of first wirings and the other to the plurality of second drive lines; a plurality of fifth wirings, commonly connected to the gates of the plurality of second transistors arranged in the second direction; and a driver circuit for driving the voltages of the fourth and fifth wirings, wherein A first voltage is applied to the fifth wiring corresponding to the unselected first wiring in the first bank selected from the plurality of banks. A control method for a semiconductor memory device, comprising applying a second voltage having an absolute value smaller than the absolute value of the first voltage to a plurality of fifth wirings in a non-selected second bank.

Images