Multilayer ceramic capacitor

Abstract

We provide multilayer ceramic capacitors with high reliability. [Solution] A multilayer ceramic capacitor comprising: a laminate comprising: an inner layer comprising a plurality of alternating layers of dielectric layers and internal electrode layers; a pair of outer layers sandwiching the inner layer from the stacking direction; and a pair of side margins sandwiching the inner layer and outer layer from the width direction perpendicular to the stacking direction; and a pair of external electrodes comprising a first external electrode and a second external electrode, respectively, arranged at both ends of the laminate in the length direction perpendicular to the stacking direction and the width direction, and providing conductivity to a first internal electrode layer and a second internal electrode layer constituting the internal electrode layer, wherein the internal electrode layer contains any metal such as Cu, Ni, Ag, Pd, and Au, or an alloy of Ag and Pd, and in the side margins of the cross section defined in the width direction and the stacking direction when the laminate is cut at the center in the length direction, crystalline oxides containing Al, Mg, and Si exist as a phase with an aspect ratio of 12.4 or more and 20 or less.

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic capacitor.

Background Art

[0002] A multilayer ceramic capacitor generally includes a laminate in which dielectric layers and internal electrode layers are alternately laminated, and further dielectric layers are laminated on the upper and lower surfaces thereof, and a pair of external electrodes formed on both end faces of the laminate. However, in order to relatively increase the area of the internal electrode layer, there is a structure in which the laminate includes an inner layer portion in which a dielectric layer and an internal electrode layer are laminated to have a capacitance, and side margin portions in which dielectric layers are disposed on both sides of the inner layer portion (for example, Patent Document 1). In such a multilayer ceramic capacitor, in order to cope with the miniaturization and multifunctionalization of electronic products in recent years and to further reduce the size and increase the capacitance, it is important to reduce the thickness in the width direction of the side margin portion and increase the inner layer portion to secure a large area of the internal electrode layer.

[0003] However, when firing a laminate having a structure with side margin portions, due to the difference in shrinkage rate, gaps are likely to occur between the inner layer portion and the side margin portions, particularly between both end portions of the internal electrode layer and the left and right side margin portions. When moisture penetrates into such gaps, the insulation resistance between the dielectric layers deteriorates, and the function as a multilayer ceramic capacitor decreases. Such a problem becomes more serious as the thickness in the width direction of the side margin portion is reduced, which impairs the reliability of the multilayer ceramic capacitor.

[0004] Therefore, there is a need to develop a multilayer ceramic capacitor that is small, has a large capacitance, and has high reliability.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

[0006] The present invention aims to provide a multilayer ceramic capacitor that is compact, high-capacitance, and highly reliable by suppressing the occurrence of gaps between the inner layer and the side margin. [Means for solving the problem]

[0007] To solve the above problems, the inventors conducted studies and found that in the side margin portion constituting the laminate, a crystalline oxide containing at least one of Al, Mg, and Si segregates as a secondary phase with a predetermined cross-sectional shape, thereby enabling reliability in terms of moisture resistance and pressure resistance while maintaining a small size and large capacity, thus completing the present invention.

[0008] In other words, the present invention provides a laminate comprising: an inner layer portion in which a plurality of dielectric layers and internal electrode layers are alternately stacked; a pair of outer layer portions sandwiching the inner layer portion from the stacking direction; and a pair of side margin portions sandwiching the inner layer portion and the outer layer portion from a width direction perpendicular to the stacking direction. A pair of external electrodes, consisting of a first external electrode and a second external electrode, are arranged at both ends of the laminate in the length direction perpendicular to the lamination direction and the width direction, and are electrically connected to the first internal electrode layer and the second internal electrode layer that constitute the internal electrode layer, respectively. A multilayer ceramic capacitor equipped with, When the laminate is cut at the central position in the longitudinal direction and the cross-section defined in the width direction and the lamination direction is viewed, In the side margin portion, a crystalline oxide containing at least one of Al, Mg, and Si exists as a long secondary phase with an aspect ratio of 5 to 20 in this multilayer ceramic capacitor. [Effects of the Invention]

[0009] According to the present invention, it is possible to suppress the occurrence of gaps between the inner layer and the side margin, and to provide a multilayer ceramic capacitor that is compact and high-capacity, yet has excellent moisture resistance and voltage resistance, and high reliability. [Brief explanation of the drawing]

[0010] [Figure 1] This is a schematic perspective view showing an example of the multilayer ceramic capacitor of the present invention. [Figure 2] Figure 1 is a schematic perspective view showing an example of a laminate that makes up a multilayer ceramic capacitor. [Figure 3] Figure 1 is a cross-sectional view of a multilayer ceramic capacitor along line AA. [Figure 4] Figure 1 is a cross-sectional view of a multilayer ceramic capacitor along the CC line. [Figure 5] Figure 1 is a cross-sectional view of a multilayer ceramic capacitor along the BB line. [Figure 6] This is a schematic plan view showing an example of a ceramic green sheet. [Figure 7] This is a schematic plan view showing an example of a ceramic green sheet. [Figure 8] This is a schematic plan view showing an example of a ceramic green sheet. [Figure 9] This is a schematic exploded perspective view showing an example of a mother block. [Figure 10] This is a schematic perspective view showing an example of a green chip. [Figure 11] This is a diagram (photograph used as a substitute for a drawing) showing the distribution of Al in a cross-section along the CC line. [Figure 12] This is a diagram (photograph used as a substitute for a drawing) showing the distribution of Mg in a cross-section along the CC line. [Figure 13] This is a diagram (photograph used as a substitute for a drawing) showing the distribution of Si in a cross-section along the CC line. [Modes for carrying out the invention]

[0011] Hereinafter, the multilayer ceramic capacitor of the present invention will be described. However, the present invention is not limited to the following configuration, and can be appropriately modified and applied within the scope not changing the gist of the present invention.

[0012] [Multilayer Ceramic Capacitor] FIG. 1 is a perspective view schematically showing an example of the multilayer ceramic capacitor of the present invention. FIG. 2 is a perspective view schematically showing an example of the laminate constituting the multilayer ceramic capacitor shown in FIG. 1. FIG. 3 is a cross-sectional view taken along line A-A of the multilayer ceramic capacitor shown in FIG. 1. FIG. 4 is a cross-sectional view taken along line C-C of the multilayer ceramic capacitor shown in FIG. 1.

[0013] In this specification, the stacking direction, width direction, and length direction of the multilayer ceramic capacitor and the laminate are defined as the directions indicated by arrows T, W, and L in the multilayer ceramic capacitor 1 shown in FIG. 1 and the laminate 10 shown in FIG. 2, respectively. In the embodiment, the stacking (T) direction, width (W) direction, and length (L) direction are orthogonal to each other, but are not necessarily in an orthogonal relationship, and may be in an intersecting relationship with each other. The stacking (T) direction is the direction in which a plurality of dielectric layers 20 and a plurality of pairs of first internal electrode layers 21a and second internal electrode layers 21b are stacked.

[0014] The multilayer ceramic capacitor 1 shown in FIG. 1 includes a laminate 10 and a pair of external electrodes formed by a first external electrode 51a and a second external electrode 51b on both end faces of the laminate 10.

[0015] As shown in FIG. 2, the laminate 10 has a rectangular parallelepiped shape or a substantially rectangular parallelepiped shape, and includes a first main surface 11 and a second main surface 12 that face each other in the stacking (T) direction, a first side surface 13 and a second side surface 14 that face each other in the width (W) direction orthogonal to the stacking (T) direction, and a first end surface 15 and a second end surface 16 that face each other in the length (L) direction orthogonal to the stacking (T) direction and the width (W) direction.

[0016] In this specification, a cross-section of a multilayer ceramic capacitor 1 or laminate 10 that is perpendicular to the first end face 15 and the second end face 16 and parallel to the stacking (T) direction is referred to as the LT cross-section, which is the cross-section in the length (L) direction and the stacking (T) direction. A cross-section of a multilayer ceramic capacitor 1 or laminate 10 that is perpendicular to the first side surface 13 and the second side surface 14 and parallel to the stacking (T) direction is referred to as the WT cross-section, which is the cross-section in the width (W) direction and the stacking (T) direction. A cross-section of a multilayer ceramic capacitor 1 or laminate 10 that is perpendicular to the first side surface 13, the second side surface 14, the first end face 15 and the second end face 16 and perpendicular to the stacking (T) direction is referred to as the LW cross-section, which is the cross-section in the length (L) direction and the width (W) direction. Therefore, Figure 3 is the LT cross-section of the multilayer ceramic capacitor 1, and Figure 4 is the WT cross-section of the multilayer ceramic capacitor 1.

[0017] The laminate 10 preferably has rounded corners and edges. Corners are the parts where three faces of the laminate intersect, and edges are the parts where two faces of the laminate intersect.

[0018] As shown in Figures 2, 3, and 4, the laminate 10 has a laminated structure in which a plurality of dielectric layers 20 and a plurality of internal electrode layers 21 are stacked in the stacking (T) direction. The internal electrode layer 21 is composed of a first internal electrode layer 21a and a second internal electrode layer 21b, and the dielectric layer 20 is positioned between the first internal electrode layer 21a and the second internal electrode layer 21b. The dielectric layer 20 extends along the width (W) and length (L) directions, and the first internal electrode layer 21a and the second internal electrode layer 21b each extend in a flat plate shape along the dielectric layer 20.

[0019] In order to miniaturize and increase the capacitance of multilayer ceramic capacitors, it is necessary to stack many internal electrode layers and dielectric layers within a predetermined height range. Therefore, it is preferable that the thickness of the dielectric layer 20 sandwiched between the internal electrode layers 21a and 21b in the stacking (T) direction be 0.45 μm or less, and the external dimensions of the stacked body be 1.0 mm or less in length, 0.5 mm or less in width, and 0.5 mm or less in height.

[0020] The first internal electrode layer 21a is drawn out to the first end face 15 of the laminate 10. On the other hand, the second internal electrode layer 21b is drawn out to the second end face 16 of the laminate 10.

[0021] The first internal electrode layer 21a and the second internal electrode layer 21b face each other in the stacking (T) direction via the dielectric layer 20. Capacitance is generated in the portion where the first internal electrode layer 21a and the second internal electrode layer 21b face each other via the dielectric layer 20.

[0022] The first internal electrode layer 21a and the second internal electrode layer 21b each preferably contain a metal such as Ni, Cu, Ag, Pd, Ag-Pd alloy, or Au. In addition to the above metal, the first internal electrode layer 21a and the second internal electrode layer 21b may also contain the same dielectric ceramic material as the dielectric layer 20.

[0023] The first external electrode 51a is provided on the first end face 15 of the laminate 10, and in Figure 1, it has portions that wrap around to parts of the first main surface 11, the second main surface 12, the first side surface 13, and the second side surface 14. The first external electrode 51a is connected to the first internal electrode layer 21a at the first end face 15.

[0024] The second external electrode 51b is provided on the second end face 16 of the laminate 10, and in Figure 1, it has a portion that wraps around to a part of the first main surface 11, the second main surface 12, the first side surface 13, and the second side surface 14. The second external electrode 51b is connected to the second internal electrode layer 21b at the second end face 16.

[0025] The first external electrode 51a and the second external electrode 51b can be formed, for example, by a base electrode layer and a plating layer placed on the base electrode layer. The base electrode layer is formed by applying a conductive paste containing metal and glass components onto the end faces 15 and 16 of the laminate 10, and then baking it. As the metal component blended into the conductive paste, for example, metals such as Cu, Ni, Ag, Pd, and Au, or alloys of Ag and Pd can be used.

[0026] The plating layer placed on the base electrode layer includes at least one of the following: metals such as Cu, Ni, Ag, Pd, and Au, or an alloy of Ag and Pd. The plating layer can have a two-layer structure, for example, a Ni plating layer and a Sn plating layer. However, the plating layer may be one layer or multiple layers.

[0027] As shown in Figures 2, 3, and 4, the laminate 10 comprises an inner layer 30 in which a dielectric layer 20, a first inner electrode layer 21a, and a second inner electrode layer 21b are laminated; a pair of outer layer portions 31a and 31b arranged to sandwich the inner layer portion 30 in the lamination (T) direction; and a pair of side margin portions 41 and 42 arranged to sandwich the inner layer portion 30, the outer layer portion 31a, and the outer layer portion 31b in the width (W) direction. In Figures 3 and 4, the inner layer 30 is the region sandwiched between the first internal electrode layer 21a closest to the first main surface 11 and the first internal electrode layer 21a closest to the second main surface 12, along the stacking (T) direction. The outer layers 31a and 31b can have the same configuration as the dielectric layer 20 and can be formed from the same dielectric ceramic material as the dielectric layer 20.

[0028] The thickness of each of the outer layers 31a and 31b is preferably 15 μm or more and 40 μm or less. However, each of the outer layers 31a and 31b may be a single layer structure rather than a multilayer structure.

[0029] As shown in Figure 4, the side margins 41 and 42 are each formed by a single dielectric layer, but they may also be composed of multiple dielectric layers stacked in the width (W) direction.

[0030] The dielectric layer 20 and the side margin portions 41 and 42 are composed of a dielectric ceramic material, for example, one whose main component is BaTiO3. The main component forms the main phase. The dielectric layer 20 constituting the inner layer portion 30 may further contain sintering aid elements. However, the dielectric ceramic material used in the dielectric layer and the side margin portions can be selected to have the optimal composition depending on the purpose of placement and the properties required by the manufacturing method.

[0031] Figure 5 is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 1, along line BB. Figure 5 shows the LW cross-section of the multilayer ceramic capacitor 1. As shown in Figure 5, the second internal electrode layer 21b is exposed on the second end face 16 of the laminate 10. Side margin portions 41 and 42 are located on the first side surface 13 and the second side surface 14 of the laminate 10, respectively. As shown in Figure 5, interfaces 21b41 and 21b42 exist between the ends of the second internal electrode layer 21b and the left and right side margin portions 41 and 42.

[0032] [Crystalline oxides] The laminate was cut along the central position (CC line) in the length (L) direction, and the WT cross-section defined in the width (W) direction and the stacking direction (T) was observed in a 10 μm × 10 μm area using wavelength-dispersive X-ray spectroscopy (WDX). The results confirmed that in the side margin region, a crystalline oxide containing at least one of Al, Mg, and Si exists as a secondary phase in a long cross-section with an aspect ratio of 5 to 20. The aspect ratio was calculated as the ratio of the major axis length to the average minor axis length when the shape of the secondary phase observed in the cross-section was approximated as an ellipse of the same area. The average minor axis length and average major axis length were weighted by the area of ​​the approximated ellipse.

[0033] Figure 11 is an image showing the distribution of Al (element) in the inner layer and side margin of the CC line section, taken by wavelength-dispersive X-ray analysis (WDX). Figure 12 is an image showing the distribution of Mg (element), similarly. Figure 13 is an image showing the distribution of Si (element), similarly.

[0034] In a laminate with a side margin structure, if a metal or metal compound containing at least one of Al, Mg, and Si is incorporated into the side margin and fired, the difference in shrinkage rate between the inner layer and the side margin can be reduced, and the occurrence of gaps between the inner layer and the side margin, particularly between the ends of the inner electrode layer and the left and right side margins, can be suppressed. This prevents deterioration of insulation resistance caused by moisture intrusion into the gaps, and improves moisture resistance and pressure resistance. Furthermore, after firing, a crystalline oxide containing at least one of Al, Mg, and Si is distributed in the side margin as a long secondary phase with an aspect ratio of 5 to 20 in the cross-section of the CC line, maintaining moisture resistance and pressure resistance, and also showing excellent resistance to mechanical or thermal shock.

[0035] Such effects are achieved by the presence of a crystalline oxide containing at least one of Al, Mg, and Si in the side margin region. However, the effect can be further enhanced if the crystalline oxide contains two or all three of Al, Mg, and Si. Therefore, it is preferable that 90 atomic percent or more of the Mg contained in the crystalline oxide consists of a composite oxide containing Al, Mg, and Si, or that 90 atomic percent or more of the Al contained in the crystalline oxide consists of a composite oxide containing Al, Mg, and Si and a composite oxide containing Al and Si.

[0036] [Evaluation Test] Samples of multilayer ceramic capacitors containing crystalline aluminum oxide in the side margin were prepared in quantities of 100 for each predetermined aspect ratio of the secondary phase, and evaluation tests were conducted to assess their moisture resistance reliability and voltage resistance reliability.

[0037] The humidity resistance reliability test was conducted at 45°C and 95% RH under a voltage of 10 V / μm, maintaining a DC voltage application for 500 hours. Samples in which the insulation resistance dropped by an order of magnitude from the start of voltage resistance application were judged to be unsuccessful, and the number of such samples is listed in Table 1.

[0038] The insulation resistance degradation test was performed by maintaining an applied power of 2.5W for 1000 hours. Samples whose insulation resistance value decreased by one order of magnitude were judged as unsatisfactory, and the number of such samples is listed in Table 1.

[0039] In the evaluation tests for moisture resistance reliability and pressure resistance reliability, samples with aspect ratios that did not produce any defective products in either test were evaluated as pass (A), and samples with aspect ratios that produced any defective products in either test were evaluated as fail (B). The results of the overall evaluation are shown in Table 1.

[0040] [Table 1]

[0041] [Manufacturing method for multilayer ceramic capacitors] The following describes an example of a manufacturing method for the multilayer ceramic capacitor 1 shown in Figure 1.

[0042] A ceramic green sheet is prepared to form the dielectric layer 20, the outer layers 31a and 31b, and the side margins 41 and 42. The ceramic green sheet contains ceramic raw materials including the dielectric ceramic material described above, as well as a binder and a solvent. Additives containing rare earth elements may also be added to the ceramic raw materials. By changing the elements contained in the additives, the composition of the dielectric forming each part can be changed. Ceramic green sheets are formed, for example, on a carrier film using a die coater, gravure coater, microgravure coater, etc.

[0043] Figures 6, 7, and 8 are schematic plan views showing an example of a ceramic green sheet. Figures 6, 7, and 8 show a first ceramic green sheet 101 for forming the inner layer 30, a second ceramic green sheet 102 for forming the inner layer 30, and a third ceramic green sheet 103 for forming the outer layer 31a or 31b, respectively.

[0044] The first ceramic green sheet 101, the second ceramic green sheet 102, and the third ceramic green sheet 103 show cutting lines X and Y for cutting each multilayer ceramic capacitor 1. Cutting line X is parallel to the length (L) direction, and cutting line Y is parallel to the width (W) direction.

[0045] As shown in Figure 6, in the first ceramic green sheet 101, an unfired first internal electrode layer 121a, corresponding to the first internal electrode layer 21a, is formed on an unfired dielectric layer 120, corresponding to the dielectric layer 20.

[0046] As shown in Figure 7, in the second ceramic green sheet 102, an unfired second internal electrode layer 121b, corresponding to the second internal electrode layer 21b, is formed on an unfired dielectric layer 120, corresponding to the dielectric layer 20.

[0047] The method for producing the first ceramic green sheet 101 shown in Figure 6 and the second ceramic green sheet 102 shown in Figure 7 is not particularly limited, but one method is to apply a conductive paste, which will become the internal electrode layer 21a or 21b upon firing, to a predetermined area on the surface of the unfired dielectric layer 120.

[0048] As shown in Figure 8, the third ceramic green sheet 103, corresponding to the outer layer 31a or 31b, can be formed from an unfired dielectric layer 120 corresponding to the dielectric layer 20. The third ceramic green sheet 103 does not have an unfired internal electrode layer 121a or 121b formed on it, unlike the first ceramic green sheet 101 and the second ceramic green sheet 102.

[0049] The first internal electrode layer 121a and the second internal electrode layer 121b can be formed using any conductive paste. For example, screen printing, gravure printing, or other methods can be used to form the first internal electrode layer 121a and the second internal electrode layer 121b using a conductive paste.

[0050] The first internal electrode layer 121a and the second internal electrode layer 121b are arranged across two adjacent regions in the length (L) direction, separated by a cutting line Y, and extend in a strip shape in the width (W) direction. The regions separated by the cutting line Y are shifted by one row in the length (L) direction between the first internal electrode layer 121a and the second internal electrode layer 121b. That is, the cutting line Y passing through the center of the first internal electrode layer 121a passes through the region between adjacent second internal electrode layers 121b, and the cutting line Y passing through the center of the second internal electrode layer 121b passes through the region between adjacent first internal electrode layers 121a.

[0051] Subsequently, a mother block is fabricated by laminating the first ceramic green sheet 101, the second ceramic green sheet 102, and the third ceramic green sheet 103.

[0052] Figure 9 is a schematic exploded perspective view showing an example of a mother block. In Figure 9, for the sake of explanation, the first ceramic green sheet 101, the second ceramic green sheet 102, and the third ceramic green sheet 103 are shown disassembled. In the actual mother block 104, the first ceramic green sheet 101, the second ceramic green sheet 102, and the third ceramic green sheet 103 are pressed together and integrated by means of hydrostatic pressing or other means.

[0053] In the mother block 104 shown in Figure 9, the first ceramic green sheet 101 and the second ceramic green sheet 102, corresponding to the inner layer 30, are alternately stacked in the stacking (T) direction. Furthermore, the third ceramic green sheet 103, corresponding to the outer layers 31a and 31b, is stacked on the upper and lower surfaces of the alternately stacked first ceramic green sheet 101 and second ceramic green sheet 102 in the stacking (T) direction. In Figure 9, three third ceramic green sheets 103 are stacked on each side, but the number of third ceramic green sheets 103 can be changed as appropriate.

[0054] Multiple green chips are produced by cutting the obtained mother block 104 along the cutting lines X and Y (see Figures 6, 7, and 8). For this cutting, methods such as dicing, press cutting, and laser cutting can be applied.

[0055] Figure 10 is a schematic perspective view showing an example of a green chip. The green chip 110 shown in Figure 10 has a laminated structure composed of multiple unfired dielectric layers 120, a first internal electrode layer 121a, and a second internal electrode layer 121b. The first side surface 113 and the second side surface 114 of the green chip 110 are surfaces revealed by cutting along the cutting line X, and the first end surface 115 and the second end surface 116 are surfaces revealed by cutting along the cutting line Y. The first internal electrode layer 121a and the second internal electrode layer 121b are exposed on the first side surface 113 and the second side surface 114. The first internal electrode layer 121a is exposed on the first end surface 115, and the second internal electrode layer 121b is exposed on the second end surface 116.

[0056] Furthermore, when the mother block 104 is cut to obtain multiple green chips 110, the first side surface 113 and the second side surface 114 of the green chip 110 may undergo slight plastic deformation downward due to the stress applied in the cutting direction, which is downward in the diagram. In addition, the cut surface may not be sufficiently smooth, or foreign matter may be present on the cut surface. For this reason, it is preferable to polish the first side surface 113 and the second side surface 114 to remove the deformed portion.

[0057] An unfired laminate is produced by forming unfired side margins on the first side surface 113 and the second side surface 114 of the obtained green chip 110. The unfired side margins are formed, for example, by attaching ceramic green sheets made of dielectric ceramic to the first and second side surfaces of the green chip.

[0058] To produce a ceramic green sheet for forming the side margin, a ceramic slurry is prepared containing ceramic raw materials, including a dielectric ceramic material mainly composed of BaTiO3, as well as a binder and a solvent. At least one metal element from Al, Mg, and Si, which should be segregated as a crystalline oxide in the side margin, is added to the ceramic slurry. These components can be added as metals or compounds such as metal oxides. Furthermore, when adding multiple metal elements, they can be added as alloys or composite compounds such as composite metal oxides.

[0059] For example, Al2O3, MgO, and SiO2 can be prepared, weighed, and added separately. Alternatively, Al2O3, MgO, and SiO2 can be weighed in predetermined proportions, these weighed materials can be placed in a ball mill along with PSZ balls and pure water, thoroughly mixed and ground in a wet mill, then heat-treated at 900°C to produce a composite oxide, which can then be added to the ceramic slurry. Note that MgO can be produced by the thermal decomposition of MgCO3, so a predetermined amount of MgCO3 may be weighed and added.

[0060] A ceramic green sheet is formed by applying a ceramic slurry to the surface of a resin film and drying it. The ceramic green sheet is then peeled off the resin film.

[0061] Next, the ceramic green sheet and the first side surface 113 of the green chip 110 are placed opposite each other and pressed together to punch out an unfired side margin portion 41. Furthermore, the second side surface 114 of the green chip 110 is also placed opposite each other and pressed together to punch out an unfired side margin portion 42. As a result, an unfired laminate is obtained.

[0062] It is preferable to perform barrel polishing or the like on the unfired laminate obtained by the above method. By polishing the unfired laminate, the corners and edges of the fired laminate 10 are rounded.

[0063] A first external electrode 51a and a second external electrode 51b are formed on the first end face 15 and the second end face 16 of the laminate 10. The first external electrode 51a and the second external electrode 51b can be formed, for example, by a base electrode layer and a plating layer placed on the base electrode layer. The base electrode layer is formed by applying a conductive paste containing metal and glass components onto the end faces 15 and 16 of the laminate 10 and then baking it. Examples of metal components that can be incorporated into the conductive paste include metals such as Cu, Ni, Ag, Pd, and Au, or alloys of Ag and Pd.

[0064] The plating layer placed on the base electrode layer includes at least one of the following: metals such as Cu, Ni, Ag, Pd, and Au, or an alloy of Ag and Pd. The plating layer can have a two-layer structure, for example, a Ni plating layer and a Sn plating layer. However, the plating layer may be one layer or multiple layers.

[0065] Based on the above, a multilayer ceramic capacitor 1 is manufactured.

[0066] In the above embodiment, the mother block 104 was cut along cutting lines X and Y to obtain multiple green chips, and then unfired side margins were formed on both sides of the green chips. However, it is also possible to modify this as follows.

[0067] In other words, by cutting the mother block only along the cutting line X, a plurality of rod-shaped green block bodies are obtained in which the first internal electrode layer and the second internal electrode layer are exposed on the side surface revealed by the cutting along the cutting line X. Then, unfired side margin portions are formed on both sides of the green block bodies, and then the bodies are cut along the cutting line Y to obtain a plurality of unfired laminates. After firing, the unfired laminates can then be fired. After firing, a multilayer ceramic capacitor can be manufactured by performing the same process as in the above embodiment.

[0068] Although preferred embodiments of the present invention have been described above, the present invention is not limited thereto, and various modifications are possible. [Explanation of Symbols]

[0069] 1. Multilayer ceramic capacitor 10 Laminate 11. First main surface of the laminate 12. Second main surface of the laminate 13 First side of the laminate 14. Second side of the laminate 15. First end face of the laminate 16. Second end face of the laminate 20 Dielectric layer 21 Internal electrode layer 21a First internal electrode layer 21b Second internal electrode layer 30 Inner layer 31 Outer layer 31a Outer layer 31b Outer layer 41 Side margin section 42 Side margin section 51 External electrode 51a First external electrode 51b Second external electrode

Claims

1. A laminate comprising: an inner layer portion formed by alternately stacking multiple dielectric layers and internal electrode layers; a pair of outer layer portions sandwiching the inner layer portion from the stacking direction; and a pair of side margin portions sandwiching the inner layer portion and the outer layer portion from a width direction perpendicular to the stacking direction; A multilayer ceramic capacitor comprising a pair of external electrodes, a first external electrode and a second external electrode, arranged at both ends of the laminate in a length direction perpendicular to the stacking direction and the width direction, and which conduct to a first internal electrode layer and a second internal electrode layer constituting the internal electrode layer, respectively, The internal electrode layer contains any of the following: metals such as Cu, Ni, Ag, Pd, and Au, or an alloy of Ag and Pd. A multilayer ceramic capacitor, wherein the laminate is cut at the central position in the longitudinal direction, and in the side margin portion of the cross section defined in the width direction and the stacking direction, crystalline oxides containing Al, Mg, and Si exist as phases with an aspect ratio of 12.4 or more and 20 or less.

2. The multilayer ceramic capacitor according to claim 1, wherein the thickness of the dielectric layer sandwiched between the internal electrode layers in the stacking direction is 0.45 μm or less.

3. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein the external dimensions of the laminate are 1.0 mm or less in length, 0.5 mm or less in width, and 0.5 mm or less in height.

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