Semiconductor package, method for manufacturing a semiconductor package
The semiconductor package simplifies structure and reduces costs by using through electrodes formed through photolithography and wet plating, addressing the challenges of complex and costly conventional designs.
JP2026115117APending Publication Date: 2026-07-09SAMSUNG ELECTRONICS CO LTD
Patent Information
- Application Number
- JP2024231576
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-12-27
- Publication Date
- 2026-07-09
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Figure 2026115117000001_ABST
Abstract
The goal is to simplify the structure of semiconductor packages to reduce manufacturing costs while simultaneously achieving high capacity and high performance. [Solution] The semiconductor package 1 has a first surface 30a and a second surface 30b on the opposite side of the first surface 30a on which electrodes 31 are formed, and comprises a plurality of semiconductor chips 30 that are sequentially stacked in a second direction perpendicular to the first direction such that the electrodes 31 do not overlap with the first surface 30a in the first direction which is the stacking direction, and has an A surface 10a facing the semiconductor chips 30 and a B surface 10b on the opposite side of the A surface 10a, and is electrically connected to the semiconductor chips 30, and comprises a sealing resin layer 70 that seals the semiconductor chips 30, and comprises a plurality of through electrodes 40 composed of one or more conductive columnar parts 41 that electrically connect the semiconductor chips 30 and the redistribution layer 10 through the electrodes 31, and each of the through electrodes 40 extends in the first direction from the A surface 10a side of the redistribution layer 10 toward the electrodes 31 of the semiconductor chips 30, penetrating the sealing resin layer 70.
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Citation Information
Patent Citations
Flip chip stacking structure and method for forming same - Patents.com
JP2023531029A
