Control device and update method

Abstract

The present invention provides a control device that can update a program running on one core while continuing to run a program running on another core. [Solution] The control device comprises a ROM storing a program, a processor, and an output circuit. The processor includes multiple cores that load the program from the ROM and execute the program. The output circuit outputs an interrupt signal to the core executing the program when one of the multiple programs in the ROM is updated. When the core detects the interrupt signal, it reloads the updated program stored in the ROM.

Description

Technical Field

[0001] The present invention relates to a control device and an update method.

Background Art

[0002] A control device such as a CPU (Central Processing Unit) module has a ROM (Read Only Memory) storing a plurality of programs and a multi-core MPU having a first core and a second core. The multi-core MPU resets the programs being executed by all cores in response to a reset signal and reloads the programs stored in the ROM to each core.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When updating a program, the programs operating on all cores within the same multi-core MPU are stopped. However, in a conventional control device, for example, while updating the program of a core responsible for a control function, state monitoring by the function of a core responsible for a monitoring function cannot be continued. That is, in a conventional control device, while continuing the execution of a program operating on a core within the multi-core MPU, a program executed on another core within the same multi-core MPU cannot be updated.

[0005] In one aspect, an object is to provide a control device or the like that can continue the execution of a program operating on one core while updating the program operating on another core.

Means for Solving the Problems

[0006] In one embodiment, the control device disclosed herein includes a ROM storing a program, a processor, and an output circuit. The processor includes a plurality of cores that load the program from the ROM and execute the program. The output circuit outputs an interrupt signal to the core that executes the program when one of the plurality of programs in the ROM is updated. When the core detects the interrupt signal, it reloads the updated program stored in the ROM. [Effects of the Invention]

[0007] In one embodiment, a program running on one core can be updated while the execution of a program running on another core continues. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a block diagram showing an example of the control device of Example 1. [Figure 2] Figure 2 is a flowchart showing an example of the processing operation of the first core involved in the first update process and the second core involved in the second update process. [Figure 3] Figure 3 is a timing chart showing an example of the processing operations of the first core, second core, and ROM when the updated first program is reloaded onto the first core. [Figure 4] Figure 4 is a block diagram showing an example of the control device of Example 2. [Figure 5] Figure 5 is a block diagram showing an example of the control device of Example 3. [Figure 6] Figure 6 is a block diagram showing an example of the control device of Example 4. [Figure 7] Figure 7 is a flowchart showing an example of the processing operation of the first core group involved in the first core group update process and the second core group involved in the second core group update process. [Figure 8] Figure 8 is a block diagram showing an example of the control device of Example 5. [Figure 9]Figure 9 is a flowchart showing an example of the processing operations of the first and second cores within the first core group involved in the third update process. [Modes for carrying out the invention]

[0009] The embodiments of the control device and other devices disclosed herein will be described in detail below with reference to the drawings. However, these embodiments do not limit the disclosed technology. Furthermore, each embodiment described below may be modified as appropriate, provided that it does not create inconsistencies.

[0010] <Example 1> Figure 1 is a block diagram showing an example of the control device 1 of Embodiment 1. The control device 1 shown in Figure 1 includes a ROM (Read Only Memory) 2, a multi-core MPU 3, and a control circuit 4. The control device 1 is an asymmetric multi-processing (AMP) configuration in which the multi-core MPU 3 is executed on all cores, and each of the 10 cores is responsible for a specific function, such as control, communication, or monitoring.

[0011] ROM2 is a non-volatile memory located outside the multicore MPU3 that stores multiple programs 20, for example, a first program 21 and a second program 22. Note that ROM2 may also be located inside the multicore MPU3, and its placement can be changed as appropriate.

[0012] The multi-core MPU3 is a processor equipped with multiple cores 10, for example, a first core 11 and a second core 12, and each core 10 executes a program 20. The program 20 can be various programs, such as applications or the OS (Operating System) that runs those applications.

[0013] The control circuit 4 is a circuit that controls the multi-core MPU 3. The control circuit 4 outputs a reset signal for starting up the multi-core MPU 3 to the multi-core MPU 3. The control circuit 4 is an output circuit that outputs an interrupt signal to the core 10 that executes one program 20 when one of the plurality of programs 20 in the ROM 2 is updated.

[0014] The control circuit 4 outputs a first interrupt signal to the first core 11 in the multi-core MPU 3. The first interrupt signal is an interrupt signal for updating the first program 21 operating on the first core 11 while continuing the execution of the second program 22 operating on the second core 12. The control circuit 4 outputs a second interrupt signal to the second core 12 in the multi-core MPU 3. The second interrupt signal is an interrupt signal for updating the second program 22 operating on the second core 12 while continuing the execution of the first program 21 operating on the first core 11.

[0015] The multi-core MPU 3, for example, resets all the cores 10 in response to the reset signal, loads the first program 21 stored in the ROM 2 into the first core 11, and loads the second program 22 stored in the ROM 2 into the second core 12. The first core 11 executes the loaded first program 21, and the second core 12 executes the loaded second program 22.

[0016] For example, assume that the first program 21 in the ROM 2 is updated due to version upgrade or the like, and the updated first program 21 is stored in the ROM 2. The control circuit 4 outputs a first interrupt signal to the first core 11 in the multi-core MPU 3 that is executing the first program 21 before the update. When the first core 11 detects the first interrupt signal, it reloads the updated first program 21 stored in the ROM 2. At this time, the second core 12 can continue to execute the second program 22 even during the update of the first program 21 by the first core 11.

[0017] For example, assume that the second program 22 in the ROM 2 is updated and the updated second program 22 is stored in the ROM 2. The control circuit 4 outputs a second interrupt signal to the second core 12 in the multi-core MPU 3 that is executing the second program 22 before the update. When the second core 12 detects the second interrupt signal, it reloads the updated second program 22 stored in the ROM 2. At this time, the first core 11 can continue to execute the first program 21 even while the second program 22 is being updated by the second core 12.

[0018] <Operation of the control device> FIG. 2 is a flowchart showing an example of the processing operations of the first core 11 related to the first update process and the second core 12 related to the second update process. Assume that the multi-core MPU 3 executes the first update process of the first core 11 and the second update process of the second core 12 in parallel.

[0019] The first update process is, for example, a process of updating the first program 21 of the first core 11. In FIG. 2, the first core 11 waits, for example, until the startup condition is satisfied, which is to wait until the device to be used becomes available in response to startup (step S10A). Note that the startup condition is, for example, a condition such as whether or not the initialization of the register is completed. After waiting for the startup condition in step S10A, the first core 11 loads the first program 21 before the update stored in the ROM 2 (step S11A). The first core 11 executes the normal operation of executing the loaded first program 21 (step S12A).

[0020] The first core 11 determines whether or not a first interrupt signal is detected during the execution of the normal operation (step S13A). When the first core 11 detects the first interrupt signal (step S13A: Yes), it determines that the first program 21 in the ROM 2 has been updated and waits until a predetermined startup condition is satisfied (step S14A). Note that the predetermined startup condition is, for example, a condition such as whether or not the time from the detection of the first interrupt signal until the reload of the first program 21 can be started has elapsed.

[0021] The first core 11 waits until the predetermined startup conditions are met, then reloads the updated first program 21 stored in ROM2 (step S15A), and proceeds to step S12A to begin normal operation of executing the updated first program 21.

[0022] Furthermore, if the first core 11 does not detect the first interrupt signal (step S13A: No), it proceeds to the processing in step S12A in order to continue normal operation of executing the first program 21.

[0023] The second update process is, for example, the process of updating the second program 22 of the second core 12. The second core 12 waits, for example, until it satisfies a startup condition, such as waiting until the device to be used becomes available (step S10B). The startup condition is, for example, whether or not the initialization of the registers is complete. After waiting for the startup condition in step S10B, the second core 12 loads the second program 22 stored in ROM2 before the update (step S11B). The second core 12 performs normal operation, executing the loaded second program 22 (step S12B).

[0024] The second core 12 determines whether or not it has detected a second interrupt signal during normal operation (step S13B). If the second core 12 has detected a second interrupt signal (step S13B: Yes), it determines that the second program 22 in the ROM 2 has been updated and waits until predetermined startup conditions are met (step S14B).

[0025] The second core 12 waits until predetermined startup conditions are met, then reloads the updated second program 22 stored in ROM2 (step S15B), and proceeds to step S12B to begin normal operation of executing the updated second program 22.

[0026] Furthermore, if the second core 12 does not detect a second interrupt signal (step S13B: No), it proceeds to step S12B in order to continue normal operation of executing the second program 22.

[0027] Figure 3 is a timing chart showing an example of the processing operations of the first core 11, the second core 12, and ROM 2 when the updated first program 21 is reloaded into the first core 11. Timing T0 shown in Figure 3 is the state in which the first program 21 and the second program 22 before the update are stored in ROM 2. Furthermore, timing T0 is the state in which the first core 11 continues its normal operation of executing the first program 21 in step S12A, and the second core 12 continues its normal operation of executing the second program 22 in step S12B.

[0028] Timing T1 is the timing when the first program 21 in ROM2 is updated. At timing T1, in step S12A, the first core 11 continues its normal operation of executing the first program 21 before the update, and in step S12B, the second core 12 continues its normal operation of executing the second program 22.

[0029] Timing T2 is the timing when the first core 11 detects the first interrupt signal, and after detecting the first interrupt signal, it is in a waiting state until the start condition is met in step S14A. During this time, the second core 12 continues its normal operation, executing the second program 22 in step S12B.

[0030] Timing T3 is the state in which the first core 11 waits until the startup conditions are met, and then in step S15A, the updated first program 21 in ROM2 is reloaded. At this time, the second core 12 continues its normal operation in step S12B, executing the second program 22.

[0031] At timing T4, the first core 11 is in a state of normal operation, having reloaded the updated first program 21 and continuing to execute the reloaded first program 21. Meanwhile, the second core 12 is in a state of normal operation, executing the second program 22 in step S12B.

[0032] In other words, the second core 12 within the multi-core MPU3 can continue executing the second program 22 even while updating the first program 21, which has been updated for the first core 11.

[0033] <Effects of Example 1> In Embodiment 1, the control circuit 4 within the control device 1 outputs a first interrupt signal to the first core 11 when the first program 21 in the ROM 2 is updated. When the first core 11 detects the first interrupt signal, it reloads the updated first program 21 from the ROM 2 and executes the reloaded first program 21. At this time, the first core 11 updates the first program 21, while the second core 12 continues to execute the second program 22. As a result, the control device 1 can update the first program 21 running on the first core 11 while continuing to execute the second program 22 running on the second core 12 within the same multi-core MPU 3.

[0034] Furthermore, the control circuit 4 outputs a second interrupt signal to the second core 12 when the second program 22 in ROM 2 is updated. When the second core 12 detects the second interrupt signal, it reloads the updated second program 22 from ROM 2 and executes the reloaded second program 22. At this time, while the second core 12 updates the second program 22, the first core 11 continues to execute the first program 21. As a result, the control device 1 can update the second program 22 running on the second core 12 while continuing to execute the first program 21 running on the first core 11 within the same multi-core MPU 3.

[0035] The control device 1 updates the first program 21 running on the first core 11 while continuing to execute the second program 22 running on the second core 12 within the same multi-core MPU 3. Furthermore, the control device 1 updates the second program 22 running on the second core 12 while continuing to execute the first program 21 running on the first core 11 within the same multi-core MPU 3. As a result, all programs (including the OS) running on the other cores 10 within the same multi-core MPU 3 can be updated without affecting the program 20 running on the core 10 within the multi-core MPU 3.

[0036] In a configuration where each core 10 of the multicore MPU3 is responsible for a specific function such as control, communication, and monitoring, the control device 1 can update a program 20 running on other cores 10 within the same multicore MPU3 without affecting the function that a particular core 10 is responsible for.

[0037] Since the control device 1 is required to operate continuously for a long period of time, it is conceivable that the program 20, including the OS, may need to be updated during operation for purposes such as defect correction or function enhancement. Even in such cases, the control device 1 can maintain partial functionality without shutting down the entire multi-core MPU 3. For example, while the program 20 of the core 10 responsible for control functions is being updated, the functionality of the core 10 responsible for monitoring functions can be maintained, allowing status monitoring to continue even during the update.

[0038] For the sake of explanation, the multi-core MPU3 is shown as having multiple cores, for example, two cores 10, but it is not limited to this; any two or more cores are acceptable, and can be changed as appropriate. Similarly, the program 20 in ROM2 is shown as two programs 20, but it is not limited to this, and can be changed as appropriate.

[0039] In Example 1, the control device 1 is shown as an example in which the control circuit 4 and the multi-core MPU 3 are separate components. However, the invention is not limited to this, and an embodiment of this form will be described below as Example 2.

[0040] <Example 2> Figure 4 is a block diagram showing an example of the control device 1A of Embodiment 2. Note that components identical to those in the control device 1 of Embodiment 1 are denoted by the same reference numerals, and the explanation of their overlapping components and operations is omitted. The difference between the control device 1A shown in Figure 4 and the control device 1 shown in Figure 1 is that the control device 1A has an FPGA (Field Programmable Gate Array) 5 that implements a multi-core MPU 3 and a control circuit 4.

[0041] <Effects of Example 2> The control device 1A of Embodiment 2 has an FPGA 5 that implements a multicore MPU 3 and a control circuit 4. As a result, the multicore MPU 3 and the control circuit 4 can be implemented on the same chip, which is more effective in reducing the number of components and wiring. Even if it is necessary to extend the functionality of the multicore MPU 3 in order to integrate multiple functions into a single multicore MPU 3, it becomes easy to add circuits for the additional functions.

[0042] In the control device 1 of Example 1, the example shown was one in which the control circuit 4 outputs interrupt signals to the first core 11 and the second core 12 in the multicore MPU 3. However, when a core 10 in the multicore MPU 3 detects an update to the program 20 in the ROM 2, the cores 10 may output interrupt signals to each other. Therefore, such an embodiment will be described below as Example 3.

[0043] <Example 3> Figure 5 is a block diagram showing an example of the control device 1B of Embodiment 3. Note that components identical to those in the control device 1 of Embodiment 1 are denoted by the same reference numerals, and the explanation of their overlapping components and operations is omitted. The difference between the control device 1B shown in Figure 5 and the control device 1 shown in Figure 1 is that the first core 11B and the second core 12B within the multi-core MPU 3B detect updates to the program 20 in the ROM 2, and the first core 11B and the second core 12B output interrupt signals to each other.

[0044] The control device 1B shown in Figure 5 includes a ROM 2, a multicore MPU 3B, and a control circuit 4B. The multicore MPU 3B has multiple cores, for example, two cores 10, namely a first core 11B and a second core 12B.

[0045] The second core 12B outputs a first interrupt signal to the first core 11B when the first program 21 in ROM2 is updated. When the first core 11B detects the first interrupt signal, it reloads the updated first program 21 stored in ROM2. At this time, the second core 12B can continue executing the second program 22 even while the first core 11B is updating the first program 21.

[0046] The first core 11B outputs a second interrupt signal to the second core 12B when the second program 22 in ROM 2 is updated. When the second core 12B detects the second interrupt signal, it reloads the updated second program 22 stored in ROM 2. In this case, the first core 11B can continue executing the first program 21 even while the second core 12B is updating the second program 22.

[0047] <Effects of Example 3> In Embodiment 3, the second core 12B in the control device 1B outputs a first interrupt signal to the first core 11B when the first program 21 in the ROM 2 is updated. When the first core 11B detects the first interrupt signal, it reloads the updated first program 21 from the ROM 2 and executes the reloaded first program 21. At this time, the first core 11B updates the first program 21, while the second core 12B continues to execute the second program 22. As a result, the control device 1B can update the first program 21 running on the first core 11B while continuing to execute the second program 22 running on the second core 12B in the same multi-core MPU 3B.

[0048] Furthermore, the first core 11B outputs a second interrupt signal to the second core 12B when the second program 22 in ROM 2 is updated. When the second core 12B detects the second interrupt signal, it reloads the updated second program 22 from ROM 2 and executes the reloaded second program 22. At this time, the second core 12B updates the second program 22, while the first core 11B continues to execute the first program 21. As a result, the control device 1B can update the second program 22 running on the second core 12B while continuing to execute the first program 21 running on the first core 11B within the same multi-core MPU 3B.

[0049] The control device 1B can update all programs (including the OS) running on other cores 10 within the same multicore MPU 3B without affecting the program 20 running on core 10 within the same multicore MPU 3B.

[0050] In the control device 1 of Example 1, the example shows the case where program 20 is executed for each core 10 in the multi-core MPU 3. However, it is not limited to this, and program 20 may be executed for each of multiple core groups within the same multi-core MPU 3, and such an embodiment will be described below as Example 4.

[0051] <Example 4> Figure 6 is a block diagram showing an example of the control device 1C of Embodiment 4. Note that components identical to those in the control device 1 of Embodiment 1 are denoted by the same reference numerals, and the explanation of their overlapping components and operations is omitted. The control device 1C shown in Figure 6 includes a ROM 2, a multi-core MPU 3C, and a control circuit 4C. The ROM 2 stores the first program 21 and the second program 22. The multi-core MPU 3C has, for example, four first cores 11C, a second core 12C, a third core 13C, and a fourth core 14C. The first cores 11C and 2 cores 12C form the first core group, and the third cores 13C and 4 cores 14C form the second core group.

[0052] The first core 11C and the second core 12C in the first core group load the first program 21 stored in ROM2 and execute the loaded first program 21. The third core 13C and the fourth core 14C in the second core group load the second program 22 stored in ROM2 and execute the loaded second program 22.

[0053] For example, suppose the first program 21 in ROM2 is updated, and the updated first program 21 is stored in ROM2. In this case, the first core 11C and the second core 12C of the multicore MPU3C that is executing the first program 21 are the cores to be updated. The control circuit 4C outputs a first interrupt signal to the first core 11C and the second core 12C of the multicore MPU3C that is executing the first program 21. When the first core 11C and the second core 12C detect the first interrupt signal, they reload the updated first program 21 stored in ROM2. In this case, the third core 13C and the fourth core 14C can continue executing the second program 22 even while the first core 11C and the second core 12C are updating the first program 21.

[0054] For example, suppose the second program 22 in ROM2 is updated, and the updated second program 22 is stored in ROM2. In this case, the third core 13C and the fourth core 14C of the multicore MPU3C that are executing the second program 22 become the cores to be updated. The control circuit 4C outputs a second interrupt signal to the third core 13C and the fourth core 14C of the multicore MPU3C that are executing the second program 22. When the third core 13C and the fourth core 14C detect the second interrupt signal, they reload the updated second program 22 stored in ROM2. In this case, the first core 11C and the second core 12C can continue executing the first program 21 even while the third core 13C and the fourth core 14C are updating the second program 22.

[0055] <Operation of the control device> Figure 7 is a flowchart showing an example of the processing operation of the first core group involved in the first core group update process and the second core group involved in the second core group update process. The multicore MPU3C is assumed to execute the first core group update process for the first core group and the second core group update process for the second core group in parallel.

[0056] The first core group update process is a process that updates the first program 21 of the first core 11C and the second core 12C within the first core group. In Figure 7, the first core 11C and the second core 12C within the first core group wait, for example, until the startup conditions are met so that the devices to be used become available (step S10A1). The startup conditions are, for example, the completion of register initialization. After waiting until the startup conditions in step S10A1 are met, the first core 11C and the second core 12C load the first program 21 stored in ROM2 before the update (step S11A1). The first core 11C and the second core 12C perform normal operations to execute the loaded first program 21 (step S12A1).

[0057] The first core 11C and the second core 12C determine whether or not they have detected the first interrupt signal during normal operation (step S13A1). If the first core 11C and the second core 12C detect the first interrupt signal (step S13A1: Yes), they determine that the first program 21 in ROM2 has been updated and wait until predetermined startup conditions are met (step S14A1).

[0058] The first core 11C and the second core 12C wait until predetermined startup conditions are met, then reload the updated first program 21 stored in ROM2 (step S15A1). Then, the first core 11C and the second core 12C proceed to the process of step S12A1 in order to start normal operation of executing the updated first program 21.

[0059] Furthermore, if the first core 11C and the second core 12C do not detect the first interrupt signal (step S13A1: No), they proceed to the process of step S12A1 in order to perform the normal operation of executing the first program 21.

[0060] The second core group update process is a process that updates the second program 22 of the third core 13C and the fourth core 14C within the second core group. The third core 13C and the fourth core 14C within the second core group wait until a startup condition is met, for example, when a device to be used becomes available (step S10B1). The startup condition is, for example, when the initialization of registers is completed. After waiting until the startup condition in step S10B1 is met, the third core 13C and the fourth core 14C load the second program 22 stored in ROM2 before the update (step S11B1). The third core 13C and the fourth core 14C perform normal operation to execute the loaded second program 22 (step S12B1).

[0061] The third core 13C and the fourth core 14C determine whether or not they have detected the second interrupt signal during normal operation (step S13B1). If the third core 13C and the fourth core 14C detect the second interrupt signal (step S13B1: Yes), they determine that the second program 22 in ROM2 has been updated and wait until predetermined startup conditions are met (step S14B1).

[0062] The third core 13C and the fourth core 14C wait until predetermined startup conditions are met, then reload the updated second program 22 stored in ROM2 (step S15B1). Then, the third core 13C and the fourth core 14C proceed to the process of step S12B1 in order to start normal operation of executing the updated second program 22.

[0063] Furthermore, if the third core 13C and the fourth core 14C do not detect the second interrupt signal (step S13B1: No), they proceed to the process of step S12B1 in order to perform the normal operation of executing the second program 22.

[0064] In other words, the third core 13C and the fourth core 14C within the second core group of the multi-core MPU3C can continue executing the second program 22 even while the first program 21 is being updated for the first core 11C and the second core 12C within the first core group.

[0065] <Effects of Example 4> In Embodiment 4, the control circuit 4C within the control device 1C outputs a first interrupt signal to the first core group when the first program 21 in the ROM 2 is updated. When the first core group detects the first interrupt signal, it reloads the updated first program 21 from the ROM 2 and executes the reloaded first program 21. At this time, the first core group updates the first program 21, while the second core group continues to execute the second program 22. As a result, the control device 1C can update the first program 21 running on the first core group while continuing to execute the second program 22 running on the second core group within the same multi-core MPU 3C.

[0066] Furthermore, the control circuit 4C outputs a second interrupt signal to the second core group when the second program 22 in ROM2 is updated. When the second core group detects the second interrupt signal, it reloads the updated second program 22 from ROM2 and executes the reloaded second program 22. At this time, the second core group updates the second program 22, while the first core group continues to execute the first program 21. As a result, the control device 1C can update the second program 22 running on the second core group while continuing to execute the first program 21 running on the first core group within the same multi-core MPU 3C.

[0067] In Example 4, the control device 1C illustrates a case where, when the first core 11C and the second core 12C in the first core group detect a first interrupt signal, the first program 21 is simultaneously reloaded from ROM 2 to the first core 11C and the second core 12C. However, the invention is not limited to this, and the first program 21 in ROM 2 may be reloaded alternately by the first core 11C and the second core 12C in the first core group. This embodiment will be described below as Example 5.

[0068] <Example 5> Figure 8 is a block diagram showing an example of the control device 1D of Embodiment 5. Note that identical components to those of the control device 1C of Embodiment 4 are denoted by the same reference numerals, and the explanation of overlapping components and operations is omitted. The difference between the control device 1D shown in Figure 8 and the control device 1C shown in Figure 6 is that, within the first core group, multiple cores 10 alternately switch between operating mode and standby mode. Operating mode is the mode in which the core 10 executes program 20. Standby mode is the mode in which the core 10 stops program execution. Furthermore, the first core 11D and the second core 12D in the multicore MPU3D detect updates to the first program 21 in ROM2, and the first core 11D and the second core 12D output a first interrupt signal to each other. The third core 13D and the fourth core 14D in the multicore MPU3D detect updates to the second program 22 in ROM2, and the third core 13D and the fourth core 14D output a second interrupt signal to each other.

[0069] The first core group within the multicore MPU3D comprises a first core 11D and a second core 12D. When the first core 11D is set to operational mode, the second core 12D is set to standby mode. Conversely, when the first core 11D is set to standby mode, the second core 12D is set to operational mode.

[0070] The second core group within the multi-core MPU3D includes a third core 13D and a fourth core 14D. When the third core 13D is set to operational mode, the fourth core 14D is set to standby mode. Conversely, when the third core 13D is set to standby mode, the fourth core 14D is set to operational mode.

[0071] When the first core 11D in the first core group detects an update to the first program 21 in ROM2 while in operating mode, it outputs a first interrupt signal to the second core 12D. When the second core 12D detects the first interrupt signal from the first core 11D while in standby mode, it reloads the updated first program 21 stored in ROM2 and sets itself to operating mode.

[0072] After being set to operating mode, the second core 12D outputs a first interrupt signal to the first core 11D. If the first core 11D detects the first interrupt signal from the second core 12D while in standby mode, it reloads the updated first program 21 stored in ROM2. In other words, the first group of cores can continue executing the first program 21 in the operating mode core 10 while updating the first program 21 in the standby mode core 10 among multiple cores 10 of the same core group.

[0073] If the third core 13D within the second core group detects an update to the second program 22 in ROM2 while in operating mode, it outputs a second interrupt signal to the fourth core 14D. If the fourth core 14D detects the second interrupt signal from the third core 13D while in standby mode, it reloads the updated second program 22 stored in ROM2 and sets itself to operating mode.

[0074] After being set to operating mode, the fourth core 14D outputs a second interrupt signal to the third core 13D. If the third core 13D detects the second interrupt signal from the fourth core 14D while in standby mode, it reloads the updated second program 22 stored in ROM2. In other words, the second group of cores can continue executing the second program 22 in the core 10 in operating mode while updating the second program 22 in the core 10 in standby mode among multiple cores 10 in the same core group.

[0075] <Operation of the control device> Figure 9 is a flowchart showing an example of the processing operation of the first core 11D and the second core 12D within the first core group involved in the third update process. Although Figure 9 illustrates the case of the first core group, the same processing is performed for the third core 13D and the fourth core 14D within the second core group.

[0076] The first core 11D in the first core group is set to an operating mode for executing the first program 21 (step S21A), and the second core 12D in the first core group is set to a standby mode (step S21B).

[0077] If the first core 11D detects an update to the first program 21 in ROM2 during operation mode, it outputs a first interrupt signal to the second core 12D (step S22). If the second core 12D detects the first interrupt signal from the first core 11D (step S23), it reloads the updated first program 21 stored in ROM2 (step S24).

[0078] The second core 12D performs a mode switch when the first program 21 is reloaded (step S25B). The second core 12D switches from standby mode to operating mode in response to the mode switch (step S26B). The first core 11D switches from operating mode to standby mode in response to the mode switch from the second core 12D (step S26A).

[0079] After switching to operating mode, the second core 12D outputs a first interrupt signal to the first core 11D while maintaining the operating mode (step S27). If the first core 11D detects the first interrupt signal from the second core 12D while maintaining standby mode (step S28), it reloads the updated first program 21 stored in ROM2 (step S29).

[0080] Then, while the first core 11D of the first core group is in operation mode and the second core 12D of the first core group is in standby mode, if the first core 11D detects an update to the first program 21 in ROM2, it outputs a first interrupt signal to the second core 12D. If the second core 12D detects the first interrupt signal while in operation mode, it reloads the updated first program 21. The second core 12D outputs a first interrupt signal to the first core 11D. Then, if the first core 11D detects the first interrupt signal while in standby mode, it reloads the updated first program 21.

[0081] In other words, the control device 1D outputs a first interrupt signal to the second core 12D while the first core 11D is in operation mode, and reloads the updated first program 21 into the second core 12D. After reloading the updated first program 21, the second core 12D sets itself to operation mode and outputs a first interrupt signal to the first core 11D. When the first core 11D detects the first interrupt signal from the second core 12D, it reloads the updated first program 21.

[0082] <Effects of Example 5> The control device 1D of Embodiment 5 alternately reloads the updated first program 21 stored in ROM2 to the first core 11D and the second core 12D within the first core group by alternately switching between them. As a result, the first core group can continue executing the first program 21 running on the core 10 in operation mode while updating the first program 21 running on the core 10 in standby mode among multiple cores 10 in the same core group.

[0083] The control device 1D alternately switches between the third core 13D and the fourth core 14D within the second core group, thereby alternately reloading the updated second program 22 stored in ROM2 to the third core 13D and the fourth core 14D. As a result, the second core group can continue executing the second program 22 running on the core 10 in operation mode while updating the second program 22 running on the core 10 in standby mode among multiple cores 10 in the same core group.

[0084] The control device 1D alternately updates two programs 20 within the same core group of the multi-core MPU 3D. As a result, while updating the program 20 running on the core 10 in standby mode among multiple cores 10 within the same core group, the execution of the program running on the core 10 in operational mode can continue.

[0085] In this example, the control device 1D outputs a first interrupt signal to the first core 11D and the second core 12D when the first core 11D and the second core 12D detect an update to the first program 21 in the ROM 2. However, this is not the only example, and can be modified as appropriate. For example, the control circuit 4D in the control device 1D may output a first interrupt signal to the second core 12D, which is in standby mode, when it detects an update to the first program 21 in the ROM 2. In this case, when the second core 12D detects the first interrupt signal, it reloads the first program 21, switches from standby mode to operation mode, and notifies the control circuit 4D of the completion of the reload. Then, when the control circuit 4D detects the completion of the reload from the second core 12D, it outputs a first interrupt signal to the first core 11D, which has been switched to standby mode. Furthermore, the first core 11D may reload the first program 21 from ROM 2 in response to a first interrupt signal from the control circuit 4D, and this can be modified as appropriate.

[0086] Control devices 1, 1A, 1B, 1C, and 1D are, for example, control devices such as DCS (Distributed Control System) and SIS (Safety Instrumented System). [Explanation of Symbols]

[0087] 1. Control device 2 ROM 3 Multi-core MPU 4. Control circuits 10 cores 11. The First Core 12. The second core 20 Programs 21. Program 1 22. Second Program

Claims

1. ROM (Read Only Memory) that stores the program, A processor having multiple cores that load the program from the ROM and execute the program, The ROM includes an output circuit that outputs an interrupt signal to the core executing the program when one of the multiple programs in the ROM is updated. The aforementioned core is A control device characterized by reloading the updated program stored in the ROM when the aforementioned interrupt signal is detected.

2. The output circuit described above is The control device according to claim 1, characterized in that it is a control circuit for controlling the processor that outputs an interrupt signal to the core executing a program when one of the multiple programs in the ROM is updated.

3. The output circuit described above is The control device according to claim 1, characterized in that it is another core in the processor that outputs an interrupt signal to the core executing a program when one of the multiple programs in the ROM is updated.

4. The output circuit described above is When one of the multiple programs in the ROM is updated, an interrupt signal is output to each of the multiple cores that execute the updated program. Each of the cores to be updated is: The control device according to claim 1, characterized in that when the interrupt signal is detected, the updated program stored in the ROM is reloaded.

5. The aforementioned processor, It has a first core and a second core that run the same program, The first core is, When the system is in a waiting mode, waiting for the second core to execute its program, it sets an operating mode to execute the program. The second core is, The operating mode is set when the first core is in standby mode. The first core is, When the interrupt signal is detected during the aforementioned operating mode, the interrupt signal is output to the second core. The second core is, When the interrupt signal from the first core is detected, the updated program is reloaded from the ROM, the system switches from the standby mode to the operating mode, and the interrupt signal is output to the first core. The first core is, The control device according to claim 1, characterized in that when the interrupt signal is detected during the standby mode, the updated program is reloaded from the ROM.

6. A control device having a ROM (Read Only Memory) that stores a program, and a processor with multiple cores that load the program from the ROM and execute the program, When one of the multiple programs in the ROM is updated, an interrupt signal is output to the core that executes that program. When the core detects the interrupt signal, it reloads the updated program stored in the ROM. An update method characterized by performing a process.

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