Semiconductor devices and electronic equipment

Abstract

This technology provides ESD resistance while offering advantages in miniaturizing semiconductor devices. [Solution] The semiconductor device comprises a semiconductor substrate, a wiring structure disposed on the semiconductor substrate, and electronic components. The wiring structure includes a pad region including pads and a circuit region, each of which includes a plurality of wiring layers, an interlayer insulating film disposed between the plurality of wiring layers, and via plugs connecting the plurality of wiring layers to each other. The electronic components are active elements, are electrically connected to the pads, and are located in the circuit region and above the upper surface of the semiconductor substrate.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and an electronic device.

Background Art

[0002] A semiconductor device includes an ESD (Electro-Static Discharge) protection circuit for protecting an electronic circuit disposed therein from noises such as ESD discharge.

[0003] Patent Document 1 describes an ESD protection circuit disposed between two bonding pads. In the ESD protection circuit described in Patent Document 1, a resistor R1 and a capacitor C1 are connected in series between a power supply voltage VCC and a reference potential VSS, and an input part of an inverter Iv1 is connected to a connection part between the resistor R1 and the capacitor C1. The inverter Iv1 has a configuration in which a transistor T1 of a P-channel MOS and a transistor T2 of an N-channel MOS are connected in series between the power supply voltage VCC and the reference potential VSS. A gate of a clamping transistor T3 made of an N-channel MOS is connected to an output part of the inverter Iv1. One end of the source / drain of the transistor T3 is connected to the power supply voltage VCC, and the other end of the source / drain of the transistor T3 is connected to the reference potential VSS. The gate of the transistor T3 is connected to the reference potential VSS via a resistor R2, and a parasitic diode DP is formed at a junction between the well region and the source of the transistor T3. Also, a diode D1 is connected between the power supply voltage VCC and the reference potential VSS. Generally, an ESD protection circuit incorporated in a semiconductor device has a complicated configuration and may occupy a large area in the semiconductor device. Therefore, the ESD protection circuit is a factor that causes the semiconductor device to be enlarged.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0005] The present invention aims to provide a technology that offers advantages in miniaturizing semiconductor devices while providing ESD resistance. [Means for solving the problem]

[0006] A first aspect of the present invention relates to a semiconductor device having a semiconductor substrate, a wiring structure disposed on the semiconductor substrate, and an electronic component, wherein the wiring structure includes a pad region including pads and a circuit region, each of the pad region and the circuit region including a plurality of wiring layers, an interlayer insulating film disposed between the plurality of wiring layers, and via plugs connecting the plurality of wiring layers to each other, the electronic component is an active element, the electronic component is electrically connected to the pads, and the electronic component is disposed in the circuit region and above the upper surface of the semiconductor substrate.

[0007] A second aspect of the present invention relates to an electronic device, wherein the electronic device comprises a semiconductor device relating to the first aspect. [Effects of the Invention]

[0008] According to the present invention, a technology is provided that offers advantages in miniaturizing semiconductor devices while providing ESD resistance. [Brief explanation of the drawing]

[0009] [Figure 1] A schematic plan view showing the configuration of a semiconductor device according to one embodiment. [Figure 2] A schematic cross-sectional view showing the configuration of a semiconductor device according to one embodiment. [Figure 3] A diagram illustrating an equivalent circuit of a part of a semiconductor device according to one embodiment. [Figure 4] (a) is a diagram showing the CAD layout of a conventional ESD protection circuit, and (b) is a diagram schematically showing the CAD layout of the electronic components of this embodiment. [Figure 5] This graph shows an estimated relationship between the area occupied by protective elements and HBM (Human Body Model) resistance. [Figure 6] Cross-sectional view of a semiconductor device incorporating a conventional ESD protection circuit (ESDC). [Figure 7] Plan view of a semiconductor device incorporating a conventional ESD protection circuit (ESDC). [Figure 8] Cross-sectional view of the semiconductor device of the electronic component EC of this embodiment. [Figure 9] A plan view of the semiconductor device of the electronic component EC of this embodiment. [Figure 10] (a) is a schematic plan view of the electronic component of the first embodiment, (b) is a schematic cross-sectional view of the electronic component of the first embodiment, and (c) is a schematic cross-sectional view of a modified example of the electronic component of the first embodiment. [Figure 11] (a) is a schematic plan view of the electronic component of the second embodiment, (b) is a schematic cross-sectional view of the electronic component of the second embodiment, and (c) is a schematic cross-sectional view of a modified example of the electronic component of the second embodiment. [Figure 12] A schematic plan view of the electronic component of the third embodiment. [Figure 13] (a) is a schematic cross-sectional view of the electronic component of the third embodiment, and (b) is a schematic cross-sectional view of the electronic component of the third embodiment. [Figure 14] A schematic plan view of the electronic component of the fourth embodiment. [Figure 15] (a) is a schematic cross-sectional view of the electronic component of the fourth embodiment, and (b) is a schematic cross-sectional view of the electronic component of the fourth embodiment. [Figure 16] (a) is a schematic plan view of the electronic component of the fifth embodiment, (b) is a schematic cross-sectional view of the electronic component of the fifth embodiment, and (c) is a schematic cross-sectional view of a modified example of the electronic component of the fifth embodiment. [Figure 17] A schematic plan view of the electronic component according to the sixth embodiment. [Figure 18] (a) is a schematic cross-sectional view of the electronic component of the sixth embodiment, and (b) is a schematic cross-sectional view of the electronic component of the sixth embodiment. [Figure 19](a) is a schematic plan view of an electronic component according to the seventh embodiment, and (b) is a schematic cross-sectional view of a modified example of the electronic component according to the seventh embodiment. [Figure 20] Schematic cross-sectional view of an electronic component according to the eighth embodiment. [Figure 21] Schematic cross-sectional view of an electronic component according to the ninth embodiment. [Figure 22] (a) is a schematic plan view of an electronic component according to the tenth embodiment, and (b) is a schematic cross-sectional view of a modified example of the electronic component according to the tenth embodiment. [Figure 23] (a) is a schematic plan view of an electronic component according to the eleventh embodiment, and (b) is a schematic cross-sectional view of a modified example of the electronic component according to the eleventh embodiment. [Figure 24] Schematic cross-sectional view of an electronic component according to the twelfth embodiment. [Figure 25] Schematic cross-sectional view of an electronic component according to the thirteenth embodiment. [Figure 26] Diagram illustrating an electronic device according to an application example.

Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the invention according to the claims, and not all combinations of the features described in the embodiments are essential to the invention. Two or more of the features described in the embodiments may be arbitrarily combined. Also, the same or similar configurations are assigned the same reference numerals, and duplicate descriptions are omitted.

[0011] Figures 1 and 2 are schematic plan and cross-sectional views, respectively, showing the configuration of a semiconductor device 1 according to one embodiment. The semiconductor device 1 may include a semiconductor chip 12 having one or more electronic components EC and one or more pads 16. The semiconductor device 1 may also include one or more lead frames 14 and a package 10 that encloses the semiconductor chip 12. Each pad 16 of the semiconductor chip 12 and its corresponding lead frame 14 may be electrically and physically connected by bonding wires 18. When forming the bonding wires 18, bonding balls 17 may be formed on the pads 16, and the pads 16 and bonding wires 18 may be electrically and physically connected via the bonding balls 17. The semiconductor chip 12 may have a pad region including the pads 16 and a circuit region. Various circuit blocks, such as a power supply circuit, arithmetic circuit, ADC (analog-to-digital converter), memory circuit, audio processor, DAC (digital-to-analog converter), video processor, bus, clock circuit, etc., may be arranged in the circuit region.

[0012] Figure 3 illustrates an equivalent circuit of a portion of a semiconductor device 1 according to one embodiment. The semiconductor device 1 may include, for example, one or more power pads VDD, one or more ground pads GND, one or more input pads IN1, IN2, one or more output pads OUT1, OUT2, and one or more circuit blocks CB. Although not shown, the semiconductor device 1 may also include one or more input / output pads. Power pads, ground pads, input pads, output pads, and input / output pads may be collectively referred to as pads. Power pad VDD may be electrically connected to power line VDDL. Power line VDDL may be supplied with a voltage (a voltage converted by the power circuit) supplied from power pad VDD via a power circuit.

[0013] Two or more pads may be electrically connected to each other by a path including an electronic component EC. Alternatively, two or more pads may be electrically connected to each other by a path including an electronic component EC and a resistive element R. In other words, an electronic component EC may be electrically connected to a pad by a wiring pattern WP. Alternatively, an electronic component EC may be electrically connected to a pad via a wiring pattern WP and a resistive element R. An electronic component EC may be, for example, a varistor having a molybdenum oxide film, or a varistor having another resistive film. Alternatively, an electronic component EC may be, for example, an active element having a molybdenum oxide film, or an active element having another semiconductor film. Such an active element may be an active element other than a varistor, for example, a transistor (e.g., a bipolar transistor, a MOS transistor, a junction field-effect transistor (JFET)), or a diode (e.g., a general-purpose diode, a PN junction diode, a PIN diode, a Schottky diode).

[0014] Conventionally, semiconductor devices have protected their internal circuits from surge currents using ESD protection circuits that include diodes containing PN junctions formed in the semiconductor substrate. However, these ESD protection circuits, including diodes containing PN junctions, occupy a considerably large area, contributing to the increased size of the semiconductor device. In this embodiment, the semiconductor device 1 is miniaturized by incorporating an electronic component EC as a protection element. The electronic component EC can have a structure selected from various structures, as will be described later.

[0015] Figure 4(a) schematically shows a CAD layout of a conventional ESD protection circuit ESDC incorporated into a semiconductor device. The ESD protection circuit ESDC can be electrically connected to the pad BP by a wiring pattern WP. Figure 4(b) schematically shows a CAD layout of a varistor as an electronic component EC in this embodiment, incorporated into a semiconductor device. The EC can be electrically connected to the pad BP by a wiring pattern WP.

[0016] Figure 5 is a graph showing the approximate relationship between the area occupied by the protective element and HBM (Human Body Model) resistance. The solid line shows the case where the electrical component EC of this embodiment is applied as the protective element, and the dotted line shows the case where the conventional ESD protection circuit ESDC, schematically shown in Figure 4(a), is applied as the protective element. According to this embodiment, excellent HBM resistance can be obtained while reducing the area of ​​the protective element.

[0017] Figures 6 and 7 show a cross-sectional view and a plan view, respectively, of a semiconductor device incorporating a conventional ESD protection circuit ESDC. In Figure 6, the surge current path in a conventional semiconductor device is schematically shown by thick arrows. The semiconductor device has a wiring structure WS on a semiconductor substrate SS. The semiconductor device also has an ESD protection circuit ESDC positioned adjacent to a pad region PR, which includes a pad BP to which a bonding wire BW is connected, and the pad BP and the ESD protection circuit ESDC are connected via a wiring pattern WP. The ESD protection circuit ESDC includes a PN junction formed in the semiconductor substrate SS.

[0018] Figures 8 and 9 show a cross-sectional view and a plan view of the semiconductor device 1 of this embodiment, in which an electronic component EC is incorporated, respectively. In Figure 8, the surge current path in the semiconductor device 1 of this embodiment is schematically shown by a thick arrow. The semiconductor device 1 has a wiring structure WS on a semiconductor substrate SS. The wiring structure WS includes a pad region PR including a pad BP and a circuit region CR, and each of the pad region PR and the circuit region CR may include a plurality of wiring layers WL, an interlayer insulating film ILIF disposed between the plurality of wiring layers WL, and via plugs VP that connect the plurality of wiring layers WL to each other. In this embodiment, the electronic component EC as a protective element is located in the circuit region CR and above the upper surface of the semiconductor substrate SS. On the other hand, conventional protective elements include PN junctions formed on the semiconductor substrate SS. A bonding wire BW may be electrically and physically connected to the upper surface of the pad BP via a bonding ball BB.

[0019] The electronic component EC may be positioned in a location adjacent to the pad region PR within the circuit region CR. Furthermore, the electronic component EC may be electrically connected to the pad BP by a wiring pattern WP. Alternatively, the electronic component EC may be electrically connected to the pad BP via a resistive element in addition to the wiring pattern WP. As schematically shown in Figure 1, the wiring structure WS of the semiconductor device 1 may have a plurality of pads 16 (including 16-1 and 16-2). The wiring structure WS may, for example, have a pad region PR-1 including a first pad 16-1 and a pad region PR-2 including a second pad 16-2, and the electronic component EC may be positioned between the first pad region PR-1 and the second pad region PR-2. The circuit region CR may include a transistor Tr located beneath the electronic component EC. This is advantageous for increasing the circuit size that can be incorporated into the semiconductor device 1.

[0020] As illustrated in Figure 8, the electronic component EC may have an electrode containing a conductive film located on the furthest wiring layer WLF, which is the furthest from the semiconductor substrate SS among a plurality of wiring layers WL. In other words, as illustrated in Figure 8, the electronic component EC may include an electrode containing a conductive film located on at least two of the wiring layers WL among a plurality of wiring layers WL.

[0021] The following describes several embodiments of electronic components EC that may be incorporated into semiconductor device 1. However, these are merely examples, and electronic components EC may have other structures.

[0022] Figure 10(a) schematically shows a plan view of the electronic component EC of the first embodiment. Figure 10(b) schematically shows a cross-sectional view of the electronic component EC of the first embodiment. The electronic component EC of the first embodiment is configured as a varistor and may have a resistive film 110, a first electrode 121 positioned in a first region R1 of the main surface 111 (here, the top surface) of the resistive film 110, and a second electrode 122 positioned in a second region R2 of the main surface 111 of the resistive film 110. The second region R2 is separated from the first region R1. The first electrode 121 and the second electrode 122 may consist of a conductive film positioned in one of a plurality of wiring layers WL, for example, the furthest wiring layer WLF, which is furthest from the semiconductor substrate SS. The first electrode 121 and the second electrode 122 may be made of, for example, a metal (e.g., aluminum) or an alloy (e.g., aluminum with tungsten or copper added). The resistive film 110 may be a molybdenum oxide film, but it may also be a film made of other materials. The first electrode 121 and the second electrode 122 may have a circular, elliptical, or rounded shape. Alternatively, the first electrode 121 and the second electrode 122 may have a rectangular shape with rounded corners. Alternatively, the first electrode 121 and the second electrode 122 may have a square or polygonal shape with rounded corners, or they may have other shapes.

[0023] Figure 10(c) schematically shows a cross-sectional view of a modified electronic component EC of the first embodiment. The modified electronic component EC of the first embodiment may have a resistive film 110, a first electrode 121 positioned in a first region R1 of the main surface 112 (here, the bottom surface) of the resistive film 110, and a second electrode 122 positioned in a second region R2 of the main surface 112 of the resistive film 110. The second region R2 is separated from the first region R1. The first electrode 121 and the second electrode 122 may consist of a conductive film positioned in any one of a plurality of wiring layers WL.

[0024] Figure 11(a) schematically shows a plan view of the electronic component EC of the second embodiment. Figure 11(b) schematically shows a cross-sectional view of the electronic component EC of the second embodiment. Matters not mentioned with respect to the electronic component EC of the second embodiment (including modifications) can be described in the preceding text. The electronic component EC of the second embodiment is configured as a varistor and may have an interlayer 130 disposed between the main surface 111 of the resistive film 110 and the first electrode 121, and between the main surface 111 of the resistive film 110 and the second electrode 122. The interlayer 130 may be, for example, a silicon film containing impurities (e.g., a polysilicon film or an amorphous silicon film). The interlayer 130 is advantageous in providing ohmic contact between the resistive film 110, which may be composed of a molybdenum oxide film or the like, and the first electrode 121 and the second electrode 122.

[0025] Figure 11(c) schematically shows a cross-sectional view of a modified electronic component EC of the second embodiment. The modified electronic component EC of the second embodiment may have an interlayer 130 disposed between the main surface 112 of the resistive film 110 and the first electrode 121, and between the main surface 112 of the resistive film 110 and the second electrode 122. The interlayer 130 may be, for example, a silicon film containing impurities (for example, a polysilicon film or an amorphous silicon film). The interlayer 130 is advantageous in providing ohmic contact between the resistive film 110, which may be composed of a molybdenum oxide film or the like, and the first electrode 121 and the second electrode 122.

[0026] Figure 12 schematically shows a plan view of the electronic component EC of the third embodiment. Figure 13(a) schematically shows a cross-sectional view of the electronic component EC of the third embodiment. Matters not mentioned with respect to the electronic component EC of the third embodiment (including modifications) can be described in the preceding text. The electronic component EC of the third embodiment is configured as a varistor and may have a resistive film 110, a first electrode 121 disposed in a first region of the main surface 111 (here, the top surface) of the resistive film 110, and a second electrode 122 disposed in a second region of the main surface 111 of the resistive film 110. In the electronic component EC of the third embodiment, each of the first electrode 121 and the second electrode 122 includes at least two conductive films 201, 202 disposed in each of at least two wiring layers WL of a plurality of wiring layers WL. The electronic component EC of the third embodiment may further include a plug VP that electrically connects the at least two conductive films 201, 202. The two conductive films 201, 202 may include a first conductive film 201 containing a first pattern P1 and a second conductive film 202 containing a plurality of second conductive patterns P2 smaller than the first pattern P1. Such a configuration is advantageous for adjusting the varistor voltage of an electronic component EC configured as a varistor. The varistor voltage can be adjusted, for example, by adjusting the area of ​​the second conductive patterns P2.

[0027] Figure 13(b) schematically shows a cross-sectional view of a modified electronic component EC of the third embodiment. The modified electronic component EC of the third embodiment may have a resistive film 110, a first electrode 121 disposed in a first region of the main surface 112 (here, the lower surface) of the resistive film 110, and a second electrode 122 disposed in a second region of the main surface 112 of the resistive film 110.

[0028] Figure 14 schematically shows a plan view of the electronic component EC of the fourth embodiment. Figure 15(a) schematically shows a cross-sectional view of the electronic component EC of the fourth embodiment. Matters not mentioned with respect to the electronic component EC of the fourth embodiment (including modifications) can be described in the preceding text. The electronic component EC of the fourth embodiment is configured as a varistor and may have an interlayer film 130 disposed between the main surface 111 (here, the top surface) of the resistive film 110 and the first electrode 121, and between the main surface 111 of the resistive film 110 and the second electrode 122.

[0029] Figure 15(b) schematically shows a cross-sectional view of a modified electronic component EC of the fourth embodiment. The modified electronic component EC of the second embodiment may have an interlayer 130 disposed between the main surface 112 (here, the bottom surface) of the resistive film 110 and the first electrode 121, and between the resistive film 110 and the second electrode 122.

[0030] Figure 16(a) schematically shows a plan view of the electronic component EC of the fifth embodiment. Figure 16(b) schematically shows a cross-sectional view of the electronic component EC of the fifth embodiment. Matters not mentioned with respect to the electronic component EC of the fifth embodiment (including modifications) can be described in the preceding explanation. The electronic component EC of the fifth embodiment is configured as a varistor and may have a first electrode 121, a resistive film 110 disposed on the first electrode 121, and a second electrode 122 disposed on the resistive film 110. In other words, the electronic component EC of the fifth embodiment may have a first electrode 121 disposed on one main surface 112 side of the resistive film 110 and a second electrode 122 disposed on the other main surface 111 side of the resistive film 110. In the first to fourth embodiments, a current path is formed so that current flows in the direction along the main surface of the resistive film 110, whereas in the fifth embodiment, a current path is formed so that current flows in the thickness direction of the resistive film 110. The second electrode 122 may consist of a conductive film located on one of the multiple wiring layers WL, for example, the furthest wiring layer WLF, which is furthest from the semiconductor substrate SS. The first electrode 121 may consist of a conductive film located on one of the multiple wiring layers WL. The first electrode 121 and the second electrode 122 may be made of a metal (e.g., aluminum) or an alloy (e.g., aluminum with tungsten or copper added).

[0031] Figure 16(c) schematically shows a cross-sectional view of a modified example of the electronic component EC of the fifth embodiment. The modified electronic component EC of the fifth embodiment may have an interlayer 130 disposed between the resistive film 110 and the first electrode 121, and between the resistive film 110 and the second electrode 122.

[0032] Figure 17 schematically shows a plan view of the electronic component EC of the sixth embodiment. Figure 18(a) schematically shows a cross-sectional view of the electronic component EC of the sixth embodiment. Matters not mentioned with respect to the electronic component EC of the sixth embodiment (including modified versions) can be described in the preceding text. The electronic component EC of the sixth embodiment is configured as a varistor and may have a first electrode 121, a resistive film 110 disposed on the first electrode 121, and a second electrode 122 disposed on the resistive film 110. In the electronic component EC of the sixth embodiment, the first electrode 121 includes at least two conductive films 201a, 202a disposed on at least two wiring layers WL of a plurality of wiring layers WL. In addition, the electronic component EC of the sixth embodiment has a second electrode 122 that includes at least two conductive films 201b, 202b disposed on at least two wiring layers WL of a plurality of wiring layers WL. Furthermore, the electronic component EC of the sixth embodiment may further include a plug VP for electrically connecting at least two conductive films 201a, 202a, and a plug VP for electrically connecting at least two conductive films 201b, 202b.

[0033] At least two conductive films 201a, 202a may include a first conductive film 201a containing a first pattern P1a and a second conductive film 202a containing a plurality of second conductive patterns P2a smaller than the first pattern P1a. At least two conductive films 201b, 202b may include a first conductive film 201b containing a first pattern P1b and a second conductive film 202b containing a plurality of second conductive patterns P2b smaller than the first pattern P1b. Such a configuration is advantageous for adjusting the varistor voltage of an electronic component EC configured as a varistor. The varistor voltage can be adjusted, for example, by adjusting the area of ​​the second conductive pattern P2.

[0034] Figure 18(b) schematically shows a cross-sectional view of a modified electronic component EC of the sixth embodiment. The modified electronic component EC of the second embodiment is configured as a varistor and may have an interlayer 130a positioned between one main surface 112 (here, the bottom surface) of the resistive film 110 and the first electrode 121, and an interlayer 130b positioned between the other main surface 111 (here, the top surface) of the resistive film 110 and the second electrode 122.

[0035] Figure 19(a) schematically shows a cross-sectional view of an electronic component EC according to the seventh embodiment. The electronic component EC of the seventh embodiment is configured as a transistor, more specifically as a bipolar transistor, and has an emitter 311, a base 312, and a collector 313. The electronic component EC of the seventh embodiment includes a semiconductor layer 310, more specifically, the emitter 311, base 312, and collector 313 may be arranged in the semiconductor layer 310. The semiconductor layer 310 may be a molybdenum oxide film, but may also be a film made of other semiconductor materials (e.g., a polysilicon film). The electronic component EC of the seventh embodiment may also have a first electrode 321 electrically connected to at least the emitter 311 and a second electrode 322 electrically connected to at least the collector 313. The second electrode 322 may be arranged such that the base 312 and the collector 322 are short-circuited, in which case the bipolar transistor may function as a diode. The first electrode 321 and the second electrode 322 may consist of a conductive film located on one of a plurality of wiring layers WL, for example, the furthest wiring layer WLF, which is furthest from the semiconductor substrate SS. The first electrode 321 and the second electrode 322 may consist of, for example, a metal (e.g., aluminum) or an alloy (e.g., aluminum with tungsten or copper added). The electronic component EC of the seventh embodiment may have an insulating film 331 that defines the region in which the first electrode 321 and the second electrode 322 are in contact with the semiconductor layer 310.

[0036] Figure 19(b) schematically shows a cross-sectional view of a modified electronic component EC of the seventh embodiment. The modified electronic component EC of the seventh embodiment is configured as a transistor, more specifically a bipolar transistor, and has an emitter 311, a base 312, and a collector 313. The modified electronic component EC of the seventh embodiment includes a semiconductor layer 310, more specifically, the emitter 311, base 312, and collector 313 may be arranged in the semiconductor layer 310. The semiconductor layer 310 may be a molybdenum oxide film, but may also be a film made of other semiconductor material (e.g., a polysilicon film). The modified electronic component EC of the seventh embodiment may also have a first electrode 321 electrically connected to at least the emitter 311 and a second electrode 322 electrically connected to at least the collector 313. The first electrode 321 may be arranged so as to short-circuit the base 312 and the emitter 311, in which case the bipolar transistor may function as a diode. The first electrode 321 and the second electrode 322 may consist of a conductive film located on one of a plurality of wiring layers WL, for example, the furthest wiring layer WLF, which is furthest from the semiconductor substrate SS. The first electrode 321 and the second electrode 322 may consist of, for example, a metal (e.g., aluminum) or an alloy (e.g., aluminum with tungsten or copper added). The electronic component EC of the seventh embodiment may have an insulating film 331 that defines the region in which the first electrode 321 and the second electrode 322 are in contact with the semiconductor layer 310.

[0037] Figure 20 schematically shows a cross-sectional view of the electronic component EC of the eighth embodiment. Matters not mentioned with respect to the electronic component EC of the eighth embodiment (including modifications) may be based on the seventh embodiment. The electronic component EC of the eighth embodiment is configured as a transistor, more specifically a bipolar transistor, and has an emitter 311, a base 312, and a collector 313. The electronic component EC of the eighth embodiment includes a semiconductor layer 310, more specifically, the emitter 311, base 312, and collector 313 may be arranged in the semiconductor layer 310. The semiconductor layer 310 may be a molybdenum oxide film, but may be a film composed of other semiconductor materials (e.g., a polysilicon film). The electronic component EC of the eighth embodiment may also have a first electrode 321 electrically connected to the emitter 311 and a second electrode 322 electrically connected to the collector 313. In the electronic component EC of the eighth embodiment, the base 312 is maintained in a floating state. The first electrode 321 may consist of a conductive film located on one of a plurality of wiring layers WL, for example, on the furthest wiring layer WLF furthest from the semiconductor substrate SS. The second electrode 322 may consist of a conductive film located on one of a plurality of wiring layers WL, for example, on a wiring layer WL below one of the furthest wiring layers WLF furthest from the semiconductor substrate SS. Alternatively, the second electrode 322 may be located between wiring layers WL. The first electrode 321 and the second electrode 322 may be made of, for example, a metal (e.g., aluminum) or an alloy (e.g., aluminum with tungsten or copper added). The electronic component EC of the eighth embodiment may have an insulating film 331 that defines the region in which the first electrode 321 is in contact with the semiconductor layer 310.

[0038] Figure 21 schematically shows a cross-sectional view of the electronic component EC of the ninth embodiment. The electronic component EC of the ninth embodiment is configured as a transistor, more specifically as a MOS transistor, and has a source 411 and a drain 412 disposed in a semiconductor layer 410, and a gate 413 disposed on the semiconductor layer 410 via a gate insulating film 414. The semiconductor layer 410 may be, for example, a molybdenum oxide film, but may also be a film made of other semiconductor materials (e.g., a polysilicon film). The source 411 and the drain 412 may have the same structure and are interchangeable. The electronic component EC of the ninth embodiment may also have a first electrode 421 electrically connected to the source 411 and the gate 413, and a second electrode 422 electrically connected to the drain 412. Alternatively, the first electrode 421 may be electrically connected to the source 411, and the second electrode 422 may be electrically connected to the drain 412 and the gate 413. The first electrode 421 and the second electrode 422 may consist of a conductive film located in one of a plurality of wiring layers WL, for example, in the furthest wiring layer WLF, which is furthest from the semiconductor substrate SS. The first electrode 421 and the second electrode 422 may consist of, for example, a metal (e.g., aluminum) or an alloy (e.g., aluminum with tungsten or copper added).

[0039] Figure 22(a) schematically shows a cross-sectional view of the electronic component EC of the tenth embodiment. The electronic component EC of the tenth embodiment is configured as a transistor, more specifically a junction field-effect transistor (JFET), and has a first conductivity type region 511 and a second conductivity type region 512 arranged in a semiconductor layer 510. The first conductivity type region 511 and the second conductivity type region 512 are opposite conductivity types to each other. The semiconductor layer 510 may be, for example, a molybdenum oxide film, but may also be a film made of other semiconductor materials (e.g., a polysilicon film). The electronic component EC of the tenth embodiment also has a first electrode 521 that constitutes the source electrode, a second electrode 522 that constitutes the drain electrode, and a third electrode 523 that constitutes the gate electrode. The first electrode 521 and the second electrode 522 are arranged so as to sandwich the second conductivity region 512 and to be electrically connected to the first conductivity region 511, and the third electrode 523 is arranged between the first electrode 521 and the second electrode 522 so as to be electrically connected to the second conductivity region 512. The first electrode 521, the second electrode 522 and the third electrode 523 may be arranged so as to be in contact with the upper surface of the semiconductor layer 510. The first electrode 521 and the second electrode 522 may be electrically connected, in which case the junction field-effect transistor may function as a diode. The first electrode 521, the second electrode 522 and the third electrode 523 may consist of conductive films located on any one of a plurality of wiring layers WL, for example, the furthest wiring layer WLF furthest from the semiconductor substrate SS. The first electrode 521, the second electrode 522, and the third electrode 523 may be made of, for example, a metal (e.g., aluminum) or an alloy (e.g., aluminum with tungsten or copper added). An insulating layer 530 may be placed beneath the semiconductor layer 510.

[0040] Figure 22(b) schematically shows a cross-sectional view of an electronic component EC of a modified example of the tenth embodiment. The electronic component EC of the modified example of the tenth embodiment is configured as a transistor, more specifically a junction field-effect transistor (JFET), and has a first conductivity type region 511 and a second conductivity type region 512 arranged in a semiconductor layer 510. The first conductivity type region 511 and the second conductivity type region 512 are opposite conductivity types to each other. The semiconductor layer 510 may be, for example, a molybdenum oxide film, but may also be a film made of other semiconductor materials (e.g., a polysilicon film). The electronic component EC of the tenth embodiment also has a first electrode 521 that constitutes a source electrode, a second electrode 522 that constitutes a drain electrode, and a third electrode 523 that constitutes a gate electrode. The first electrode 521 and the second electrode 522 are arranged to be electrically connected to the first conductivity type region 511, and the third electrode 523 is arranged to be electrically connected to the second conductivity type region 512. The first electrode 521 and the second electrode 522 may be positioned to contact the lower surface of the semiconductor layer 510. The third electrode 523 may be positioned to contact the upper surface of the semiconductor layer 510. The first electrode 521 and the second electrode 522 may be electrically connected, in which case the junction field-effect transistor may function as a diode. The third electrode 523 may consist of a conductive film positioned in one of the plurality of wiring layers WL, for example, in the furthest wiring layer WLF furthest from the semiconductor substrate SS. The first electrode 521 and the second electrode 522 may consist of a conductive film positioned in one of the plurality of wiring layers WL, for example, in one of the wiring layers WL below the furthest wiring layer WLF furthest from the semiconductor substrate SS. Alternatively, the first electrode 521 and the second electrode 522 may be positioned between wiring layers WL. The first electrode 521, the second electrode 522, and the third electrode 523 may be made of, for example, a metal (e.g., aluminum) or an alloy (e.g., aluminum with tungsten or copper added).

[0041] Figure 23(a) schematically shows a cross-sectional view of an electronic component EC of the 11th embodiment. The electronic component EC of the 11th embodiment is configured as a diode, more specifically as a PN junction diode, and has a first conductivity type region 611 and a second conductivity type region 612. The first conductivity type region 611 and the second conductivity type region 612 are opposite conductivity types, and their junction surfaces constitute a PN junction. The first conductivity type region 611 and the second conductivity type region 612 may be, for example, a molybdenum oxide film, but may also be a film composed of other semiconductor materials (e.g., a polysilicon film). The electronic component EC of the 11th embodiment also has one or more first electrodes 621 (two first electrodes 621a, 621b in the illustrated example) electrically connected to the first conductivity type region 611, and one or more second electrodes 622 (two second electrodes 622a, 622b in the illustrated example) electrically connected to the second conductivity type region 612. If multiple first electrodes 621 are provided, they may be electrically connected to each other. Similarly, if multiple second electrodes 622 are provided, they may be electrically connected to each other. One or more first electrodes 621 and one or more second electrodes 622 may be made of, for example, a metal (e.g., aluminum) or an alloy (e.g., aluminum with tungsten or copper added). In the example shown in Figure 23(a), the first electrodes 621a and the second electrodes 622a may be made of conductive films located in any one of the multiple wiring layers WL, for example, in the furthest wiring layer WLF furthest from the semiconductor substrate SS. The first electrodes 621b and the second electrodes 622b may be made of conductive films located in any one of the multiple wiring layers WL, for example, in the wiring layer WL below one of the furthest wiring layers WLF furthest from the semiconductor substrate SS. Alternatively, the first electrodes 621b and the second electrodes 622b may be located between wiring layers WL.

[0042] Figure 23(b) schematically shows a cross-sectional view of an electronic component EC of a modified example of the 11th embodiment. The electronic component EC of the 11th embodiment is configured as a diode, more specifically as a PN junction diode, and has a first conductivity type region 611 and a second conductivity type region 612. The first conductivity type region 611 and the second conductivity type region 612 are opposite conductivity types, and their junction surfaces constitute a PN junction. The first conductivity type region 611 and the second conductivity type region 612 may be, for example, a molybdenum oxide film, but may also be a film made of another semiconductor material (e.g., a polysilicon film). The electronic component EC of the modified example of the 11th embodiment also has one or more first electrodes 621 electrically connected to the first conductivity type region 611 and one or more second electrodes 622 electrically connected to the second conductivity type region 612. If multiple first electrodes 621 are provided, they may be electrically connected to each other. Furthermore, if multiple second electrodes 622 are provided, they may be electrically connected to each other. One or more first electrodes 621 and one or more second electrodes 622 may be made of, for example, a metal (e.g., aluminum) or an alloy (e.g., aluminum with tungsten or copper added). In the example shown in Figure 23(b), the first electrode 621 may be made of a conductive film located in any one of the multiple wiring layers WL, for example, the furthest wiring layer WLF furthest from the semiconductor substrate SS. The second electrode 622 may be made of a conductive film located in any one of the multiple wiring layers WL, for example, the wiring layer WL below one of the furthest wiring layers WLF furthest from the semiconductor substrate SS. Alternatively, the second electrode 622 may be located between wiring layers WL.

[0043] Figure 24 schematically shows a cross-sectional view of an electronic component EC of the twelfth embodiment. The electronic component EC of the twelfth embodiment is configured as a diode, more specifically a Schottky diode, and includes a semiconductor layer 710, a barrier metal 720 disposed in contact with one surface of the semiconductor layer 710, a first electrode 731 disposed in contact with the barrier metal 720, and a second electrode 732 disposed in contact with the other surface of the semiconductor layer 710. The semiconductor layer 710 and the barrier metal 720 form a Schottky junction. The semiconductor layer 710 may be, for example, a molybdenum oxide film, but may also be a film made of another semiconductor material (e.g., a polysilicon film). The first electrode 731 and the second electrode 732 may be made of, for example, a metal (e.g., aluminum) or an alloy (e.g., aluminum with tungsten or copper added). The first electrode 731 may be made of a conductive film disposed on one of a plurality of wiring layers WL, for example, the furthest wiring layer WLF, which is furthest from the semiconductor substrate SS. The second electrode 732 may consist of a conductive film placed below one of the multiple wiring layers WL, for example, the wiring layer WL of the furthest wiring layer WLF furthest from the semiconductor substrate SS. Alternatively, the second electrode 732 may be placed between wiring layers WL.

[0044] Figure 25 schematically shows a cross-sectional view of the electronic component EC of the 13th embodiment. The electronic component EC of the 13th embodiment is configured as a diode, more specifically as a PIN diode, and has a first conductivity type region 811, a second conductivity type region 812, and an intrinsic semiconductor region 813 arranged in a semiconductor layer 810. The first conductivity type region 811 and the second conductivity type region 812 are opposite conductivity types. The intrinsic semiconductor region 813 is located between the first conductivity type region 811 and the second conductivity type region 812. The semiconductor layer 810 may be, for example, a molybdenum oxide film, but may also be a film made of other semiconductor materials (e.g., a polysilicon film). The electronic component EC of the 13th embodiment also has a first electrode 821 arranged to contact the first conductivity type semiconductor region 811 and a second electrode 822 arranged to contact the second conductivity type semiconductor region 812. The first electrode 821 and the second electrode 822 may be composed of, for example, a metal (e.g., aluminum) or an alloy (e.g., aluminum with tungsten or copper added). The first electrode 821 may consist of a conductive film placed in one of the plurality of wiring layers WL, for example, the furthest wiring layer WLF furthest from the semiconductor substrate SS. The second electrode 822 may consist of a conductive film placed in one of the plurality of wiring layers WL, for example, the wiring layer WL below one of the furthest wiring layers WLF furthest from the semiconductor substrate SS. Alternatively, the second electrode 822 may be placed between wiring layers WL.

[0045] Figure 26 shows an example configuration of an electronic device 1100 as an application example of the semiconductor device 1 described above. The electronic device 1100 may be, for example, a computer, an information terminal, a communication terminal, a camera, a signal processing device, a vehicle control device, a flight control device, etc., or a composite of at least two of these electronic devices. The electronic device 1100 includes a plurality of semiconductor devices 1101, 1102, 1103, which may be arranged on one or more printed circuit boards (PCBs). At least one of the plurality of semiconductor devices 1101, 1102, 1103 may incorporate an electronic component EC, as in the semiconductor device 1 described above. The electronic device 1100 may also include one or more electronic components arranged outside the plurality of semiconductor devices 1101, 1102, 1103. The electronic component EC may have the configuration described as any of the first to sixth embodiments. The electronic component EC may be arranged between two or more signal lines 1112 in the electronic device 1100. Two or more such signal lines 1112 may be located adjacent to each other, or they may be located via other signal lines 1112. The electronic component EC may be located between the signal line 1112 and the power line. The electronic component EC may be located between the signal line 1112 and the ground line. The electronic component EC may be electrically connected to a pad or terminal 1111.

[0046] The invention is not limited to the embodiments described above, and various modifications and changes are possible within the scope of the gist of the invention.

Claims

1. A semiconductor device comprising a semiconductor substrate, a wiring structure disposed on the semiconductor substrate, and electronic components, The wiring structure includes a pad region including a pad and a circuit region, each of the pad region and the circuit region including a plurality of wiring layers, interlayer insulating films disposed between the plurality of wiring layers, and via plugs connecting the plurality of wiring layers to each other. The aforementioned electronic component is an active element, The aforementioned electronic component is electrically connected to the pad, The aforementioned electronic component is located in the circuit region and above the upper surface of the semiconductor substrate. A semiconductor device characterized by the following features.

2. The aforementioned electronic component is positioned within the circuit region in close proximity to the pad region. The semiconductor device according to feature 1.

3. The electronic component is electrically connected to the pad by a wiring pattern. The semiconductor device according to feature 1.

4. The electronic component is electrically connected to the pad via a wiring pattern and a resistive element. The semiconductor device according to feature 1.

5. The wiring structure further comprises a second pad region including a second pad, The electronic component is located between the pad region and the second pad region. The semiconductor device according to feature 1.

6. The aforementioned electronic component has a molybdenum oxide film, The semiconductor device according to feature 1.

7. The electronic component has an electrode that includes a conductive film disposed in the furthest wiring layer, which is the furthest from the semiconductor substrate, among the plurality of wiring layers. The semiconductor device according to feature 1.

8. The aforementioned electronic component is a transistor. The semiconductor device according to feature 1.

9. The transistor includes a molybdenum oxide film, The semiconductor device according to feature 8.

10. The aforementioned transistor is a bipolar transistor. The semiconductor device according to feature 8.

11. The bipolar transistor has a base that is maintained in a floating state. The semiconductor device according to feature 10.

12. The bipolar transistor has its base and collector short-circuited, or its base and emitter short-circuited. The semiconductor device according to feature 10.

13. The aforementioned transistor is a MOS transistor. The semiconductor device according to feature 9.

14. The MOS transistor has its gate and source or drain short-circuited. The semiconductor device according to feature 13.

15. The aforementioned transistor is a junction field-effect transistor. The semiconductor device according to feature 9.

16. The aforementioned junction field-effect transistor has its source and drain short-circuited. The semiconductor device according to feature 15.

17. The aforementioned electronic component is a diode. The semiconductor device according to feature 1.

18. The diode includes a molybdenum oxide film. The semiconductor device according to feature 17.

19. The diode is a PN junction diode. The semiconductor device according to feature 18.

20. The diode is a Schottky diode. The semiconductor device according to feature 17.

21. The diode is a PIN junction diode. The semiconductor device according to feature 17.

22. The circuit region includes a transistor located beneath the electronic component. A semiconductor device according to any one of claims 1 to 21.

23. An electronic device comprising a semiconductor device according to any one of claims 1 to 21.

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