Semiconductor module

Abstract

To provide a semiconductor module that is less susceptible to noise in gate wiring and sense wiring. [Solution] A semiconductor module 1 comprising: a first substrate 10 on which a first gate wiring 12 and a first sense wiring 13 are formed; a semiconductor element 20 disposed on the first substrate 10 and having a gate electrode and a main electrode, the gate electrode being connected to the first gate wiring 12 and the main electrode being connected to the first sense wiring 13; a pin terminal 30 electrically connected to at least one of the first gate wiring 12 and the first sense wiring 13 and extending upward; a second substrate 40 disposed above the first substrate 10 and having a second gate wiring 42 and a second sense wiring 43, the second gate wiring 42 and the second sense wiring 43 being connected to the pin terminal 30; and an external connector 50 disposed on the second substrate 40 and connected to the second gate wiring 42 and the second sense wiring 43.

Description

Technical Field

[0001] The present invention relates to a semiconductor module.

Background Art

[0002] Conventionally, a semiconductor module that collectively connects a gate wiring and a sense wiring connected to a semiconductor element to the outside with a connector is known (see, for example, Patent Document 1).

[0003] As such a semiconductor module (conventional semiconductor module 900), for example, a semiconductor module as shown in FIG. 7 can be exemplified. The conventional semiconductor module 900 includes a substrate 910 having gate wiring 912 (912a) and sense wiring 913 (913a), a semiconductor element 920 (920a) disposed on the substrate 910, and an external connection connector 950 disposed on the substrate 910 and connected to the gate wiring 912 and the sense wiring 913. It is a three-phase inverter module.

[0004] In the conventional semiconductor module, by routing the gate wiring 912 and the sense wiring 913 and connecting them to the connector 950, the gate wiring 912, the sense wiring 913, and an external control board can be collectively connected using the connector.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] However, in conventional semiconductor modules 900, the gate wiring 912, sense wiring 913, and connector 950 are located on the same substrate 910 as the main current wiring 914-918. Therefore, the gate wiring 912 and sense wiring 913 make a large detour to the outer edge of the substrate 910 to avoid the main current wiring 914-918 and connect to the connector 950. As a result, it is difficult to sufficiently separate the gate wiring 912 and sense wiring 913 from the main current wiring 914-918 in all areas of the substrate 910, which leads to a problem where noise is easily generated in the gate wiring 912 and sense wiring 913.

[0007] Furthermore, because the gate wiring 912 and sense wiring 913 are connected to the connector 950 by making a large detour to the outer periphery of the circuit board 910 to avoid the main current wiring 914-918, the inductance increases due to the longer wiring pattern distance (see Figure 5 described later), which presents a problem in that noise is more likely to occur in the gate wiring 912 and sense wiring 913 during high-frequency operation.

[0008] This invention was made to solve the above-mentioned problems, and aims to provide a semiconductor module that is less susceptible to noise in gate wiring and sense wiring. [Means for solving the problem]

[0009] The semiconductor module of the present invention is characterized by comprising: a first substrate on which at least a first gate wiring and a first sense wiring are formed; a semiconductor element disposed on the first substrate and having a gate electrode and a main electrode, wherein the gate electrode is connected to the first gate wiring and the main electrode is connected to the first sense wiring; a pin terminal electrically connected to at least one of the first gate wiring and the first sense wiring and extending upward; a second substrate disposed above the first substrate and having a second gate wiring and a second sense wiring, wherein the second gate wiring and the second sense wiring are each connected to the corresponding pin terminal; and an external connector disposed on the second substrate and connected to the second gate wiring and the second sense wiring. [Effects of the Invention]

[0010] The semiconductor module of the present invention includes pin terminals extending upward, a second substrate positioned above the first substrate and to which the second gate wiring and second sense wiring are connected to corresponding pin terminals, and an external connector positioned on the second substrate and connected to the second gate wiring and second sense wiring. Therefore, the first gate wiring and first sense wiring can be connected to the connector via the pin terminals, the second gate wiring, and the second sense wiring, and the connector can be positioned on a substrate different from the main current wiring. Consequently, there is no need to make a large detour of the first gate wiring and first sense wiring to the outer periphery of the substrate to avoid the main current wiring, and the first gate wiring and first sense wiring can be sufficiently separated from the main current wiring. Furthermore, since the second gate wiring and second sense wiring are separated from the first substrate, they can be sufficiently separated from the main current wiring. As a result, noise is less likely to occur in the gate wiring (first gate wiring and second gate wiring) and sense wiring (first sense wiring and second sense wiring).

[0011] Furthermore, according to the semiconductor module of the present invention, since it is not necessary to route gate wiring and sense wiring to avoid routing the main current wiring, the wiring pattern distance can be shortened and the inductance can be reduced (see Figure 6). As a result, noise is less likely to occur in the gate wiring and sense wiring, especially during high-frequency operation. [Brief explanation of the drawing]

[0012] [Figure 1] This figure shows a semiconductor module 1 according to an embodiment. Figure 1(a) shows a plan view of the semiconductor module 1, and Figure 1(b) shows a cross-sectional view of the semiconductor module 1. [Figure 2] This figure shows the relationship between the first substrate 10, the semiconductor element 20, and the connecting member 32 of the semiconductor module 1 according to the embodiment. In Figure 2, Figure 1(a) is a diagram in which the molding resin 70, the second substrate 40, and the connector 50 are omitted from the illustration. [Figure 3]This figure shows the relationship between the second substrate 40, connector 50, and case 60 of the semiconductor module 1 according to the embodiment. Figure 3(a) is a plan view showing the relationship between the second substrate 40, connector 50, and case 60 of the semiconductor module 1, and Figure 3(b) is a cross-sectional view showing the relationship between the second substrate 40, connector 50, and case 60 of the semiconductor module 1. Note that Figure 3 is a figure from Figure 1(a) in which the molding resin 70 is omitted. [Figure 4] This figure shows the relationship between the second gate wiring and second sense wiring of the semiconductor module 1 according to the embodiment and the pin terminal 30. Figure 4 is a figure from Figure 3(a) in which the insulating substrate 41 of the second substrate 40 is omitted. [Figure 5] This graph shows the relationship between the inductance of each semiconductor element in the semiconductor module according to the embodiment and the switching frequency of the switch element. [Figure 6] This graph shows the relationship between the inductance of each semiconductor element in the semiconductor module of the comparative example and the switching frequency of the switch element. [Figure 7] This is a plan view showing a conventional semiconductor module 900. [Modes for carrying out the invention]

[0013] The semiconductor module of the present invention will be described below based on the embodiments shown in the figures. Note that the embodiments described below do not limit the invention as defined in the claims. Furthermore, not all of the elements and combinations thereof described in the embodiments are necessarily essential to the solution of the present invention.

[0014] [Embodiment] 1. Configuration of the semiconductor module 1 according to the embodiment FIG. 1 is a diagram showing a semiconductor module 1 according to an embodiment. In the semiconductor module 1, the longitudinal direction is defined as the x - direction (the right side in FIG. 1 (the side where the semiconductor element 20f described later is arranged) is taken as positive), the short - hand direction is defined as the y - direction (the upper side in FIG. 1 (the side where the terminals T1 and T2 are provided) is taken as positive), and the height direction is defined as the z - direction (the side where the connector is provided is taken as positive). Also, when referring collectively to a plurality of members of the same kind, the alphabet after the number may be omitted. For example, when referring collectively to the semiconductor elements 20a, 20b, 20c, 20d, 20e, and 20f, they may simply be referred to as the semiconductor element 20.

[0015] As shown in FIG. 1, the semiconductor module 1 according to the embodiment includes a first substrate 10, semiconductor elements 20, pin terminals 30 and 31, a second substrate 40, and a connector 50. These are housed in a case 60 and sealed with a resin 70. The semiconductor module 1 has a substantially rectangular - parallelepiped shape. On the lower - surface side of the semiconductor module 1, the back - surface side of the first substrate 10 is exposed. On the upper - surface side, the connector 50 is exposed on the slightly - x - direction side of the central portion, and the longitudinal direction of the connector 50 is arranged to extend in the y - direction. On the +y - direction side (the upper side in FIG. 1) of the upper surface, force terminals T1 and T2 are provided, and on the -y - direction side of the upper surface, force terminals T3, T4, and T5 are respectively exposed on the upper side of the case 60.

[0016] The case 60 is made of a relatively hard resin. The case 60 has an opening at the center and can be filled with resin by potting. The central opening and the second substrate 40 have corresponding sizes and shapes. The case 60 is provided with regions for forming the force terminals T1 and T2 in the +y - direction and regions for forming the force terminals T3 to T5 in the -y - direction.

[0017] The force terminal T1 is an input terminal, and the force terminal T2 is an output terminal. The force terminals T3 to T5 respectively constitute a U terminal, a V terminal, and a W terminal. The force terminals T1 to T5 are respectively connected to the first wiring 14 to the fifth wiring 18 described later. The force terminal T1 is connected to an external power supply, and the force terminal T2 is connected to a reference potential.

[0018] The first substrate 10 has a metal film (for example, a copper film) formed on the front and back surfaces of the insulating substrate 11.

[0019] The metal film on the front side is pattern-wired. As shown in FIG. 2, a first wiring (bus bar) 14 extending in the +x direction along the outer edge of the insulating substrate 11 in the +y direction, a second wiring 15 disposed on the -y direction side of the first wiring 14 and extending in the x direction, a third wiring 16 disposed on the -y direction side of the first wiring 14 on the -x direction side of the insulating substrate 11, a fourth wiring 17 disposed on the -y direction side of the second wiring 15 and on the +x direction side of the third wiring 16, and a fifth wiring 18 disposed on the -y direction side of the first wiring 14 on the +x direction side of the insulating substrate 11 are formed, and they are spaced apart from each other. Also, the first gate wirings 12a, 12b, 12c, 12d, 12e, 12f and the first sense wirings 13a, 13b, 13c, 13d, 13e, 13f are also formed in a state of being spaced apart from each of the wirings.

[0020] In the first wiring 14 and the fifth wiring 18, openings corresponding to regions for arranging support portions 80 for supporting a second substrate 40 described later are formed. Also, in the first wiring 14, lands (not shown) are formed for arranging semiconductor elements 20a, 20c on the -x direction side from the center and semiconductor element 20f on the +x direction side. Also, lands for arranging semiconductor elements 20b, 20d, 20e are provided in the third wiring 16 to the fifth wiring 18 respectively.

[0021] Near each land, the first gate wiring and the first sense wiring are formed so as to be spaced apart from each other and adjacent to each other.

[0022] The first gate wirings 12a, 12b, 12c, 12d, 12e, and 12f are formed spaced apart so that they are close to the gate electrodes of each semiconductor element 20a to 20f when each semiconductor element 20a to 20f is placed. One end of each first gate wiring 12a, 12b, 12c, 12d, 12e, and 12f is electrically connected to the gate electrode of the semiconductor element 20 via connecting members 34a, 34b, 34c, 34d, 34e, and 34f (these six connecting members are sometimes collectively referred to as connecting member 34), and the other end is connected to pin terminals 30a to 30f.

[0023] The first sense wirings 13a, 13b, 13c, 13d, 13e, and 13f are formed near the corners of the source electrodes of the semiconductor elements 20a to 20f when each semiconductor element 20a to 20f is positioned, and are spaced apart from the other wirings. One end of the first sense wiring 13 is connected to a thin portion extending from the region connected to the main electrode of the semiconductor element 20 in the connecting member 32, which will be described later, and the other end is connected to the pin terminal 31.

[0024] Each semiconductor element 20a, 20b, 20c, 20d, 20e, and 20f has a source electrode and a drain electrode as main electrodes, as well as a gate electrode, and the drain electrode is arranged on the first substrate 10 with the drain electrode connected to the first wiring 14 or the third to fifth wirings 16 to 18. The source electrode is formed on most of the side opposite to the first substrate 10, and the gate electrode is formed in the center of one side of the rectangular source electrode.

[0025] Each gate electrode is connected to the corresponding first gate wiring 12 via a gate connecting member 34. Each main electrode is connected to the wiring of the first substrate 10 via a connecting member 32, and is also connected to the first sense wiring 13 of the first substrate 10. The connecting member 32 has a wide portion on one side which is a source connection portion connected to the source electrode, and the other side which is a wiring connection portion connected to the wiring of the first substrate 10. It also has sense wiring connection portions 33a to 33f connected to the source connection portion.

[0026] The semiconductor element 20a is positioned near the -x end of the first wiring 14. The source electrode is connected to the third wiring 16 via a connecting member 32a, and is also connected to the first sense wiring 13a via a sense wiring connection portion 33a, which is formed in a continuous (integrated) state with the connecting member 32a. The gate electrode is connected to the first gate wiring 12a via a gate connecting member 34a.

[0027] The semiconductor element 20b is positioned near the boundary between the third wiring 16 and the second wiring 15 and the fourth wiring 17. The source electrode is connected to the second wiring 15 via a connecting member 32b, and is also connected to the first sense wiring 13b via a sense wiring connection portion 33b which is formed in a continuous state with the connecting member 32b. The gate wiring is connected to the first gate wiring 12b via a gate connecting member 34b.

[0028] The semiconductor element 20c is positioned slightly towards the -x direction from the center of the first wiring 14. The source electrode is connected to the fourth wiring 17 via a connecting member 32c, and is also connected to the first sense wiring 13c via a sense wiring connection portion 33c which is formed in a continuous state with the connecting member 32c. The gate wiring is connected to the first gate wiring 12c via a gate connecting member 34c.

[0029] The semiconductor element 20d is positioned near the boundary between the second wiring 15 and the fifth wiring 18 in the fourth wiring 17. The source electrode is connected to the second wiring 15 via a connecting member 32d, and is also connected to the first sense wiring 13d via a sense wiring connection portion 33d which is formed in a continuous state with the connecting member 32d. The gate wiring is connected to the first gate wiring 12d via a gate connecting member 34d.

[0030] The semiconductor element 20e is positioned near the boundary between the second wiring 15 and the fourth wiring 17 in the fifth wiring 18. The source electrode is connected to the second wiring 15 via a connecting member 32e, and is also connected to the first sense wiring 13e via a sense wiring connection portion 33e which is formed in a continuous state with the connecting member 32e. The gate wiring is connected to the first gate wiring 12e via a gate connecting member 34e.

[0031] The semiconductor element 20f is positioned near the boundary between the second wiring 15 and the fifth wiring 18 at the +x-direction end of the first wiring 14. The source electrode is connected to the fifth wiring 18 via a connecting member 32f and to the first sense wiring 13f via a sense wiring connection portion 33f which is formed in a continuous state with the connecting member 32f. The gate wiring is connected to the first gate wiring 12f via a gate connecting member 34f.

[0032] Viewed in plan view, the spacing between semiconductor elements in the region close to where the connector 50 is located is narrower than the spacing between conductive elements in the region farther from where the connector 50 is located. Specifically, as shown in Figures 2 to 4, the spacing between adjacent semiconductor elements 20a, 20b, and 20c on the -x side (left side of Figure 2) of the first substrate 10 is narrower than the spacing between adjacent semiconductor elements 20d, 20e, and 20f on the +x side (right side of Figure 2) of the first substrate 10.

[0033] The semiconductor module 1 according to this embodiment constitutes a three-phase inverter in which semiconductor elements 20a and 20b, semiconductor elements 20c and 20d, and semiconductor elements 20e and 20f are connected in parallel to each other, respectively.

[0034] As shown in Figures 1 to 4, pin terminal 30 is electrically connected to the first gate wiring 12, extends upward (in the +z direction), and penetrates through holes formed at the ends of the second gate wirings 42a to 42f on the second substrate 40. Pin terminal 31 is electrically connected to the first sense wiring 13, extends upward (in the +z direction), and penetrates through holes formed at the end of the second sense wiring 43 on the second substrate 40. Pin terminals 30 and 31 are positioned to maintain insulation from each other.

[0035] The second substrate 40 is positioned above the first substrate 10 and spaced apart from it. As shown in Figure 3, the second substrate 40 has an insulating substrate 41 and second gate wirings 42a, 42b, 42c, 42d, 42e, 42f and second sense wirings 43a, 43b, 43c, 43d, 43e, 43f formed on the insulating substrate 41. The second gate wirings 42a, 42b, 42c, 42d, 42e, 42f and the second sense wirings 43a, 43b, 43c, 43d, 43e, 43f each correspond to six semiconductor elements 20a, 20b, 20c, 20d, 20e, 20f, and are connected to the first gate wirings 12a, 12b, 12c, 12d, 12e, 12f and the first sense wirings 13a, 13b, 13c, 13d, 13e, 13f via pin terminals 30, 31, respectively. In Embodiment 1, the second substrate 40 is a glass epoxy substrate, but any suitable substrate can be used. The second substrate 40 is supported on the first substrate 10 by three support parts 80 spaced appropriately apart.

[0036] The second gate wiring 42 and the second sense wiring 43 are, for example, a metal film, such as copper foil. One end of each second gate wiring 42 and second sense wiring 43 is connected to a connector 50. The other end has a through-hole through which the corresponding pin terminals 30 and 31 are connected. The second gate wiring 42 and second sense wiring 43 are composed of a straight section extending in the y-direction or x-direction, and an oblique section extending from the tip of the straight section in the +x-direction or -x-direction, and are formed without large detours.

[0037] Connector 50 is an external connector located on the second substrate 40 and connected to the second gate wiring 42 and the second sense wiring 43. Connector 50 consists of a box-shaped housing 51 and a plurality of contacts 52 formed inside the housing 51. The plurality of contacts pass through the underside of the housing 51 and are connected to the corresponding second gate wiring 42 or second sense wiring 43.

[0038] For example, potting resin can be used for the resin 70. The resin 70 is poured through the central opening of the case 60 and solidified to fill the top surface of the first substrate 10, the semiconductor element 20, the pin terminals 30, the second substrate 40, and the bottom of the connector 50.

[0039] 2. Parasitic inductance of semiconductor module 1 according to the embodiment Next, the parasitic inductance of the semiconductor module 1 according to the embodiment will be explained using the semiconductor modules of the example and comparative example.

[0040] The semiconductor module according to the embodiment is a semiconductor module having the same configuration as the semiconductor module according to the embodiment. The semiconductor module according to the comparative example is a semiconductor module having the same configuration as the conventional semiconductor module 900. The semiconductor elements 20a, 20b, 20c, 20d, 20e, and 20f of the semiconductor modules according to the embodiment and comparative example are designated as Q1 to Q6, respectively.

[0041] The inductance of the gate electrodes of semiconductor elements Q1 to Q6 was calculated and detected by computer simulation when a voltage of a predetermined frequency was applied to the semiconductor modules according to the examples and comparative examples, and plotted for each frequency to obtain a graph of inductance against frequency.

[0042] As shown in Figure 5, in the semiconductor module relating to the comparative example, the inductance of each semiconductor element is large at low frequencies and decreases as the frequency increases. Specifically, at a frequency of 10 3At this level, the inductance of semiconductor element Q1 is approximately 30 nH, the inductance of semiconductor element Q2 is approximately 57 nH, the inductance of semiconductor element Q3 is approximately 95 nH, the inductance of semiconductor element Q4 is approximately 45 nH, the inductance of semiconductor element Q5 is approximately 70 nH, and the inductance of semiconductor element Q6 is approximately 120 nH.

[0043] In contrast, as shown in Figure 6, the semiconductor module according to the embodiment shows that even at low frequencies, the inductance of each semiconductor element only increases slightly, and does not change significantly with frequency. Specifically, at a frequency of 10 3 At this level, the inductance of semiconductor element Q1 is approximately 22 nH, the inductance of semiconductor element Q2 is approximately 20 nH, the inductance of semiconductor element Q3 is approximately 60 nH, the inductance of semiconductor element Q4 is approximately 25 nH, the inductance of semiconductor element Q5 is approximately 23 nH, and the inductance of semiconductor element Q6 is approximately 43 nH.

[0044] Although not shown in the diagram, the inductance of all sense lines was also calculated, and the inductance of all six first sense lines in the embodiment is smaller than the inductance of the six first sense lines in the comparative example.

[0045] Therefore, it was confirmed that the inductance was reduced in all semiconductor devices.

[0046] 3. Effects of the semiconductor module 1 according to the embodiment According to the semiconductor module 1 of this embodiment, it includes upward-extending pin terminals 30, 31, a second substrate 40 positioned above the first substrate 10 with a second gate wiring 42 and a second sense wiring 43 connected to the corresponding pin terminals 30, 31, and an external connector 50 positioned on the second substrate 40 and connected to the second gate wiring 42 and the second sense wiring 43. Therefore, the first gate wiring 12 and the first sense wiring 13 can be connected to the connector 50 via the pin terminals 30, 31, the second gate wiring 42 and the second sense wiring 43, and the connector 50 can be positioned on a substrate different from the main current wiring. Consequently, it is not necessary to make a large detour around the outer periphery of the first substrate to avoid the main current wiring for the first gate wiring 12 and the first sense wiring 13, and the first gate wiring 12 and the first sense wiring 13 can be sufficiently separated from the main current wiring. Furthermore, since the second gate wiring 42 and the second sense wiring 43 are separated from the first substrate 10, they can be sufficiently separated from the main current wiring. As a result, noise is less likely to occur in the gate wiring (first gate wiring 12 and second gate wiring 42) and sense wiring (first sense wiring 13 and second sense wiring 43).

[0047] Furthermore, according to the semiconductor module 1 of this embodiment, since it is not necessary to route the first gate wiring 12 and the first sense wiring 13 to avoid routing the main current wiring, the wiring pattern distance can be shortened and the inductance can be reduced (see Figure 6). As a result, noise is less likely to occur in the gate wiring and sense wiring during high-frequency operation.

[0048] Furthermore, since the semiconductor module 1 according to this embodiment constitutes a three-phase inverter as a semiconductor module, the difference in inductance between each phase can be reduced, and as a result, the inductance of each semiconductor element of the semiconductor module can be reduced.

[0049] Furthermore, according to the semiconductor module 1 of the embodiment, when viewed in plan, the spacing between semiconductor elements in the region close to where the connector 50 is located (the left region in Figure 2) is narrower than the spacing between semiconductor elements in the region far from where the connector 50 is located (the right region in Figure 2). Therefore, the second gate wiring 42 and second sense wiring 43 in the region close to the connector 50 can be shortened, and the influence from adjacent second gate wiring 42 and second sense wiring 43 in the region far from the connector 50 can be reduced.

[0050] Furthermore, according to the semiconductor module 1 of this embodiment, since the semiconductor module 1 is covered with a case 60 having an opening in the center, it can be made highly resistant to external shocks. Also, since an area for arranging terminals can be secured in the case 60, it is possible to prevent the occupied area of ​​the semiconductor module from increasing due to extending force terminals outside the first substrate 10, for example, when an insert case is used.

[0051] Furthermore, according to the semiconductor module 1 of the embodiment, since the second substrate 40 is a glass epoxy substrate, it can be made into a second substrate that has excellent mechanical strength, rigidity, heat resistance temperature, insulation and heat insulation properties, and is resistant to warping even when thin.

[0052] Although the present invention has been described above based on the embodiments described above, the present invention is not limited to the embodiments described above. It can be implemented in various forms without departing from the spirit of the invention, and for example, the following modifications are also possible.

[0053] (1) The positions, connections, number, circuit configuration, terminals, etc. described in the above embodiments (including each modified example; the same applies hereinafter) are illustrative examples and can be changed within the scope that does not impair the effects of the present invention.

[0054] (2) In the above embodiment, a substrate with wiring (second gate wiring and second sense wiring) arranged on only one side was used as the second substrate, but the present invention is not limited thereto. A substrate capable of arranging wiring on both sides may be used as the second substrate. In this case, the second sense wiring can be formed on one side of the second substrate and the second gate wiring can be formed on the other side. In this case, it is particularly preferable that the second gate wiring and the second sense wiring of the semiconductor element furthest from the connector are arranged in an overlapping region when viewed in plan. With such a configuration, the wiring can be arranged so that the magnetic field (noise) formed by the current flowing through the second gate wiring is canceled out by the magnetic field (noise) formed by the current flowing through the second sense wiring, resulting in a semiconductor module that is even less prone to noise. [Explanation of Symbols]

[0055] 1...Semiconductor module, 10...First substrate, 12,12a,12b,12c,12d,12e,12f...First gate wiring, 13,13a,13b,13c,13d,13e,13f...First sense wiring, 20,20a,20b,20c,20d,20e,20f...Semiconductor element, 30,31...Pin terminals, 40...Second substrate, 42,42a,42b,42c,42d,42e,42f...Second gate wiring, 43,43a,43b,43c,43d,43e,43f...Second sense wiring, 50...Connector, 60...Case, 70...Resin

Claims

1. A first substrate on which at least a first gate trace and a first sense trace are formed, A semiconductor element disposed on the first substrate, having a gate electrode and a main electrode, wherein the gate electrode is connected to a first gate wiring and the main electrode is connected to a first sense wiring, A pin terminal electrically connected to at least one of the first gate wiring and the first sense wiring, and extending upward, A second board is positioned above the first board and has a second gate wiring and a second sense wiring, the second gate wiring and the second sense wiring being connected to the corresponding pin terminals, A semiconductor module characterized by comprising an external connector disposed on the second substrate and connected to the second gate wiring and the second sense wiring.

2. The aforementioned semiconductor element has six semiconductor elements, The second gate wiring and second sense wiring have a number corresponding to six of the semiconductor elements, The semiconductor module according to claim 1, characterized in that the semiconductor module constitutes a three-phase inverter.

3. The semiconductor element comprises a plurality of semiconductor elements, The semiconductor module according to claim 1 or 2, characterized in that, when viewed in plan, the spacing between the semiconductor elements in the region close to the location where the connector is located is narrower than the spacing between the semiconductor elements in the region far from the location where the connector is located.

4. The second substrate can be wired on both sides, The semiconductor module according to claim 1 or 2, characterized in that, in the semiconductor element furthest from the connector, the second gate wiring is formed on one side of the second substrate, the second sense wiring is formed on the other side of the second substrate, and the second gate wiring and the second sense wiring are arranged in an overlapping region when viewed in plan.

5. The semiconductor module according to claim 1 or 2, characterized in that the semiconductor module is covered by a case having an opening in the center, and the case is filled with resin.

6. The semiconductor module according to claim 1 or 2, characterized in that the second substrate is a glass epoxy substrate.

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